Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843020
H. Yaich, M. Masmoudi
This article presents a new coders / decoders of images inspired by the retina for wireless sensors networks (WSN). Indeed, the problem of the compression is important for questions of energy saving, in particular for embedded system. We are convinced that a change is necessary in the philosophy which underlies the conception (design) of the coders / decoders of images to end in innovative and successful systems. The main hypothesis in this work is that the retina generates for the visual stimuli a compressed neural code. Our compression scheme is a combination of a compressed neural code of the retina and data compression techniques.
{"title":"A novel bio-inspired coding scheme for wireless sensor networks","authors":"H. Yaich, M. Masmoudi","doi":"10.1109/IDT.2016.7843020","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843020","url":null,"abstract":"This article presents a new coders / decoders of images inspired by the retina for wireless sensors networks (WSN). Indeed, the problem of the compression is important for questions of energy saving, in particular for embedded system. We are convinced that a change is necessary in the philosophy which underlies the conception (design) of the coders / decoders of images to end in innovative and successful systems. The main hypothesis in this work is that the retina generates for the visual stimuli a compressed neural code. Our compression scheme is a combination of a compressed neural code of the retina and data compression techniques.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128460031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843044
Karima Garradhi, N. Hassen, K. Besbes
A new high performance OTA circuit using source degeneration technique and a flipped-voltage follower current mirror is presented. Source-degeneration techniques improve the bias current of the input differential pair when large signals are applied, thus, increasing circuit dynamic characteristics. The OTA is implemented in Tower Jazz 0.18µm TS18SL technology under a ± 0.9V supply voltage. Simulation results show that the OTA achieves a wide differential input range, a good Gm tenability and a low power consumption of 1.2µW. A first order Gm-C filter based on the proposed OTA is designed and simulation results are presented and commented.
提出了一种采用源退化技术和倒转电压跟随器电流镜的高性能OTA电路。当输入大信号时，源退化技术提高了输入差分对的偏置电流，从而提高了电路的动态特性。OTA采用Tower Jazz 0.18µm TS18SL技术，电源电压为±0.9V。仿真结果表明，OTA具有较宽的差分输入范围、良好的Gm可持续性和1.2 μ W的低功耗。基于所提出的OTA设计了一阶Gm-C滤波器，给出了仿真结果并给出了评价。
{"title":"Low-voltage and low-power OTA using source-degeneration technique and its application in Gm-C filter","authors":"Karima Garradhi, N. Hassen, K. Besbes","doi":"10.1109/IDT.2016.7843044","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843044","url":null,"abstract":"A new high performance OTA circuit using source degeneration technique and a flipped-voltage follower current mirror is presented. Source-degeneration techniques improve the bias current of the input differential pair when large signals are applied, thus, increasing circuit dynamic characteristics. The OTA is implemented in Tower Jazz 0.18µm TS18SL technology under a ± 0.9V supply voltage. Simulation results show that the OTA achieves a wide differential input range, a good Gm tenability and a low power consumption of 1.2µW. A first order Gm-C filter based on the proposed OTA is designed and simulation results are presented and commented.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130628166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843033
Abdelkader Ben Amara, E. Pissaloux, Mohamed Atri
Complex image processing algorithms (e.g. Sobel edge detection) combined with higher resolution video streaming, are so computationally and put bigger demands on processing power. Unlike the software solutions, parallel solutions satisfy well these algorithms' performance, but using a programmable logic such as FPGA's can provide us more. Driven by the rapid technological advances, today it's possible to combine a high-speed CPU and an FPGA technology on a single system on Chip (SoC), such as the Xilinx Zynq 7000 series. In this paper, we present a HD video streaming architecture and a Sobel edge detection IP core design and implementation using a high-level synthesis workflow. A HD video with a 1080p resolution streamed from a laptop HDMI interface. The processed videos were displayed by the use of a monitor. For implementation, we used a Digilent ZYBO Zynq ZC7010 based platform and our experimental results will be compared with an NVIDIA M840 GPU.
{"title":"Sobel edge detection system design and integration on an FPGA based HD video streaming architecture","authors":"Abdelkader Ben Amara, E. Pissaloux, Mohamed Atri","doi":"10.1109/IDT.2016.7843033","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843033","url":null,"abstract":"Complex image processing algorithms (e.g. Sobel edge detection) combined with higher resolution video streaming, are so computationally and put bigger demands on processing power. Unlike the software solutions, parallel solutions satisfy well these algorithms' performance, but using a programmable logic such as FPGA's can provide us more. Driven by the rapid technological advances, today it's possible to combine a high-speed CPU and an FPGA technology on a single system on Chip (SoC), such as the Xilinx Zynq 7000 series. In this paper, we present a HD video streaming architecture and a Sobel edge detection IP core design and implementation using a high-level synthesis workflow. A HD video with a 1080p resolution streamed from a laptop HDMI interface. The processed videos were displayed by the use of a monitor. For implementation, we used a Digilent ZYBO Zynq ZC7010 based platform and our experimental results will be compared with an NVIDIA M840 GPU.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"226 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127214399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843064
Sabrine Hamdi, H. Faiedh, C. Souani, K. Besbes
Automatic road signs recognition (RSR) aims to increase the safety for all traffic participants such as drivers and pedestrians. Despite all the significant advances in road sign detection brought by computer vision for driving assistance, it is still a challenging problem. One reason is the extremely varying lighting conditions, namely daytime and nighttime. An automatic system equipped with a camera on the dashboard of the vehicle, must detect and alarms the driver when a road sign is present in poor lighting conditions. Most of existing RSR systems divided the problem into three modules: object detection, shape recognition and content classification. This paper's main objective is to develop an adequate and robust system for road signs detection independent of lighting. The road sign detection is based on the RGB-color space segmentation with an empirically determined threshold. It extracts the relevant red and blue regions in the image with limit values of Bounding Boxes. The extraction algorithm proposed and its performances are tested and discussed in a dataset of real driving scenarios, captured under various weather conditions.
{"title":"A lighting independent vision based system for driver assistance","authors":"Sabrine Hamdi, H. Faiedh, C. Souani, K. Besbes","doi":"10.1109/IDT.2016.7843064","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843064","url":null,"abstract":"Automatic road signs recognition (RSR) aims to increase the safety for all traffic participants such as drivers and pedestrians. Despite all the significant advances in road sign detection brought by computer vision for driving assistance, it is still a challenging problem. One reason is the extremely varying lighting conditions, namely daytime and nighttime. An automatic system equipped with a camera on the dashboard of the vehicle, must detect and alarms the driver when a road sign is present in poor lighting conditions. Most of existing RSR systems divided the problem into three modules: object detection, shape recognition and content classification. This paper's main objective is to develop an adequate and robust system for road signs detection independent of lighting. The road sign detection is based on the RGB-color space segmentation with an empirically determined threshold. It extracts the relevant red and blue regions in the image with limit values of Bounding Boxes. The extraction algorithm proposed and its performances are tested and discussed in a dataset of real driving scenarios, captured under various weather conditions.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123433033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843060
A. Fredj, J. Malek, E. Bourennane
In image and video processing the denoising process is an important step before several processing tasks. This paper presents a Faster Oriented Speckle Reducing Anisotropic Diffusion filter (FOSRAD) method to speed up the processing time and keep a higher quality of image, which can be considered as a modified version of the Oriented Speckle Reducing Anisotropic Diffusion (OSRAD) filter. The OSRAD works very well for denoising images with speckle noise. However, this filter has a powerful computational complexity and is not suitable for real time implementation. In this paper we propose a new scheme for optimizing the processing time based on look ahead decomposition technique. This method leads to dividing the processing time by two. Compared to the conventional OSRAD filter, the proposed filter has the advantage of speeding up the numerical scheme. The simulation result show that the FOSRAD filter improved the execution time by 14× compared to the original OSRAD filter. A comparison measure is given by the metrics like the mean structural similarity index and the peak signal-to-noise ratio.
{"title":"Fast oriented Anisotropic Diffusion filter","authors":"A. Fredj, J. Malek, E. Bourennane","doi":"10.1109/IDT.2016.7843060","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843060","url":null,"abstract":"In image and video processing the denoising process is an important step before several processing tasks. This paper presents a Faster Oriented Speckle Reducing Anisotropic Diffusion filter (FOSRAD) method to speed up the processing time and keep a higher quality of image, which can be considered as a modified version of the Oriented Speckle Reducing Anisotropic Diffusion (OSRAD) filter. The OSRAD works very well for denoising images with speckle noise. However, this filter has a powerful computational complexity and is not suitable for real time implementation. In this paper we propose a new scheme for optimizing the processing time based on look ahead decomposition technique. This method leads to dividing the processing time by two. Compared to the conventional OSRAD filter, the proposed filter has the advantage of speeding up the numerical scheme. The simulation result show that the FOSRAD filter improved the execution time by 14× compared to the original OSRAD filter. A comparison measure is given by the metrics like the mean structural similarity index and the peak signal-to-noise ratio.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126776243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843016
Imed Yehyaoui, T. Frikha, Mohamed Abid, Hassen Drira
Advanced algorithms are used today in multimedia applications and several other fields like wireless communication, medical treatments, defense systems, and a wide variety of consumer applications. These algorithms need more sophisticated systems than ever before. In the wide spreading virtual reality applications and 3D technologies, the need for fast and accurate 3D shape analysis computations, in the ever growing amount of 3D data and scanning systems performance, is steadily growing. In this paper, we propose a hardware acceleration of Elastic riemannian metrics computations for shape analysis used in a 3D face analysis context. The proposed architecture exploit the new concept of Dynamic partial reconfiguration by loading the accelerator in a specified reconfigurable partition, on a Xilinx Zynq-7000 integrated circuit, when needed. The reconfiguration is performed dynamically and partially without blocking or disturbing the rest of the system. The improved hardware acceleration shall enable high-performance computations with lower energy consumption while covering less area on the FPGA.
{"title":"Embedded adaptation for 3D face analysis using Elastic Riemannian algorithm","authors":"Imed Yehyaoui, T. Frikha, Mohamed Abid, Hassen Drira","doi":"10.1109/IDT.2016.7843016","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843016","url":null,"abstract":"Advanced algorithms are used today in multimedia applications and several other fields like wireless communication, medical treatments, defense systems, and a wide variety of consumer applications. These algorithms need more sophisticated systems than ever before. In the wide spreading virtual reality applications and 3D technologies, the need for fast and accurate 3D shape analysis computations, in the ever growing amount of 3D data and scanning systems performance, is steadily growing. In this paper, we propose a hardware acceleration of Elastic riemannian metrics computations for shape analysis used in a 3D face analysis context. The proposed architecture exploit the new concept of Dynamic partial reconfiguration by loading the accelerator in a specified reconfigurable partition, on a Xilinx Zynq-7000 integrated circuit, when needed. The reconfiguration is performed dynamically and partially without blocking or disturbing the rest of the system. The improved hardware acceleration shall enable high-performance computations with lower energy consumption while covering less area on the FPGA.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115649663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843025
Sahar Abdelhedi, M. Baklouti, R. Bourguiba, Jaouhar Mouine
New ultra-low power FPGAs provide system designers the flexibility to create completely customizable low-power solutions to bring new classes of applications to life. Fall detection is one of the major problems the elderly population is facing. This paper aims to present the design of an heterogeneous wearable system built with Zynq System-On-Chip (SoC) for fall detection. The design has been validated on ARM A9 processor for the software side and using Vivado High Level Synthesis (HLS) for hardware implementation on a Zynq-7010 SoC. The implementation results of the fall detection core showed less power consumed and 50% less on-chip logic resources used compared to the software implementation.
新型超低功耗fpga为系统设计人员提供了创建完全可定制的低功耗解决方案的灵活性，从而使新型应用成为现实。跌倒检测是老年人面临的主要问题之一。本文旨在介绍一种基于Zynq系统芯片(SoC)的异构可穿戴跌倒检测系统的设计。该设计已在ARM A9处理器上进行了软件端验证，并在Zynq-7010 SoC上使用Vivado High Level Synthesis (HLS)进行了硬件实现。与软件实现相比，跌落检测核心的实现结果显示功耗更低，片上逻辑资源使用减少50%。
{"title":"Vivado HLS-based implementation of a fall detection decision core on an FPGA platform","authors":"Sahar Abdelhedi, M. Baklouti, R. Bourguiba, Jaouhar Mouine","doi":"10.1109/IDT.2016.7843025","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843025","url":null,"abstract":"New ultra-low power FPGAs provide system designers the flexibility to create completely customizable low-power solutions to bring new classes of applications to life. Fall detection is one of the major problems the elderly population is facing. This paper aims to present the design of an heterogeneous wearable system built with Zynq System-On-Chip (SoC) for fall detection. The design has been validated on ARM A9 processor for the software side and using Vivado High Level Synthesis (HLS) for hardware implementation on a Zynq-7010 SoC. The implementation results of the fall detection core showed less power consumed and 50% less on-chip logic resources used compared to the software implementation.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115397614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843019
Amel Ben Mahjoub, Mohamed Atri
Human action recognition is an important computer vision research area, which is helpful in umpteen applications. This paper presents our method to recognize human activities. We use the Spatio-Temporal Interest Point (STIP) for detection of the important change in the image. Then, we extract appearance and motion features of these interest points using the histogram of Oriented Gradient (HOG) and Histogram of Optical Flow (HOF) descriptors. Finally, we match the Support Vector Machine (SVM) by Bag Of Word (BOW) of the space-time interest point descriptor to give the label of each video sequence. We perform our approach to UTD-MHAD complex dataset and it provides a good action recognition rate. Our proposed algorithm perform better than other methods based on the same sequence data of the public UTD-MHAD database.
{"title":"Human action recognition using RGB data","authors":"Amel Ben Mahjoub, Mohamed Atri","doi":"10.1109/IDT.2016.7843019","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843019","url":null,"abstract":"Human action recognition is an important computer vision research area, which is helpful in umpteen applications. This paper presents our method to recognize human activities. We use the Spatio-Temporal Interest Point (STIP) for detection of the important change in the image. Then, we extract appearance and motion features of these interest points using the histogram of Oriented Gradient (HOG) and Histogram of Optical Flow (HOF) descriptors. Finally, we match the Support Vector Machine (SVM) by Bag Of Word (BOW) of the space-time interest point descriptor to give the label of each video sequence. We perform our approach to UTD-MHAD complex dataset and it provides a good action recognition rate. Our proposed algorithm perform better than other methods based on the same sequence data of the public UTD-MHAD database.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115693996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843048
Maissa Daoud, H. Mnif, M. Ghorbel
A resistive termination low noise amplifier (RTLNA) for biosensor application is presented. The proposed RTLNA consists of merging the block of the input impedance matching with the amplification block to reduce the LNA size. Several techniques are used to reach this goal. The exploitation of the internal capacitors of the CMOS transistors helped us to avoid the use of capacitors. The choice of the resistive termination LNA is explained by the good performances that offers this architecture like high gain, good linearity and stability. The RTLNA comprising only one inductor, resistor and four CMOS transistors without affecting the circuit performances. In the ISM band (2.45GHz) the proposed LNA achieves a maximum voltage gain of about 19.6 dB, a minimum noise figure of 4.8dB and an IIP3 of +4dBm.
{"title":"Resistive termination low noise amplifier for bio-sensor applications","authors":"Maissa Daoud, H. Mnif, M. Ghorbel","doi":"10.1109/IDT.2016.7843048","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843048","url":null,"abstract":"A resistive termination low noise amplifier (RTLNA) for biosensor application is presented. The proposed RTLNA consists of merging the block of the input impedance matching with the amplification block to reduce the LNA size. Several techniques are used to reach this goal. The exploitation of the internal capacitors of the CMOS transistors helped us to avoid the use of capacitors. The choice of the resistive termination LNA is explained by the good performances that offers this architecture like high gain, good linearity and stability. The RTLNA comprising only one inductor, resistor and four CMOS transistors without affecting the circuit performances. In the ISM band (2.45GHz) the proposed LNA achieves a maximum voltage gain of about 19.6 dB, a minimum noise figure of 4.8dB and an IIP3 of +4dBm.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"28 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127208397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843034
Lei Xie, Hoang Anh Du Nguyen, M. Taouil, S. Hamdioui, K. Bertels, M. Alfailakawi
Many emerging technologies are under investigation to realize alternatives for future scalable electronics. Memristor is one of the most promising candidates due to memrsitor's non-volatility, high integration density, near-zero standby power consumption, etc. Memristors have been recently utilized in non-volatile memory, neuromorphic system, resistive computing architecture, and FPGA to name but a few. An FPGA typically consists of configurable logic blocks (CLBs), programmable interconnects, configuration, and block memories. Most of the recent work done was focused on using memristor to build FPGA interconnects and memories. This paper proposes two novel FPGA implementations that utilize memristor-based CLBs and their corresponding automatic design flow. To illustrate the potential of the proposed implementations, they are benchmarked using Toronto 20, and compared with the state-of-the-art in terms of area and delay. The experimental results show that both the area (up to 4.24×) and delay (up to 1.46×) of the novel FPGAs are very promising.
{"title":"Non-volatile look-up table based FPGA implementations","authors":"Lei Xie, Hoang Anh Du Nguyen, M. Taouil, S. Hamdioui, K. Bertels, M. Alfailakawi","doi":"10.1109/IDT.2016.7843034","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843034","url":null,"abstract":"Many emerging technologies are under investigation to realize alternatives for future scalable electronics. Memristor is one of the most promising candidates due to memrsitor's non-volatility, high integration density, near-zero standby power consumption, etc. Memristors have been recently utilized in non-volatile memory, neuromorphic system, resistive computing architecture, and FPGA to name but a few. An FPGA typically consists of configurable logic blocks (CLBs), programmable interconnects, configuration, and block memories. Most of the recent work done was focused on using memristor to build FPGA interconnects and memories. This paper proposes two novel FPGA implementations that utilize memristor-based CLBs and their corresponding automatic design flow. To illustrate the potential of the proposed implementations, they are benchmarked using Toronto 20, and compared with the state-of-the-art in terms of area and delay. The experimental results show that both the area (up to 4.24×) and delay (up to 1.46×) of the novel FPGAs are very promising.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"333 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132302334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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