Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843050
Aymen Ben Hammadi, Mongia Mhiri, F. Haddad, Sehmi Saad, K. Besbes
In this paper, a reconfigurable active bandpass filter (BPF) has been designed and fabricated in a 130 nm CMOS technology to cover a wide tuning of radio-frequencies. The filter is based on active inductor comprising tow control voltages for inductance value, quality factor and central frequency tenability. Throughout the wide frequency range (1.82–4.44 GHz), the BPF achieves an average insertion loss of 9.27 ± 0.37 dB and a noise figure between 11.03 and 9.1 dB. Operating at supply voltage of 1 V, the circuit consumes 2.27–2.72 mW and occupies only 390×400 µm2 chip area.
{"title":"A 1.82–4.44 GHz reconfigurable bandpass filter based on tunable active inductor","authors":"Aymen Ben Hammadi, Mongia Mhiri, F. Haddad, Sehmi Saad, K. Besbes","doi":"10.1109/IDT.2016.7843050","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843050","url":null,"abstract":"In this paper, a reconfigurable active bandpass filter (BPF) has been designed and fabricated in a 130 nm CMOS technology to cover a wide tuning of radio-frequencies. The filter is based on active inductor comprising tow control voltages for inductance value, quality factor and central frequency tenability. Throughout the wide frequency range (1.82–4.44 GHz), the BPF achieves an average insertion loss of 9.27 ± 0.37 dB and a noise figure between 11.03 and 9.1 dB. Operating at supply voltage of 1 V, the circuit consumes 2.27–2.72 mW and occupies only 390×400 µm2 chip area.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130114179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843021
Haytham Ashour
System-on-Chip (SoC) Verification is becoming a challenge in nowadays chips. Hardware acceleration is becoming mandatory in SoC verification. Emulation enables longer test cases and more tests to run in less time. However, emulation based verification is still not supporting verification of analog modules. These analog modules are parts of the Physical Layer (PHY) of the Designs-Under-Test (DUT) which includes some digital modules as well to interface with upper layers in the protocol and to control analog modules. So, there is a need to develop emulator friendly physical layers of different protocols to enable emulation based verification. These PHY modules should be flexible enough to cover different configurations of the designs under test. This paper presents how to enable emulation based verification of a full Serial ATA protocol (SATA) controller designs, used in storage applications, using a SATA Verification IP (VIP) and Configurable SATA PHY design.
{"title":"Challenges in serial protocols Verification on an emulation environment (SATA as an example)","authors":"Haytham Ashour","doi":"10.1109/IDT.2016.7843021","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843021","url":null,"abstract":"System-on-Chip (SoC) Verification is becoming a challenge in nowadays chips. Hardware acceleration is becoming mandatory in SoC verification. Emulation enables longer test cases and more tests to run in less time. However, emulation based verification is still not supporting verification of analog modules. These analog modules are parts of the Physical Layer (PHY) of the Designs-Under-Test (DUT) which includes some digital modules as well to interface with upper layers in the protocol and to control analog modules. So, there is a need to develop emulator friendly physical layers of different protocols to enable emulation based verification. These PHY modules should be flexible enough to cover different configurations of the designs under test. This paper presents how to enable emulation based verification of a full Serial ATA protocol (SATA) controller designs, used in storage applications, using a SATA Verification IP (VIP) and Configurable SATA PHY design.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130965322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843055
Eman El Mandouh, A. Wassal
As the size and the complexity of today's HW designs increase significantly, the debugging process becomes a real bottleneck in the function verification life cycle. A huge amount of debugging data is generated during HW design simulation, emulation and prototyping sessions. So any attempt to automate the diagnosis of the resulted data can be of great help to reduce the debugging time and increase the diagnosis accuracy. This paper proposes the utilization of machine learning techniques to automate the diagnosis of design trace history. k-means clustering technique is used to group the trace segments that own huge similarity and identify the ones that occur rarely during the design execution time. We demonstrate the application of the proposed framework in guiding the functional verification debugging effort using a group of industrial HW designs.
{"title":"Accelerating the debugging of FV traces using K-means clustering techniques","authors":"Eman El Mandouh, A. Wassal","doi":"10.1109/IDT.2016.7843055","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843055","url":null,"abstract":"As the size and the complexity of today's HW designs increase significantly, the debugging process becomes a real bottleneck in the function verification life cycle. A huge amount of debugging data is generated during HW design simulation, emulation and prototyping sessions. So any attempt to automate the diagnosis of the resulted data can be of great help to reduce the debugging time and increase the diagnosis accuracy. This paper proposes the utilization of machine learning techniques to automate the diagnosis of design trace history. k-means clustering technique is used to group the trace segments that own huge similarity and identify the ones that occur rarely during the design execution time. We demonstrate the application of the proposed framework in guiding the functional verification debugging effort using a group of industrial HW designs.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"8 Pt 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126271365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843032
M. Makni, M. Baklouti, S. Niar, M. W. Jmal, M. Abid
Field Programmable Gate Arrays (FPGAs) are increasingly being considered as an effective solution to cope with current performance requirements of embedded systems due to their reconfigurability, scalability and their lower cost solution. The increasing configurable logic capacity of the FPGA has enabled designers to integrate a large number of soft-core processors into FPGA devices. Evaluating the performance of existing soft-cores presents a great challenge for designers to select the most efficient and the suitable soft-core for a specific software application. This paper presents an overview of soft-core processors that are used in embedded systems. We compare different open-source and commercial soft-cores such as openFire, LEON3, Microblaze, etc, based on major architectural features. We also evaluate the impact of the selected soft-core processors on the total execution time and the FPGA area consumption using different applications.
{"title":"A comparison and performance evaluation of FPGA soft-cores for embedded multi-core systems","authors":"M. Makni, M. Baklouti, S. Niar, M. W. Jmal, M. Abid","doi":"10.1109/IDT.2016.7843032","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843032","url":null,"abstract":"Field Programmable Gate Arrays (FPGAs) are increasingly being considered as an effective solution to cope with current performance requirements of embedded systems due to their reconfigurability, scalability and their lower cost solution. The increasing configurable logic capacity of the FPGA has enabled designers to integrate a large number of soft-core processors into FPGA devices. Evaluating the performance of existing soft-cores presents a great challenge for designers to select the most efficient and the suitable soft-core for a specific software application. This paper presents an overview of soft-core processors that are used in embedded systems. We compare different open-source and commercial soft-cores such as openFire, LEON3, Microblaze, etc, based on major architectural features. We also evaluate the impact of the selected soft-core processors on the total execution time and the FPGA area consumption using different applications.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122781673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843026
Ratshih S. Abd El-Azeem, M. El-Moursy, A. Nassar, A. Gharib, Nahla T. Abou-El-Kheir, Moataz S. El-Kharashi
A Computational Filter (CF) that employs a sample calculation functional block is presented. CF significantly reduces the hardware requirements to realize an interpolation filter. The Computational Filter is compared with advanced Finite Impulse Response (CFIR). CFIR programmable filter is implemented using Computation Sharing Multiplication (CSHM) technique to optimize the conventional design. The proposed CF significantly reduces the implementation area as compared to CFIR. The maximum average error for wide range of interpolation factors from 8 to 256 is less than 3% for CF and 0.02 %for CFIR. Xilinx Virtex5 FPGA XC5VTX240T device is used to compare the proposed design and the advanced CFIR for different interpolation factors. The Computational Filter average reduction in hardware implementation is between 78.8 % and 97.1% for interpolation factor of 8 to 64. The maximum operating frequency for the CFIR is 1 MHZ.
{"title":"High performance interpolation filter using direct computation","authors":"Ratshih S. Abd El-Azeem, M. El-Moursy, A. Nassar, A. Gharib, Nahla T. Abou-El-Kheir, Moataz S. El-Kharashi","doi":"10.1109/IDT.2016.7843026","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843026","url":null,"abstract":"A Computational Filter (CF) that employs a sample calculation functional block is presented. CF significantly reduces the hardware requirements to realize an interpolation filter. The Computational Filter is compared with advanced Finite Impulse Response (CFIR). CFIR programmable filter is implemented using Computation Sharing Multiplication (CSHM) technique to optimize the conventional design. The proposed CF significantly reduces the implementation area as compared to CFIR. The maximum average error for wide range of interpolation factors from 8 to 256 is less than 3% for CF and 0.02 %for CFIR. Xilinx Virtex5 FPGA XC5VTX240T device is used to compare the proposed design and the advanced CFIR for different interpolation factors. The Computational Filter average reduction in hardware implementation is between 78.8 % and 97.1% for interpolation factor of 8 to 64. The maximum operating frequency for the CFIR is 1 MHZ.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115739479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843009
Imen Ben Ida, A. Jemai, A. Loukil
The technology of Internet of Things (IoT) and cloud has exposed devices to vulnerabilities. As they are distributed, the different devices communicate real time information to open, private or hybrid clouds, with the possibility of collecting, storing and analyzing big data streams in new forms. In the healthcare context, the increased deployment of IoT devices makes patient information a subject to malicious attacks depending on the security and privacy of the IoT devices. While a number of researchers have explored such security challenges and open problems in IoT, there is an unfortunate lack of a systematic study of the security challenges in the IoT for eHealth on clouds. In this paper, we aim at bridging this gap by conducting a thorough analysis of IoT security Vulnerability. We present then security challenges in the cloud for eHealth domain and recent proposed solutions. We also provide a proposition of an IoT system in the cloud.
{"title":"A survey on security of IoT in the context of eHealth and clouds","authors":"Imen Ben Ida, A. Jemai, A. Loukil","doi":"10.1109/IDT.2016.7843009","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843009","url":null,"abstract":"The technology of Internet of Things (IoT) and cloud has exposed devices to vulnerabilities. As they are distributed, the different devices communicate real time information to open, private or hybrid clouds, with the possibility of collecting, storing and analyzing big data streams in new forms. In the healthcare context, the increased deployment of IoT devices makes patient information a subject to malicious attacks depending on the security and privacy of the IoT devices. While a number of researchers have explored such security challenges and open problems in IoT, there is an unfortunate lack of a systematic study of the security challenges in the IoT for eHealth on clouds. In this paper, we aim at bridging this gap by conducting a thorough analysis of IoT security Vulnerability. We present then security challenges in the cloud for eHealth domain and recent proposed solutions. We also provide a proposition of an IoT system in the cloud.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"374 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115785806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843002
R. Leveugle
Integrated embedded systems are increasingly used in many applications, including critical ones. The fast growing Internet-of-Things markets still increase concerns about reliability, safety and security. Circuits made in up-to-date technologies are more sensitive to perturbations, in spite of manufacturing progress, due to the number of functions implemented in a single chip. Malicious attacks are based on creating errors to take the control of a system and/or steal private data. In this context, an increasing number of designers need to take care, early in the design flow, of consequences of soft errors (i.e., errors in the processed data, without physical defect induced in the chip).
{"title":"Tutorial 1: “New approaches towards early dependability evaluation of digital integrated systems”","authors":"R. Leveugle","doi":"10.1109/IDT.2016.7843002","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843002","url":null,"abstract":"Integrated embedded systems are increasingly used in many applications, including critical ones. The fast growing Internet-of-Things markets still increase concerns about reliability, safety and security. Circuits made in up-to-date technologies are more sensitive to perturbations, in spite of manufacturing progress, due to the number of functions implemented in a single chip. Malicious attacks are based on creating errors to take the control of a system and/or steal private data. In this context, an increasing number of designers need to take care, early in the design flow, of consequences of soft errors (i.e., errors in the processed data, without physical defect induced in the chip).","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126911042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843014
A. Obeid, M. BenSaleh, Mohamed I. Alkanhal, A. Shalash, M. Abid
Reconfigurable technologies offer solutions to important requirements such as time to market and adaptability. Furthermore, reconfigurable technologies introduced new concepts and opportunities that were not known before. In this work, we introduce basic reconfigurable technology concepts and introduce selected examples of course-grained reconfigurable solutions with emphasis on WaCASIP SW contributions. We then propose a methodology for Reconfigurable Computing solitons design. The design methodology attempts to find balance between design requirements, VLSI techniques and reconfigurations features.
{"title":"A proposed methodology for designing reconfigurable solutions","authors":"A. Obeid, M. BenSaleh, Mohamed I. Alkanhal, A. Shalash, M. Abid","doi":"10.1109/IDT.2016.7843014","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843014","url":null,"abstract":"Reconfigurable technologies offer solutions to important requirements such as time to market and adaptability. Furthermore, reconfigurable technologies introduced new concepts and opportunities that were not known before. In this work, we introduce basic reconfigurable technology concepts and introduce selected examples of course-grained reconfigurable solutions with emphasis on WaCASIP SW contributions. We then propose a methodology for Reconfigurable Computing solitons design. The design methodology attempts to find balance between design requirements, VLSI techniques and reconfigurations features.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127028571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843024
Haytham Saafan, M. El-Kharashi, A. Salem
Component reuse, complex buses and input/output connections add challenges to the SoC integration process. A large percentage of design integration errors comes from connectivity errors that may come from the connectivity specification or the SoC code generation scripts or both. Defining or documenting SoC connectivity is an error prone task by itself. SoC designers may use a standard for documenting SoC like IP-XACT, or have their own customized spreadsheets for describing the pin level connections, or they may not be using any method to specify SoC connectivity. This paper describes two approaches that enable SoC design and integration engineers with no connectivity specification to use Formal Verification to easily validate the connections on the SoC.
{"title":"SoC connectivity specification extraction using incomplete RTL design: An approach for Formal connectivity Verification","authors":"Haytham Saafan, M. El-Kharashi, A. Salem","doi":"10.1109/IDT.2016.7843024","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843024","url":null,"abstract":"Component reuse, complex buses and input/output connections add challenges to the SoC integration process. A large percentage of design integration errors comes from connectivity errors that may come from the connectivity specification or the SoC code generation scripts or both. Defining or documenting SoC connectivity is an error prone task by itself. SoC designers may use a standard for documenting SoC like IP-XACT, or have their own customized spreadsheets for describing the pin level connections, or they may not be using any method to specify SoC connectivity. This paper describes two approaches that enable SoC design and integration engineers with no connectivity specification to use Formal Verification to easily validate the connections on the SoC.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124035053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843040
S. H. Sfar, R. Tourki, I. Bennour
Transaction level modelling (TLM) is among the most promising electronic system level (ESL) methodologies to handle the growing complexity of ESL designs. The last SystemC standard incorporates TLM concepts by adding the TLM-2 library. It places de facto SystemC and TLM-2 library as a standard when writing transaction level (TL) models. Standard establishment is a corner stone to pass to next logical steps that are transaction-level synthesis and electronic design automation. Nevertheless, good practice in writing and simulating systems at transaction level must be adopted to bring up more elaborated semantics of each TL model. We write this paper in this sense. Through guideline example, we expose techniques to write well-structured and modular TL models that help to explore and optimize the system architecture.
{"title":"Stepwise SystemC/TLM-2 models structuring and optimizations","authors":"S. H. Sfar, R. Tourki, I. Bennour","doi":"10.1109/IDT.2016.7843040","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843040","url":null,"abstract":"Transaction level modelling (TLM) is among the most promising electronic system level (ESL) methodologies to handle the growing complexity of ESL designs. The last SystemC standard incorporates TLM concepts by adding the TLM-2 library. It places de facto SystemC and TLM-2 library as a standard when writing transaction level (TL) models. Standard establishment is a corner stone to pass to next logical steps that are transaction-level synthesis and electronic design automation. Nevertheless, good practice in writing and simulating systems at transaction level must be adopted to bring up more elaborated semantics of each TL model. We write this paper in this sense. Through guideline example, we expose techniques to write well-structured and modular TL models that help to explore and optimize the system architecture.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131994768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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