Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843013
Mohamed Abdelsalam
Hardware-assisted verification, or emulation, delivers the capacity and performance for extremely fast, full System on Chip (SoC) testing. Emulation enables realistic software execution, longer test cases and more tests to be run in less time. In doing so, it allows more design requirements to be covered while more bugs are uncovered. Recently, introducing Virtual Devices methodology expanded the landscape beyond these two fundamental benefits in terms of what can be accomplished virtually with an emulator. As a result, leading electronic-design companies want to take advantage of the benefits of both megahertz verification and a fully virtual accelerated verification flow. In this paper, we present a Non-Volatile Memory Express (NVMe) Solid State Drive (SSD) verification solution that has been built using these two enabling technologies.
{"title":"NVMe Solid State Drive verification solution using HW Emulation and Virtual Device Technologies","authors":"Mohamed Abdelsalam","doi":"10.1109/IDT.2016.7843013","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843013","url":null,"abstract":"Hardware-assisted verification, or emulation, delivers the capacity and performance for extremely fast, full System on Chip (SoC) testing. Emulation enables realistic software execution, longer test cases and more tests to be run in less time. In doing so, it allows more design requirements to be covered while more bugs are uncovered. Recently, introducing Virtual Devices methodology expanded the landscape beyond these two fundamental benefits in terms of what can be accomplished virtually with an emulator. As a result, leading electronic-design companies want to take advantage of the benefits of both megahertz verification and a fully virtual accelerated verification flow. In this paper, we present a Non-Volatile Memory Express (NVMe) Solid State Drive (SSD) verification solution that has been built using these two enabling technologies.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133044326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843022
Ahmed El-Naggar, Essraa Massoud, A. Medhat, Hala Ibrahim, Bassma Al-Abassy, Sameh El-Ashry, Mostafa Khamis, A. Shalaby
In contrast to past projections using conventional bus-based interconnections, the use of Network on Chip (NoC) as an interconnection platform has become more promising to solve complex on-chip communication problems due to what it offers from scalability, reusability and efficiency. Moreover, providing a suitable test base to inspect and verify functionality of any IP core is a compulsory stage. To elaborate; Universal Verification Methodology (UVM) is introduced as a standardized and reusable methodology for verifying integrated circuit designs. In this paper, we present an architecture of a complete UVM environment to test generic routers through various test cases providing different scenarios to be applied. We also aim to establish a base on which other researchers can build to proceed towards finding better solutions.
{"title":"A narrative of UVM testbench environment for interconnection routers: A practical approach","authors":"Ahmed El-Naggar, Essraa Massoud, A. Medhat, Hala Ibrahim, Bassma Al-Abassy, Sameh El-Ashry, Mostafa Khamis, A. Shalaby","doi":"10.1109/IDT.2016.7843022","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843022","url":null,"abstract":"In contrast to past projections using conventional bus-based interconnections, the use of Network on Chip (NoC) as an interconnection platform has become more promising to solve complex on-chip communication problems due to what it offers from scalability, reusability and efficiency. Moreover, providing a suitable test base to inspect and verify functionality of any IP core is a compulsory stage. To elaborate; Universal Verification Methodology (UVM) is introduced as a standardized and reusable methodology for verifying integrated circuit designs. In this paper, we present an architecture of a complete UVM environment to test generic routers through various test cases providing different scenarios to be applied. We also aim to establish a base on which other researchers can build to proceed towards finding better solutions.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114211054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843005
K. Smiri, Safa Bekri, Habib Smei
Multiprocessor Systems-on-Chip (MPSoC) allow the implementation of heterogeneous architectures with a high integration capacity. In recent years, computational requirements MPSoC are increasing exponentially. This complexity, coupled with constantly evolving specifications, has forced designers to consider intrinsically flexible implementations. Deploying applications typical of multimedia domains is difficult, not only due to the heterogeneous parallelism in the platforms, but also due to the performance constraints that typify these systems. An application can be modeled as a set of cooperative tasks. A task can be implemented in software or in hardware depending on its complexity and the involved cost. Our proposal is a fault tolerance approach which combines the results of a performance model and a technical's fault tolerance. We interest of the dynamic migration task to resolve the Fault-Tolerant for Multiprocessors Embedded System.
{"title":"Fault-Tolerant in Embedded Systems (MPSoC): Performance estimation and dynamic migration tasks","authors":"K. Smiri, Safa Bekri, Habib Smei","doi":"10.1109/IDT.2016.7843005","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843005","url":null,"abstract":"Multiprocessor Systems-on-Chip (MPSoC) allow the implementation of heterogeneous architectures with a high integration capacity. In recent years, computational requirements MPSoC are increasing exponentially. This complexity, coupled with constantly evolving specifications, has forced designers to consider intrinsically flexible implementations. Deploying applications typical of multimedia domains is difficult, not only due to the heterogeneous parallelism in the platforms, but also due to the performance constraints that typify these systems. An application can be modeled as a set of cooperative tasks. A task can be implemented in software or in hardware depending on its complexity and the involved cost. Our proposal is a fault tolerance approach which combines the results of a performance model and a technical's fault tolerance. We interest of the dynamic migration task to resolve the Fault-Tolerant for Multiprocessors Embedded System.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126794570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843006
Habib Smei, K. Smiri, A. Jemai
For different applications like high quality Internet video, mobile video or digital TV, efficient coding of video signals is required to meet technical constraints as bandwidth, latency or execution time. To cope with these constraints and the growing demand in terms of resolution and quality as HD, Quad-HD and UHD videos, more efficient coding is required. For that, the h.265 HEVC (High Efficiency Video Coding) is developed by JCT-VC to substitute to MPEG-2, MPEG-4 and h.264 codecs.
对于高质量的互联网视频、移动视频或数字电视等不同的应用，需要对视频信号进行高效编码，以满足带宽、延迟或执行时间等技术限制。为了应对这些限制以及高清、四清和超高清视频在分辨率和质量方面日益增长的需求，需要更高效的编码。为此，h.265HEVC (High Efficiency Video Coding)是JCT-VC为替代MPEG-2、MPEG-4和h.264编解码器而开发的。
{"title":"Pipelining the HEVC decoder on ZedBoard plateform","authors":"Habib Smei, K. Smiri, A. Jemai","doi":"10.1109/IDT.2016.7843006","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843006","url":null,"abstract":"For different applications like high quality Internet video, mobile video or digital TV, efficient coding of video signals is required to meet technical constraints as bandwidth, latency or execution time. To cope with these constraints and the growing demand in terms of resolution and quality as HD, Quad-HD and UHD videos, more efficient coding is required. For that, the h.265 HEVC (High Efficiency Video Coding) is developed by JCT-VC to substitute to MPEG-2, MPEG-4 and h.264 codecs.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131423794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843046
Khaled El-Kenawy, M. Dessouky
This paper presents a stress-aware transistors layout pattern generation flow. For a given set of transistors with different finger unit ratios, and a set of user specified devices pattern together with the DC operating point for each device in the pattern, an Absolute Mismatch Factor (AMF) is provided. AMF presents the degree of matching between the devices in the pattern taking Shallow Trench Isolation (STI) into consideration. Multiple stacks are placed in a matrix-like layout recommended by recent technology nodes. The flow goal is to help the designer achieve a pattern with minimum AMF i.e. best matching, while avoiding multiple expensive iterations of layout design, extraction and post-layout simulations. Examples include multi-finger current mirror designs in a 65nm process. Post-layout simulations are finally used to demonstrate the results.
{"title":"Stress-aware analog layout devices pattern generation","authors":"Khaled El-Kenawy, M. Dessouky","doi":"10.1109/IDT.2016.7843046","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843046","url":null,"abstract":"This paper presents a stress-aware transistors layout pattern generation flow. For a given set of transistors with different finger unit ratios, and a set of user specified devices pattern together with the DC operating point for each device in the pattern, an Absolute Mismatch Factor (AMF) is provided. AMF presents the degree of matching between the devices in the pattern taking Shallow Trench Isolation (STI) into consideration. Multiple stacks are placed in a matrix-like layout recommended by recent technology nodes. The flow goal is to help the designer achieve a pattern with minimum AMF i.e. best matching, while avoiding multiple expensive iterations of layout design, extraction and post-layout simulations. Examples include multi-finger current mirror designs in a 65nm process. Post-layout simulations are finally used to demonstrate the results.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"83 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120892807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843027
Lydie Terras, Y. Teglia, M. Agoyan, R. Leveugle
Control-flow checking (CFC) is one of the main approaches to monitor the behavior of a microprocessor-based system without specific assumptions on error models (e.g., single bit flips). Many approaches have been proposed and evaluated, but none takes explicitly into account the possibility of indirect jumps or calls for which destination addresses are not hard-coded. This paper discusses first the need for an approach taking care of such sequence breaks. Then an approach is proposed to enhance current control-flow checking schemes.
{"title":"Taking into account indirect jumps or calls in continuous control-flow checking","authors":"Lydie Terras, Y. Teglia, M. Agoyan, R. Leveugle","doi":"10.1109/IDT.2016.7843027","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843027","url":null,"abstract":"Control-flow checking (CFC) is one of the main approaches to monitor the behavior of a microprocessor-based system without specific assumptions on error models (e.g., single bit flips). Many approaches have been proposed and evaluated, but none takes explicitly into account the possibility of indirect jumps or calls for which destination addresses are not hard-coded. This paper discusses first the need for an approach taking care of such sequence breaks. Then an approach is proposed to enhance current control-flow checking schemes.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134529900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843059
Wajdi Farhat, H. Faiedh, C. Souani, K. Besbes
This paper describes a hardware implementation for real-time road signs recognition system on automotive oriented FPGA. The proposed traffic sign recognition system is based on color segmentation and Template Matching. This architecture is implemented on FPGA device of ZYNQ 7020 Xilinx family. Therefore, a software/hardware co-design architecture for a Zynq-7020 FPGA is presented as a primary objective of this work. Results show that the proposed system achieves over 97% accuracy even in difficult condition weather. In addition, in this work, a hardware implementation of the proposed system will be presented to achieve real-time constraints.
{"title":"Real-time hardware/software co-design of a traffic sign recognition system using Zynq FPGA","authors":"Wajdi Farhat, H. Faiedh, C. Souani, K. Besbes","doi":"10.1109/IDT.2016.7843059","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843059","url":null,"abstract":"This paper describes a hardware implementation for real-time road signs recognition system on automotive oriented FPGA. The proposed traffic sign recognition system is based on color segmentation and Template Matching. This architecture is implemented on FPGA device of ZYNQ 7020 Xilinx family. Therefore, a software/hardware co-design architecture for a Zynq-7020 FPGA is presented as a primary objective of this work. Results show that the proposed system achieves over 97% accuracy even in difficult condition weather. In addition, in this work, a hardware implementation of the proposed system will be presented to achieve real-time constraints.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128675939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843030
P. L. Thangkhiew, Rahul Gharpinde, Varun Chowdhary Paturi, K. Datta, I. Sengupta
Memristor has drawn the attention of circuit designers for its non-volatility, and is considered as a viable candidate to replace CMOS technology in many applications. Another interesting characteristic of memristor is that it can be employed in crossbar array architecture that allows very high packing density. In addition to implementing high capacity storage systems, memristor can also be used to realize logic functions. In this paper, the Memristor Aided Logic (MAGIC) design style is used to map the NOR netlist of a given Boolean function to memristor crossbar arrays. Various optimization techniques have been used by scheduling the NOR gates to time steps in order to reduce the hardware cost. To illustrate the viability of the design methodology, full adder and ripple carry adder circuits have been studied and analyzed.
{"title":"Area efficient implementation of ripple carry adder using memristor crossbar arrays","authors":"P. L. Thangkhiew, Rahul Gharpinde, Varun Chowdhary Paturi, K. Datta, I. Sengupta","doi":"10.1109/IDT.2016.7843030","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843030","url":null,"abstract":"Memristor has drawn the attention of circuit designers for its non-volatility, and is considered as a viable candidate to replace CMOS technology in many applications. Another interesting characteristic of memristor is that it can be employed in crossbar array architecture that allows very high packing density. In addition to implementing high capacity storage systems, memristor can also be used to realize logic functions. In this paper, the Memristor Aided Logic (MAGIC) design style is used to map the NOR netlist of a given Boolean function to memristor crossbar arrays. Various optimization techniques have been used by scheduling the NOR gates to time steps in order to reduce the hardware cost. To illustrate the viability of the design methodology, full adder and ripple carry adder circuits have been studied and analyzed.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134268571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843037
Rania Mzid, M. Abid
Model-based approaches for the development of software intensive real-time embedded systems allow early verification of timing properties at the design phase. In order to perform such verification, some aspects of the target software platform (i.e. the Real-Time Operating System (RTOS)) need to be considered such as priorities, scheduling policies, etc. However, one of the basic principles of model-based approaches, is to keep RTOS-independence of the design model. Hence, some assumptions on the software platform are implicitly made to achieve timing verification. This approach may lead to a mismatch between the design model and the RTOS-specific model describing the real-time application and thus, at the implementation level, timing properties may be affected. To tackle this issue, we define in this paper a reconfigurable middleware called RT-Mw. This middleware aims to explicitly describe the software assumptions at the design level for timing verification. Such approach allows early verification of these assumptions before the effective deployment which may prevents the mismatch between the design and the RTOS-Specific models. RT-Mw is described using UML modeling language together with the MARTE Standard.
{"title":"UML-based reconfigurable middleware for design-level timing verification in model-based approach","authors":"Rania Mzid, M. Abid","doi":"10.1109/IDT.2016.7843037","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843037","url":null,"abstract":"Model-based approaches for the development of software intensive real-time embedded systems allow early verification of timing properties at the design phase. In order to perform such verification, some aspects of the target software platform (i.e. the Real-Time Operating System (RTOS)) need to be considered such as priorities, scheduling policies, etc. However, one of the basic principles of model-based approaches, is to keep RTOS-independence of the design model. Hence, some assumptions on the software platform are implicitly made to achieve timing verification. This approach may lead to a mismatch between the design model and the RTOS-specific model describing the real-time application and thus, at the implementation level, timing properties may be affected. To tackle this issue, we define in this paper a reconfigurable middleware called RT-Mw. This middleware aims to explicitly describe the software assumptions at the design level for timing verification. Such approach allows early verification of these assumptions before the effective deployment which may prevents the mismatch between the design and the RTOS-Specific models. RT-Mw is described using UML modeling language together with the MARTE Standard.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127294010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843011
N. Gamal, H. Fahmy, Y. Ismail, Tawfik Ismail, M. M. El-Din, H. Mostafa
To overcome point-to-point interconnect obstacles, Networks-on-Chips (NoCs) within FPGAs have been introduced. NoCs provide independent interfaces of communication which lead to increasing design scalability and improving its efficiency. We analyze area, delay and power gaps between soft and hard implementations on FPGA-specific NoC; and target two different configurations in soft implementation. The first configuration targets reducing the delay gap by a factor of 5.5é between soft and hard implementations at the expense of increasing the power gap to be a factor of 12.2×. The second configuration is more suitable for applications that are concerned with power saving. It reduces the power gap to a factor of 4.5× with a small increase in the delay gab by a factor of 6.3× and the area gap is increased from 5.9× to 6.9×.
{"title":"Design guidelines for soft implementations to embedded NoCs of FPGAs","authors":"N. Gamal, H. Fahmy, Y. Ismail, Tawfik Ismail, M. M. El-Din, H. Mostafa","doi":"10.1109/IDT.2016.7843011","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843011","url":null,"abstract":"To overcome point-to-point interconnect obstacles, Networks-on-Chips (NoCs) within FPGAs have been introduced. NoCs provide independent interfaces of communication which lead to increasing design scalability and improving its efficiency. We analyze area, delay and power gaps between soft and hard implementations on FPGA-specific NoC; and target two different configurations in soft implementation. The first configuration targets reducing the delay gap by a factor of 5.5é between soft and hard implementations at the expense of increasing the power gap to be a factor of 12.2×. The second configuration is more suitable for applications that are concerned with power saving. It reduces the power gap to a factor of 4.5× with a small increase in the delay gab by a factor of 6.3× and the area gap is increased from 5.9× to 6.9×.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132652000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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