Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843056
I. Frigui, M. S. Karoui, H. Ghariani
The goal of this communication is to present a comparison between three dipole folded passive ultra-high frequency (UHF) tag antennas: a common dipole meander and two others with respectively square and triangular additional bends. The results demonstrate that the modified tag structures are a good alternative for a significant size reduction and they ensure dual-band antenna functionality as well. All designed tag antennas maintain the radiation patterns characteristics of the dipole antenna but they have different impacts on reflection coefficient, bandwidth and gain. Ultimately, the preferred structure is the most appropriate for the application.
{"title":"A study of the bends effects on a meandered dipole tag antenna","authors":"I. Frigui, M. S. Karoui, H. Ghariani","doi":"10.1109/IDT.2016.7843056","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843056","url":null,"abstract":"The goal of this communication is to present a comparison between three dipole folded passive ultra-high frequency (UHF) tag antennas: a common dipole meander and two others with respectively square and triangular additional bends. The results demonstrate that the modified tag structures are a good alternative for a significant size reduction and they ensure dual-band antenna functionality as well. All designed tag antennas maintain the radiation patterns characteristics of the dipole antenna but they have different impacts on reflection coefficient, bandwidth and gain. Ultimately, the preferred structure is the most appropriate for the application.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121528063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843057
H. Almabrouk, Maha Kharroubi, Fares Tounsi, B. Mezghani, Y. Bernard
In this paper, a preliminary analysis of a 6-axis micromachined Inertial Measurement Unit (IMU) structure is performed. We firstly give a review of current approaches found in literature for 6-axis IMU sensor technology. Then, we present and analyze the proposed single mass macro model structure. We mainly investigate the simultaneous detection of all possible six axis motion components with a single bloc based on SMSD approach. The angular velocity detection method is based on the Coriolis Effect which requires a certain translation applied to a suspended mass attached to a piezoelectric membrane. Two methods have been examined: first one is based on the Eigenfrequencies of the membrane, and second one is based on the inverse piezoelectric effect to actuate the membrane. So, electrodes deposited on the piezoelectric membrane are employed for sensing and actuating mechanisms based on direct/reverse piezoelectric effects. As a primary investigation, a modal analysis of the IMU macro model consisting of a piezoelectric Buzzer is presented. FEM simulations and measurement values show a good agreement. Applied stress on the membrane submitted to a linear acceleration is evaluated and improved designs, allowing 3 to 4 times higher stress values, are investigated.
{"title":"Macro model analysis of a single mass 6-DOF Inertial Measurement Unit system","authors":"H. Almabrouk, Maha Kharroubi, Fares Tounsi, B. Mezghani, Y. Bernard","doi":"10.1109/IDT.2016.7843057","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843057","url":null,"abstract":"In this paper, a preliminary analysis of a 6-axis micromachined Inertial Measurement Unit (IMU) structure is performed. We firstly give a review of current approaches found in literature for 6-axis IMU sensor technology. Then, we present and analyze the proposed single mass macro model structure. We mainly investigate the simultaneous detection of all possible six axis motion components with a single bloc based on SMSD approach. The angular velocity detection method is based on the Coriolis Effect which requires a certain translation applied to a suspended mass attached to a piezoelectric membrane. Two methods have been examined: first one is based on the Eigenfrequencies of the membrane, and second one is based on the inverse piezoelectric effect to actuate the membrane. So, electrodes deposited on the piezoelectric membrane are employed for sensing and actuating mechanisms based on direct/reverse piezoelectric effects. As a primary investigation, a modal analysis of the IMU macro model consisting of a piezoelectric Buzzer is presented. FEM simulations and measurement values show a good agreement. Applied stress on the membrane submitted to a linear acceleration is evaluated and improved designs, allowing 3 to 4 times higher stress values, are investigated.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124622073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843018
Geoffroy Pertuisot, N. Bélanger, Y. Elhillali, S. Niar, A. Rivenq
Avionics in the helicopter manufacturers' landscape faces new challenges. Whereas customers raise continuously their needs in terms of new functions and embedded systems performances, certification authorities maintain complex rules to fulfill for parallel computing. This constraining situation has conducted avionics professionals to consider heterogeneous architectures for avionics as a growing trend. The complexity of such architectures combined with the large number of embedded applications to integrate puts under light the need of new approaches to optimize the mapping of task on heterogeneous processing. In the present paper, we explain how a co-design method could meet avionics requirements with a specific co-design architecture exploration and the task's granularity tuning. An implementation of the proposed avionics co-design system is also proposed.
{"title":"A co-design space exploration tool for avionic high performance heterogeneous embedded architectures","authors":"Geoffroy Pertuisot, N. Bélanger, Y. Elhillali, S. Niar, A. Rivenq","doi":"10.1109/IDT.2016.7843018","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843018","url":null,"abstract":"Avionics in the helicopter manufacturers' landscape faces new challenges. Whereas customers raise continuously their needs in terms of new functions and embedded systems performances, certification authorities maintain complex rules to fulfill for parallel computing. This constraining situation has conducted avionics professionals to consider heterogeneous architectures for avionics as a growing trend. The complexity of such architectures combined with the large number of embedded applications to integrate puts under light the need of new approaches to optimize the mapping of task on heterogeneous processing. In the present paper, we explain how a co-design method could meet avionics requirements with a specific co-design architecture exploration and the task's granularity tuning. An implementation of the proposed avionics co-design system is also proposed.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124550726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843058
Maissa Daoud, H. Mnif, M. Ghorbel
This paper presents the design and simulation results of a low power low noise amplifier (LNA) for 2.45 GHz industrial, scientific and medical (ISM) receiver for Body Area Network (BAN) in 0.18 um CMOS technology. This architecture is based on the resistive termination LNA. The proposed LNA consumes just 2.4 mW power. Its bandwidth is between 2 and 2.7 GHz. The simulated LNA shows a high voltage gain of about 22.7 dB with 0.86 dB minimal noise figure at 2.45 GHz frequency. It is characterized by an excellent input impedance equal to 48Ω at 2.45GHz.
介绍了一种用于2.45 GHz体域网(BAN)工业、科学和医疗(ISM)接收机的0.18 um CMOS低功耗低噪声放大器(LNA)的设计和仿真结果。该架构基于阻性端接LNA。拟议的LNA仅消耗2.4兆瓦的功率。它的带宽在2到2.7 GHz之间。仿真的LNA在2.45 GHz频率下具有22.7 dB的高电压增益和0.86 dB的最小噪声系数。它的特点是具有优异的输入阻抗，在2.45GHz时等于48Ω。
{"title":"A low power low noise amplifier for 2.45GHz ISM receiver for Body Area Network","authors":"Maissa Daoud, H. Mnif, M. Ghorbel","doi":"10.1109/IDT.2016.7843058","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843058","url":null,"abstract":"This paper presents the design and simulation results of a low power low noise amplifier (LNA) for 2.45 GHz industrial, scientific and medical (ISM) receiver for Body Area Network (BAN) in 0.18 um CMOS technology. This architecture is based on the resistive termination LNA. The proposed LNA consumes just 2.4 mW power. Its bandwidth is between 2 and 2.7 GHz. The simulated LNA shows a high voltage gain of about 22.7 dB with 0.86 dB minimal noise figure at 2.45 GHz frequency. It is characterized by an excellent input impedance equal to 48Ω at 2.45GHz.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132785126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843010
S. Chtourou, M. Abid, Z. Marrakchi, Emna Amouri, H. Mehrez
Field Programmable Gate Arrays (FPGAs) have become popular media for the implementation of many digital circuits. The quality of FPGA device is controlled by three factors which are: quality of the FPGA architecture, quality of the Computer-Aided Design (CAD) tools used to map circuits into the FPGA and electrical design of the FPGA. The subject of this paper is the exploration and optimization of cluster-based mesh FPGAs. To conduct this objective, we propose an exploration environment for cluster-based mesh FPGA architectures to explore and improve power consumption, area and performance. We propose also a new 2D cluster-based mesh FPGA architecture using hierarchical interconnect topology and long routing wires. With experimental method, we explore the effect of architecture parameters that control the interconnect flexibility. Results show that long routing wires improve the FPGA flexibility and performance. Nevertheless, as the long wires span increases, their delay also increases and impedes the overall performances. To mitigate the long wire length issues and improve performances, we propose to explore a development methodology of stacked FPGA architecture using 3D technology process. By adjusting the span of long wires, we can design two-tiers 3D cluster-based FPGA with 2 identical 2D functional layers. Moreover, we propose to investigate CAD algorithms aspect to optimize the mapping of application on the 3D FPGA architecture.
{"title":"Design of advanced 2D and 3D FPGAs: Architecture-level exploration and algorithm-level optimization","authors":"S. Chtourou, M. Abid, Z. Marrakchi, Emna Amouri, H. Mehrez","doi":"10.1109/IDT.2016.7843010","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843010","url":null,"abstract":"Field Programmable Gate Arrays (FPGAs) have become popular media for the implementation of many digital circuits. The quality of FPGA device is controlled by three factors which are: quality of the FPGA architecture, quality of the Computer-Aided Design (CAD) tools used to map circuits into the FPGA and electrical design of the FPGA. The subject of this paper is the exploration and optimization of cluster-based mesh FPGAs. To conduct this objective, we propose an exploration environment for cluster-based mesh FPGA architectures to explore and improve power consumption, area and performance. We propose also a new 2D cluster-based mesh FPGA architecture using hierarchical interconnect topology and long routing wires. With experimental method, we explore the effect of architecture parameters that control the interconnect flexibility. Results show that long routing wires improve the FPGA flexibility and performance. Nevertheless, as the long wires span increases, their delay also increases and impedes the overall performances. To mitigate the long wire length issues and improve performances, we propose to explore a development methodology of stacked FPGA architecture using 3D technology process. By adjusting the span of long wires, we can design two-tiers 3D cluster-based FPGA with 2 identical 2D functional layers. Moreover, we propose to investigate CAD algorithms aspect to optimize the mapping of application on the 3D FPGA architecture.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134292579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843029
M. M. El-Din, H. Fahmy, Y. Ismail, N. Gamal, H. Mostafa
The leakage power of FinFET-based FPGA cluster is studied and evaluated with technology node 14nm. The impact of threshold voltage variation, considering die-to-die variations, on the leakage power is reported after simulating a 2-Bit adder benchmark and comparing the results with the dynamic power consumption. Simulation results show, with the leakage power segmentation, that the multiplexers are the most consuming components for leakage power in the FPGA cluster architecture. Some leakage power control techniques are investigated including transistor stacking, minimum leakage vector, and gate sizing. The effect of each technique on the leakage power, leakage power variation, and the delay is reported and compared with the original design.
{"title":"Leakage power evaluation of FinFET-based FPGA cluster under threshold voltage variation","authors":"M. M. El-Din, H. Fahmy, Y. Ismail, N. Gamal, H. Mostafa","doi":"10.1109/IDT.2016.7843029","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843029","url":null,"abstract":"The leakage power of FinFET-based FPGA cluster is studied and evaluated with technology node 14nm. The impact of threshold voltage variation, considering die-to-die variations, on the leakage power is reported after simulating a 2-Bit adder benchmark and comparing the results with the dynamic power consumption. Simulation results show, with the leakage power segmentation, that the multiplexers are the most consuming components for leakage power in the FPGA cluster architecture. Some leakage power control techniques are investigated including transistor stacking, minimum leakage vector, and gate sizing. The effect of each technique on the leakage power, leakage power variation, and the delay is reported and compared with the original design.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114588919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843015
Y. Alkabani
As hardware system designers include third party IPs in their designs and outsource the fabrication to off-shore facilities, hardware security threats are becoming more serious. Threats include the overbuilding and malicious circuit insertion at the foundry during fabrication. Split fabrication for both 2D, 2.5D, and 3D ICs has been suggested to overcome these threats. In split fabrication, the system designer partitions the system into two parts: a complex part and a simple part. The complex part includes all the advanced circuitry that needs to be fabricated in a high-end untrusted fabrication facility. However, without the simple part, it is difficult for the untrusted foundry to identify the functionality of the system. The simple part is fabricated and integrated with the complex part in a trusted old foundry. This paper explores the use of an optimized set of isomorphic cells to implement digital systems. The use of these optimized cells should make it harder for the untrusted foundry to understand the system while simplifying the fabrication and integration process at the trusted foundry. The trade-off between simplifying the fabrication process at the trusted facility and the area overhead is studied on combinational benchmarks. The experimental results indicate that an average of 20% effort reduction can be achieved while maintaining a negligible impact on the area and delay of the original design.
{"title":"Hardware security and split fabrication","authors":"Y. Alkabani","doi":"10.1109/IDT.2016.7843015","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843015","url":null,"abstract":"As hardware system designers include third party IPs in their designs and outsource the fabrication to off-shore facilities, hardware security threats are becoming more serious. Threats include the overbuilding and malicious circuit insertion at the foundry during fabrication. Split fabrication for both 2D, 2.5D, and 3D ICs has been suggested to overcome these threats. In split fabrication, the system designer partitions the system into two parts: a complex part and a simple part. The complex part includes all the advanced circuitry that needs to be fabricated in a high-end untrusted fabrication facility. However, without the simple part, it is difficult for the untrusted foundry to identify the functionality of the system. The simple part is fabricated and integrated with the complex part in a trusted old foundry. This paper explores the use of an optimized set of isomorphic cells to implement digital systems. The use of these optimized cells should make it harder for the untrusted foundry to understand the system while simplifying the fabrication and integration process at the trusted foundry. The trade-off between simplifying the fabrication process at the trusted facility and the area overhead is studied on combinational benchmarks. The experimental results indicate that an average of 20% effort reduction can be achieved while maintaining a negligible impact on the area and delay of the original design.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"187 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114745112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843047
Sehmi Saad, Mongia Mhiri, Aymen Ben Hammadi, K. Besbes
In this paper, a new single-ended tunable active inductor (TAI) based on the use of two simples transconducters is proposed. A feedback resistance is added to improve the quality factor, while the tuning range of the desired inductance value is achieved by using a network of capacitance. The TAI has been implemented in a MS/RF 90 nm CMOS technology and a 1-V supply is used. The simulation results show that an inductance tuning range from 3.55 to 50 nH can be achieved. A high quality factor of 895 is obtained at the frequency 1.82 GHz. The circuit occupies a small active area of 22 × 27.5 mm2, presents a noise level of less than 4.2nV/√Hz, and consumes a power of 0.5 mW.
{"title":"Design of high-performance CMOS tunable active inductor","authors":"Sehmi Saad, Mongia Mhiri, Aymen Ben Hammadi, K. Besbes","doi":"10.1109/IDT.2016.7843047","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843047","url":null,"abstract":"In this paper, a new single-ended tunable active inductor (TAI) based on the use of two simples transconducters is proposed. A feedback resistance is added to improve the quality factor, while the tuning range of the desired inductance value is achieved by using a network of capacitance. The TAI has been implemented in a MS/RF 90 nm CMOS technology and a 1-V supply is used. The simulation results show that an inductance tuning range from 3.55 to 50 nH can be achieved. A high quality factor of 895 is obtained at the frequency 1.82 GHz. The circuit occupies a small active area of 22 × 27.5 mm2, presents a noise level of less than 4.2nV/√Hz, and consumes a power of 0.5 mW.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122834921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843041
R. El-Adawi, M. Dessouky
Yield estimation for high replication circuits such as SRAMs and flip flops is becoming a challenging task because a rare event in a circuit cell may impact significantly the whole system yield. The standard Monte Carlo Simulation is not efficient in detecting rare events because of the large number of simulations needed. The statistical blockade has been proposed to decrease the number of Monte Carlo simulations needed. In this paper it is shown that regression modeling can be used for parameter subset selection. This decreases the complexity of the problem while maintaining almost the same accuracy as the standard statistical blockade.
{"title":"Regression modeling for subset selection in rare-event statistical circuit simulation","authors":"R. El-Adawi, M. Dessouky","doi":"10.1109/IDT.2016.7843041","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843041","url":null,"abstract":"Yield estimation for high replication circuits such as SRAMs and flip flops is becoming a challenging task because a rare event in a circuit cell may impact significantly the whole system yield. The standard Monte Carlo Simulation is not efficient in detecting rare events because of the large number of simulations needed. The statistical blockade has been proposed to decrease the number of Monte Carlo simulations needed. In this paper it is shown that regression modeling can be used for parameter subset selection. This decreases the complexity of the problem while maintaining almost the same accuracy as the standard statistical blockade.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115542505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843035
M. Azeem, R. Chotin-Avot, U. Farooq, Maminionja Ravoson, H. Mehrez
Multiple FPGA-based prototyping plays an important role in the design and verification process due to their low cost and high execution speed. However, there is a need to optimize the configuration flow of this multiple FPGA-based prototyping. In this paper, we address the partitioning of large designs and propose a debugging methodology for these partitioned designs using Signal Tap II embedded logic analyzer by Quartus tool of Altera. Usually SignalTap II tool is used to debug design implemented on single FPGA and this logic analyzer debugs FPGA device by probing the states of internal signals without using external debug equipment. However, we use SignalTap II logic analyzer for large designs on multiple FPGAs and we facilitate the debugging methodology for thousands of signals under consideration. We propose the debugging of large designs after partitioning by developing the techniques to trace the required signals under test through multiple FPGAs without using FPGA internal memory. We have generated various large benchmarks as well and tested them for multiple FPGA-based prototyping.
基于多fpga的原型设计以其低成本和高执行速度在设计和验证过程中发挥着重要作用。然而，需要优化这种基于多个fpga的原型的配置流程。在本文中，我们讨论了大型设计的划分，并提出了一种调试方法，该方法使用Altera的Quartus工具使用Signal Tap II嵌入式逻辑分析仪对这些划分的设计进行调试。通常使用SignalTap II工具调试在单个FPGA上实现的设计，该逻辑分析仪在不使用外部调试设备的情况下，通过探测内部信号的状态来调试FPGA器件。然而，我们在多个fpga上使用SignalTap II逻辑分析仪进行大型设计，并且我们促进了数千个正在考虑的信号的调试方法。我们建议在划分后通过开发技术来跟踪需要测试的信号通过多个FPGA而不使用FPGA内部存储器的大型设计的调试。我们还生成了各种大型基准测试，并针对多个基于fpga的原型进行了测试。
{"title":"Multiple FPGAs based prototyping and debugging with complete design flow","authors":"M. Azeem, R. Chotin-Avot, U. Farooq, Maminionja Ravoson, H. Mehrez","doi":"10.1109/IDT.2016.7843035","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843035","url":null,"abstract":"Multiple FPGA-based prototyping plays an important role in the design and verification process due to their low cost and high execution speed. However, there is a need to optimize the configuration flow of this multiple FPGA-based prototyping. In this paper, we address the partitioning of large designs and propose a debugging methodology for these partitioned designs using Signal Tap II embedded logic analyzer by Quartus tool of Altera. Usually SignalTap II tool is used to debug design implemented on single FPGA and this logic analyzer debugs FPGA device by probing the states of internal signals without using external debug equipment. However, we use SignalTap II logic analyzer for large designs on multiple FPGAs and we facilitate the debugging methodology for thousands of signals under consideration. We propose the debugging of large designs after partitioning by developing the techniques to trace the required signals under test through multiple FPGAs without using FPGA internal memory. We have generated various large benchmarks as well and tested them for multiple FPGA-based prototyping.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124885890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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