Pub Date : 2013-04-12DOI: 10.1109/WMED.2013.6544491
T. Hollis
On behalf of the Organizing Committee, it is my pleasure to welcome you to the 2013 IEEE Workshop on Microelectronics and Electron Devices (WMED); a professional workshop hosted by the Boise Chapter of the IEEE Electron Devices Society (EDS). For eleven years, the WMED technical program has brought world renowned researchers to the Mountain West to discuss the progress of semiconductor-related technologies. This year, we are thrilled to be joined by several distinguished speakers, who will present their perspectives on a variety of important topics ranging from emerging device technologies, to next generation device fabrication, all the way to the larger systems which will take advantage of the enhanced device characteristics. I wish to share with each of our speakers my sincere appreciation for his or her contribution to the 2013 technical program.
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Pub Date : 2013-04-12DOI: 10.1109/WMED.2013.6544505
Xue-feng Lin, W. Morinville, Z. Suo, K. Zhuang, C. Krasinski, D. Markowitz, K. Noehring, Yang Zhou, S. York, H. Yapa, J. Brown, Shifeng Lu
Comprehensive studies of the integrity of HfO2-based high-k gate dielectrics are critical for optimizing and determining their performance properties. We present our results of atomic force microscopy, angle-resolved X-ray photoelectron spectroscopy, mercury probe, secondary ion mass spectrometry, and X-ray diffraction investigations of the HfO2 gate stack integrity thermally processed with low and high temperatures, and the arising issues on interfacial reaction, diffusion, crystal phase, surface structures, impurities, and dielectric behaviors are addressed and discussed. The aim of the present study is to gain a better understanding of these physical, chemical, and structural characteristics of high-k oxide gate dielectric stacks on silicon under elevated temperature annealing.
{"title":"Thermal processing impact on the integrity of HfO2-based high-k gate dielectrics","authors":"Xue-feng Lin, W. Morinville, Z. Suo, K. Zhuang, C. Krasinski, D. Markowitz, K. Noehring, Yang Zhou, S. York, H. Yapa, J. Brown, Shifeng Lu","doi":"10.1109/WMED.2013.6544505","DOIUrl":"https://doi.org/10.1109/WMED.2013.6544505","url":null,"abstract":"Comprehensive studies of the integrity of HfO2-based high-k gate dielectrics are critical for optimizing and determining their performance properties. We present our results of atomic force microscopy, angle-resolved X-ray photoelectron spectroscopy, mercury probe, secondary ion mass spectrometry, and X-ray diffraction investigations of the HfO2 gate stack integrity thermally processed with low and high temperatures, and the arising issues on interfacial reaction, diffusion, crystal phase, surface structures, impurities, and dielectric behaviors are addressed and discussed. The aim of the present study is to gain a better understanding of these physical, chemical, and structural characteristics of high-k oxide gate dielectric stacks on silicon under elevated temperature annealing.","PeriodicalId":134493,"journal":{"name":"2013 IEEE Workshop on Microelectronics and Electron Devices (WMED)","volume":"477 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132623699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-12DOI: 10.1109/WMED.2013.6544500
W. Haensch
Summary form only given. The enormous success of Si CMOS technology is based on the economy of scale. Cost is driven down by increasing wafer size and decreasing feature sizes while performance is steadily growing. The pervasive nature of microelectronic can be seen in all aspects of daily life. The industry enjoyed the success story for several decades by simply following the scaling laws. More recently it is realized that increased performance will come at an unacceptable cost of power and conventional CMOS scaling is rapidly coming to an end. The quest for solutions is in full swing how to meet the computational demands for the foreseeable future. Possible solutions are the change of device architecture and the introduction of high mobility materials for the devices to boost performance. Beyond the classical device materials Si, Ge, and some III/V compounds carbon in the form of carbon nano tubes or graphene are suggested as possible alternative candidates for digital applications. Replacing the field effect transistor by a tunnel FET holds the promise of a low power switch that can be realized with conventional channel materials. Moving from electrical charge to other state variables, like for instance spin, might provide new possibilities to meet the computational needs in the future.
{"title":"Invited talk: Computing beyond the 11nm node: Which devices will we use?","authors":"W. Haensch","doi":"10.1109/WMED.2013.6544500","DOIUrl":"https://doi.org/10.1109/WMED.2013.6544500","url":null,"abstract":"Summary form only given. The enormous success of Si CMOS technology is based on the economy of scale. Cost is driven down by increasing wafer size and decreasing feature sizes while performance is steadily growing. The pervasive nature of microelectronic can be seen in all aspects of daily life. The industry enjoyed the success story for several decades by simply following the scaling laws. More recently it is realized that increased performance will come at an unacceptable cost of power and conventional CMOS scaling is rapidly coming to an end. The quest for solutions is in full swing how to meet the computational demands for the foreseeable future. Possible solutions are the change of device architecture and the introduction of high mobility materials for the devices to boost performance. Beyond the classical device materials Si, Ge, and some III/V compounds carbon in the form of carbon nano tubes or graphene are suggested as possible alternative candidates for digital applications. Replacing the field effect transistor by a tunnel FET holds the promise of a low power switch that can be realized with conventional channel materials. Moving from electrical charge to other state variables, like for instance spin, might provide new possibilities to meet the computational needs in the future.","PeriodicalId":134493,"journal":{"name":"2013 IEEE Workshop on Microelectronics and Electron Devices (WMED)","volume":"634 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123048615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-12DOI: 10.1109/WMED.2013.6544495
J. Knickerbocker
Silicon interposer packaging and thin die stacking technologies with through-silicon-vias (TSV's) can improve performance, increase bandwidth, improve power efficiency, and reduce costs for systems applications. Proper system architecture and designs are critical to achieve these system benefits using silicon interposer packaging (2.5D) and 3-dimensional (3D) die stacking technologies. 2.5D and 3D heterogeneous multi-chip integration technologies have numerous challenges but through advancements they each can provide significant system benefits when compared to traditional packaging integration solutions. Portable electronics such as smart phones, sensors and bio-medical systems can benefit from “technology miniaturization” with increasing function in product generations, improved power efficiency, lower cost and high volume scale up capability associated with this small size and wafer or panel level processing. Large systems can also benefit from 2.5D and 3D technologies by taking advantage of close proximity computing, higher bandwidth with low latency, and power efficiencies to achieve higher performance and lower energy per operation.
{"title":"Invited talk: 2.5D and 3D technology advancements for systems","authors":"J. Knickerbocker","doi":"10.1109/WMED.2013.6544495","DOIUrl":"https://doi.org/10.1109/WMED.2013.6544495","url":null,"abstract":"Silicon interposer packaging and thin die stacking technologies with through-silicon-vias (TSV's) can improve performance, increase bandwidth, improve power efficiency, and reduce costs for systems applications. Proper system architecture and designs are critical to achieve these system benefits using silicon interposer packaging (2.5D) and 3-dimensional (3D) die stacking technologies. 2.5D and 3D heterogeneous multi-chip integration technologies have numerous challenges but through advancements they each can provide significant system benefits when compared to traditional packaging integration solutions. Portable electronics such as smart phones, sensors and bio-medical systems can benefit from “technology miniaturization” with increasing function in product generations, improved power efficiency, lower cost and high volume scale up capability associated with this small size and wafer or panel level processing. Large systems can also benefit from 2.5D and 3D technologies by taking advantage of close proximity computing, higher bandwidth with low latency, and power efficiencies to achieve higher performance and lower energy per operation.","PeriodicalId":134493,"journal":{"name":"2013 IEEE Workshop on Microelectronics and Electron Devices (WMED)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132408249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-12DOI: 10.1109/WMED.2013.6544504
M. R. Latif, M. Mitkova, G. Tompa, E. Coleman
This study is related to fabrication and characterization of redox conductive bridge memristors (RCBM). An active region in RCBM is formed by chalcogenide glass (ChG) doped with silver (Ag). We report the application of plasma enhanced chemical vapor deposition (PECVD) method for depositing ChG films which gives the advantage of flexibility in the composition and structure not easily achieved with sputtering or thermal evaporation. The growth kinetics of the deposition process, as well as the properties of the films is investigated. Optimal deposition conditions for reliable device performance are determined. The electrical characteristics of the devices fabricated at these conditions are also tested.
{"title":"PECVD of GexS1−x films for nano-ionic redox conductive bridge memristive switch memory","authors":"M. R. Latif, M. Mitkova, G. Tompa, E. Coleman","doi":"10.1109/WMED.2013.6544504","DOIUrl":"https://doi.org/10.1109/WMED.2013.6544504","url":null,"abstract":"This study is related to fabrication and characterization of redox conductive bridge memristors (RCBM). An active region in RCBM is formed by chalcogenide glass (ChG) doped with silver (Ag). We report the application of plasma enhanced chemical vapor deposition (PECVD) method for depositing ChG films which gives the advantage of flexibility in the composition and structure not easily achieved with sputtering or thermal evaporation. The growth kinetics of the deposition process, as well as the properties of the films is investigated. Optimal deposition conditions for reliable device performance are determined. The electrical characteristics of the devices fabricated at these conditions are also tested.","PeriodicalId":134493,"journal":{"name":"2013 IEEE Workshop on Microelectronics and Electron Devices (WMED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129418442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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