Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348227
A. Balasinski, J. Cetin
Uniform pattern density of physical layers of the die, such as diffusion, poly, or metals, has significant impact on electrical parameters of the product. At active level, variations in pattern density across the die translate into wide distributions of punch-through or breakdown voltages. At poly and metal levels, a non-uniform pattern density would result in poor planarity and give rise to high via resistances and poor control of the inter-layer capacitive coupling. However, at design stage, the complex functions of SoC functional blocks do not give designers enough freedom to strictly observe a predefined set of pattern density rules. Instead, the die pattern has to be made more uniform at die integration level, by global addition of fill features (waffles). While conceptually simple, this presents significant technical challenge, as the criteria for this addition are often difficult to meet. The simple but time consuming way of making pattern density uniform is based on manual drawing of dummy features over the electrical database (intellectual property, IP) of the die. A simplistic, automated approach is to add fill pattern of fixed density until it becomes close to target pattern density of the die. However, it may not be possible to equalize out all the regions even with changes in the die architecture. In addition, this approach tends to add dummy features even if unnecessary, driving towards very high pattern density. This solution is disadvantageous for RF/analog products the performance of which can be compromised by the capacitive coupling through the waffles. The methodology proposed that the initial die pattern density is first evaluated followed by the adjustable, intelligent fill of dynamic density at the block level. This way, it is possible to keep the original pattern density and work only on the areas of small density. The authors propose that the standard cell methodology should enable pre-die level modifications of pattern density and its extraction, to ensure that all the required blocks could be placed on the product and that their parasitics are properly extracted
{"title":"Intelligent Fill Pattern and Extraction Methodology for SoC","authors":"A. Balasinski, J. Cetin","doi":"10.1109/IWSOC.2006.348227","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348227","url":null,"abstract":"Uniform pattern density of physical layers of the die, such as diffusion, poly, or metals, has significant impact on electrical parameters of the product. At active level, variations in pattern density across the die translate into wide distributions of punch-through or breakdown voltages. At poly and metal levels, a non-uniform pattern density would result in poor planarity and give rise to high via resistances and poor control of the inter-layer capacitive coupling. However, at design stage, the complex functions of SoC functional blocks do not give designers enough freedom to strictly observe a predefined set of pattern density rules. Instead, the die pattern has to be made more uniform at die integration level, by global addition of fill features (waffles). While conceptually simple, this presents significant technical challenge, as the criteria for this addition are often difficult to meet. The simple but time consuming way of making pattern density uniform is based on manual drawing of dummy features over the electrical database (intellectual property, IP) of the die. A simplistic, automated approach is to add fill pattern of fixed density until it becomes close to target pattern density of the die. However, it may not be possible to equalize out all the regions even with changes in the die architecture. In addition, this approach tends to add dummy features even if unnecessary, driving towards very high pattern density. This solution is disadvantageous for RF/analog products the performance of which can be compromised by the capacitive coupling through the waffles. The methodology proposed that the initial die pattern density is first evaluated followed by the adjustable, intelligent fill of dynamic density at the block level. This way, it is possible to keep the original pattern density and work only on the areas of small density. The authors propose that the standard cell methodology should enable pre-die level modifications of pattern density and its extraction, to ensure that all the required blocks could be placed on the product and that their parasitics are properly extracted","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126574155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348238
O. Faurax, L. Freund, A. Tria, T. Muntean, F. Bancel
Microcircuits dedicated to security in smartcards are targeted by more and more sophisticated attacks like fault attacks that combine physical disturbance and cryptanalysis. The use of simulation for circuit validation considering these attacks is limited by the time needed to compute the result of the chosen fault injections. Usually, this choice is made by the user according to his knowledge of the circuit functionality. The aim of this paper is to propose a generic and semi-automatic method to reduce the number of fault injections using types of data stored in registers (latch by latch)
{"title":"A generic method for fault injection in circuits","authors":"O. Faurax, L. Freund, A. Tria, T. Muntean, F. Bancel","doi":"10.1109/IWSOC.2006.348238","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348238","url":null,"abstract":"Microcircuits dedicated to security in smartcards are targeted by more and more sophisticated attacks like fault attacks that combine physical disturbance and cryptanalysis. The use of simulation for circuit validation considering these attacks is limited by the time needed to compute the result of the chosen fault injections. Usually, this choice is made by the user according to his knowledge of the circuit functionality. The aim of this paper is to propose a generic and semi-automatic method to reduce the number of fault injections using types of data stored in registers (latch by latch)","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"231 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114078059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348269
S. Areibi, Fujian Li
The Fiduccia-Mattheyses (F-M) algorithm (1982) has proved to be an efficient algorithm for VLSI circuit partitioning, and it is widely used for several physical design automation applications. As digital circuits are becoming larger and more complex, methods such as the F-M algorithm are becoming slower and less efficient. To accelerate the F-M algorithm, an embedded computing system based on an FPGA chip is proposed. A speedup hardware module handles the computationally intensive functions while an embedded processor (a MicroBlaze soft-core) handles intense memory access operations that cannot be implemented efficiently with dedicated hardware. The co-design system can produce as good results as a pure software implementation, and can achieve better results than a pure-hardware based system by an average of 25%. The co-design based approach achieves results that are 2times faster than the pure-software based design
{"title":"A Hardware/Software Co-Design Approach for VLSI Circuit Partitioning","authors":"S. Areibi, Fujian Li","doi":"10.1109/IWSOC.2006.348269","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348269","url":null,"abstract":"The Fiduccia-Mattheyses (F-M) algorithm (1982) has proved to be an efficient algorithm for VLSI circuit partitioning, and it is widely used for several physical design automation applications. As digital circuits are becoming larger and more complex, methods such as the F-M algorithm are becoming slower and less efficient. To accelerate the F-M algorithm, an embedded computing system based on an FPGA chip is proposed. A speedup hardware module handles the computationally intensive functions while an embedded processor (a MicroBlaze soft-core) handles intense memory access operations that cannot be implemented efficiently with dedicated hardware. The co-design system can produce as good results as a pure software implementation, and can achieve better results than a pure-hardware based system by an average of 25%. The co-design based approach achieves results that are 2times faster than the pure-software based design","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125308267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348262
A.R. Fouli, M. El-Kharashi, H. El-Henawy
This paper presents a pilot project in the serial advanced technology attachment interface controllers. It implements the SATA host controller based on the SATA2.5 standard. It shows how to enhance the hardware performance in both the implementation and the verification phases. Complete register transfer logic implementation of the host controller architecture is written in Verilog. PSL assertions are applied to fully test and verify the design. The design is being realized on Xilinx Virtex-II Pro FPGA
本文介绍了一种串行先进技术连接接口控制器的试验方案。它基于SATA2.5标准实现了SATA主机控制器。它展示了如何在实现和验证阶段提高硬件性能。完整的寄存器传输逻辑实现的主控制器架构是用Verilog写的。应用PSL断言对设计进行全面测试和验证。该设计在Xilinx Virtex-II Pro FPGA上实现
{"title":"Serial ATA Host Controller: A Hardware Implementation","authors":"A.R. Fouli, M. El-Kharashi, H. El-Henawy","doi":"10.1109/IWSOC.2006.348262","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348262","url":null,"abstract":"This paper presents a pilot project in the serial advanced technology attachment interface controllers. It implements the SATA host controller based on the SATA2.5 standard. It shows how to enhance the hardware performance in both the implementation and the verification phases. Complete register transfer logic implementation of the host controller architecture is written in Verilog. PSL assertions are applied to fully test and verify the design. The design is being realized on Xilinx Virtex-II Pro FPGA","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"237 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132278003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348224
S. Kirolos, T. Ragheb, J. Laska, M. Duarte, Y. Massoud, Richard Baraniuk
The stability and programmability of digital signal processing systems has motivated engineers to move the analog-to-digital conversion (ADC) process closer and closer to the front end of many signal processing systems in order to perform as much processing as possible in the digital domain. Unfortunately, many important applications, including radar and communication systems, involve wideband signals that seriously stress modern ADCs; sampling these signals above the Nyquist rate is in some cases challenging and in others impossible. While wideband signals by definition have a large bandwidth, often the amount of information they carry per second is much lower; that is, they are compressible in some sense. The first contribution of this paper is a new framework for wideband signal acquisition purpose-built for compressible signals that enables sub-Nyquist data acquisition via an analog-to-information converter (AIC). The framework is based on the recently developed theory of compressive sensing in which a small number of non-adaptive, randomized measurements are sufficient to reconstruct compressible signals. The second contribution of this paper is an AIC implementation design and study of the tradeoffs and non-idealities introduced by real hardware. The goal is to identify and optimize the parameters that dominate the overall system performance
{"title":"Practical Issues in Implementing Analog-to-Information Converters","authors":"S. Kirolos, T. Ragheb, J. Laska, M. Duarte, Y. Massoud, Richard Baraniuk","doi":"10.1109/IWSOC.2006.348224","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348224","url":null,"abstract":"The stability and programmability of digital signal processing systems has motivated engineers to move the analog-to-digital conversion (ADC) process closer and closer to the front end of many signal processing systems in order to perform as much processing as possible in the digital domain. Unfortunately, many important applications, including radar and communication systems, involve wideband signals that seriously stress modern ADCs; sampling these signals above the Nyquist rate is in some cases challenging and in others impossible. While wideband signals by definition have a large bandwidth, often the amount of information they carry per second is much lower; that is, they are compressible in some sense. The first contribution of this paper is a new framework for wideband signal acquisition purpose-built for compressible signals that enables sub-Nyquist data acquisition via an analog-to-information converter (AIC). The framework is based on the recently developed theory of compressive sensing in which a small number of non-adaptive, randomized measurements are sufficient to reconstruct compressible signals. The second contribution of this paper is an AIC implementation design and study of the tradeoffs and non-idealities introduced by real hardware. The goal is to identify and optimize the parameters that dominate the overall system performance","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115129267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348236
J. Ravindra, N. Chittarvu, M. Srinivas
In deep-submicron technology (DSM), minimizing the propagation delay and power dissipation on buses is the most important design objective in system-on-chip (SOC) design. In particular, the coupling effects between wires on the bus that can cause serious problems such as cross-talk delay, noise and power dissipation. Most of the researchers have concentrated either on minimizing the power dissipation or minimizing crosstalk delay. In this paper, the authors propose a technique for energy efficient data transmission for on-chip buses and evaluate the effectiveness of our technique by using SPEC 95 benchmarks suit. The authors show that our technique achieves 35% of energy savings over the un-encoded data transmission on the data bus
{"title":"Energy Efficient Spatial Coding Technique for Low Power VLSI Applications","authors":"J. Ravindra, N. Chittarvu, M. Srinivas","doi":"10.1109/IWSOC.2006.348236","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348236","url":null,"abstract":"In deep-submicron technology (DSM), minimizing the propagation delay and power dissipation on buses is the most important design objective in system-on-chip (SOC) design. In particular, the coupling effects between wires on the bus that can cause serious problems such as cross-talk delay, noise and power dissipation. Most of the researchers have concentrated either on minimizing the power dissipation or minimizing crosstalk delay. In this paper, the authors propose a technique for energy efficient data transmission for on-chip buses and evaluate the effectiveness of our technique by using SPEC 95 benchmarks suit. The authors show that our technique achieves 35% of energy savings over the un-encoded data transmission on the data bus","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128243881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348256
Zhijun Wang, Liping Liang
An all digital CMOS serial link transceiver with 3x over-sampling based data recovery circuit is presented in this paper. The modified data recovery circuit is simpler than those using 3x over-sampling recovery circuit in (Chih-Kong Ken Yang et al., 1998) and (Chih-Kong Ken Yang and Horowitz). An all digital DLL (delay locked loop) is used to generate the multiphase clocks and a new CPRD (coarse phase-difference range decision) unit is introduced here to reduce the lock time. The whole design's feasibility is verified by the Verilog HDL modeling. And the DLL's performance is simulated by HSPICE in SMIC 0.18mum CMOS technology. The simulation results show that the system is workable. The data recovery's latency of the transceiver is reduced to 5 cycles and the whole system can hold about 1Gbps data bit rate in the worst case
本文介绍了一种全数字CMOS串行链路收发器，该收发器具有3倍过采样的数据恢复电路。改进后的数据恢复电路比(Chih-Kong Ken Yang et al.， 1998)和(Chih-Kong Ken Yang and Horowitz)中使用3x过采样恢复电路的数据恢复电路更简单。采用全数字延迟锁相环(DLL)产生多相时钟，并引入粗相位差范围判断(CPRD)单元来减少锁相时间。通过Verilog HDL建模验证了整个设计的可行性。并利用HSPICE在中芯0.18 μ m CMOS技术下对DLL的性能进行了仿真。仿真结果表明，该系统是可行的。收发器的数据恢复延迟减少到5个周期，整个系统在最坏情况下可以保持1Gbps左右的数据比特率
{"title":"An All Digital CMOS Serial Link Transceiver with 3x Over-sampling Based Data Recovery","authors":"Zhijun Wang, Liping Liang","doi":"10.1109/IWSOC.2006.348256","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348256","url":null,"abstract":"An all digital CMOS serial link transceiver with 3x over-sampling based data recovery circuit is presented in this paper. The modified data recovery circuit is simpler than those using 3x over-sampling recovery circuit in (Chih-Kong Ken Yang et al., 1998) and (Chih-Kong Ken Yang and Horowitz). An all digital DLL (delay locked loop) is used to generate the multiphase clocks and a new CPRD (coarse phase-difference range decision) unit is introduced here to reduce the lock time. The whole design's feasibility is verified by the Verilog HDL modeling. And the DLL's performance is simulated by HSPICE in SMIC 0.18mum CMOS technology. The simulation results show that the system is workable. The data recovery's latency of the transceiver is reduced to 5 cycles and the whole system can hold about 1Gbps data bit rate in the worst case","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121661717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348229
A. Kassem, M. Hamad, M. Sawan
This paper concerns a new design method for a system on a chip (SOC) dedicated to ultrasonic digital imaging systems (UDIS). This design method allow for the creation of a new generation of miniaturized and portable ultrasonic machines, where the electronic components will be integrated on only one single chip. It also make possible to visualize in real time the ultrasound images. An ultrasound imaging is a common and popular technique to evaluate, in a noninvasive way and in real time, the internal anatomy structure and its function. It requires high resolution and real-time images processing. The proposed design core efficiently integrates all of the necessary ultrasonic B-mode processing modules. It includes digital beamforming, quadrature demodulation of RF signals, digital filtering and envelope detection of the received signals. This system handles 128 scan lines and 6400 samples per scan line with a 90deg angle of view span. The design uses a minimum size look-up memory to store the initial scan information. Rapid prototyping using an ARM/FPGA combination is used to validate the operation of the described system
{"title":"An Efficient SoC Dedicated to Ultrasonic Digital Imaging Systems","authors":"A. Kassem, M. Hamad, M. Sawan","doi":"10.1109/IWSOC.2006.348229","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348229","url":null,"abstract":"This paper concerns a new design method for a system on a chip (SOC) dedicated to ultrasonic digital imaging systems (UDIS). This design method allow for the creation of a new generation of miniaturized and portable ultrasonic machines, where the electronic components will be integrated on only one single chip. It also make possible to visualize in real time the ultrasound images. An ultrasound imaging is a common and popular technique to evaluate, in a noninvasive way and in real time, the internal anatomy structure and its function. It requires high resolution and real-time images processing. The proposed design core efficiently integrates all of the necessary ultrasonic B-mode processing modules. It includes digital beamforming, quadrature demodulation of RF signals, digital filtering and envelope detection of the received signals. This system handles 128 scan lines and 6400 samples per scan line with a 90deg angle of view span. The design uses a minimum size look-up memory to store the initial scan information. Rapid prototyping using an ARM/FPGA combination is used to validate the operation of the described system","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"75 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121156197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348249
Hazem ElTahawy
and bio are not available at the printing time. ix
和生物在打印时是不可用的。9
{"title":"System on Chip (SOC) design pressures reach critical point","authors":"Hazem ElTahawy","doi":"10.1109/IWSOC.2006.348249","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348249","url":null,"abstract":"and bio are not available at the printing time. ix","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131435726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348258
M. Elsabrouty, M. Bouchard, Tyseer Aboulnasr
A classical adaptive filtering view of the problem of instantaneous blind signal separation is presented. This classical form enables an easy understanding of the natural gradient algorithm. A new RLS-based algorithm is developed using this classical interpretation. The algorithm provides improved on-line separation speed under the same steady state error compared to the natural gradient algorithm without requiring pre-whitening
{"title":"A Classical Adaptive Filtering Blind Signal Separation","authors":"M. Elsabrouty, M. Bouchard, Tyseer Aboulnasr","doi":"10.1109/IWSOC.2006.348258","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348258","url":null,"abstract":"A classical adaptive filtering view of the problem of instantaneous blind signal separation is presented. This classical form enables an easy understanding of the natural gradient algorithm. A new RLS-based algorithm is developed using this classical interpretation. The algorithm provides improved on-line separation speed under the same steady state error compared to the natural gradient algorithm without requiring pre-whitening","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"27 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132746735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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