Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348268
A.M. Ismail, M. Nafie
Soft output Viterbi algorithm (SOVA) and max-log-maximum a posteriori (Max-Log-MAP) are used for turbo codes decoding. SOVA is considered a simple way of implementation with higher throughput in comparison to the Max-Log-MAP, while the later is still superior from decoding performance point of view. A modified SOVA (MSOVA) was theoretically proven to be equivalent to Max-Log-MAP. In this paper a HW implementation for CDMA2000 turbo decoder using MSOVA is presented. This implementation is based on the MSOVA, using Xilinx Virtex 2 pro FPGA. The implementation was shown to have higher throughput and lower latency than a commercial decoder
turbo码译码采用软输出维特比算法(SOVA)和最大对数最大后验算法(Max-Log-MAP)。与Max-Log-MAP相比，SOVA被认为是一种简单的实现方式，具有更高的吞吐量，而后者从解码性能的角度来看仍然优于Max-Log-MAP。从理论上证明了改进的SOVA (MSOVA)等价于Max-Log-MAP。本文介绍了一种基于MSOVA的CDMA2000 turbo译码器的硬件实现。该实现基于MSOVA，使用Xilinx Virtex 2 pro FPGA。与商用解码器相比，该实现具有更高的吞吐量和更低的延迟
{"title":"FPGA Based Implementation of MSOVA for CDMA2000 Turbo Decoder","authors":"A.M. Ismail, M. Nafie","doi":"10.1109/IWSOC.2006.348268","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348268","url":null,"abstract":"Soft output Viterbi algorithm (SOVA) and max-log-maximum a posteriori (Max-Log-MAP) are used for turbo codes decoding. SOVA is considered a simple way of implementation with higher throughput in comparison to the Max-Log-MAP, while the later is still superior from decoding performance point of view. A modified SOVA (MSOVA) was theoretically proven to be equivalent to Max-Log-MAP. In this paper a HW implementation for CDMA2000 turbo decoder using MSOVA is presented. This implementation is based on the MSOVA, using Xilinx Virtex 2 pro FPGA. The implementation was shown to have higher throughput and lower latency than a commercial decoder","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"168 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116267655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348220
J. J. Lopes, J.S. Luiz, E. Marques, J. Cardoso
High-performance FPGA accelerating software applications are a growing demand in fields as communications, image processing, and scientific computing among others. Moreover, as the cost per gate of FPGAs declines, embedded and high-performance systems designers are being presented with new opportunities for creating accelerated software applications using FPGA-based programmable hardware platforms. Powerful high-level language to RTL generators are now emerging. One of the promises of these tools is to allow software and systems engineers to implement algorithms quickly in a familiar language and target the design to a programmable device. The generators available today support syntaxes with different degrees of fidelity to the original language. This paper focuses on the efficient use of C to RTL generators that have a high degree of fidelity to the original C language. The objective of this project is to study some tools that starting from languages of high level as ANSI-C, and generate FPGA accelerating software applications automatically. In this paper are presented tools and partial results of the hardware generated by them
高性能FPGA加速软件应用在通信、图像处理和科学计算等领域的需求日益增长。此外，随着fpga每门成本的下降，嵌入式和高性能系统设计人员正在为使用基于fpga的可编程硬件平台创建加速软件应用程序提供新的机会。强大的高级语言到RTL生成器正在出现。这些工具的承诺之一是允许软件和系统工程师用熟悉的语言快速实现算法，并将设计目标定位于可编程设备。目前可用的生成器支持的语法与原始语言的保真度不同。本文的重点是有效地使用C to RTL生成器，这些生成器对原始C语言具有很高的保真度。本课题的目的是研究一些从ANSI-C等高级语言入手的工具，自动生成FPGA加速软件应用。本文给出了由它们生成的工具和部分硬件结果
{"title":"A Benchmark Approach for Compilers in Reconfigurable Hardware","authors":"J. J. Lopes, J.S. Luiz, E. Marques, J. Cardoso","doi":"10.1109/IWSOC.2006.348220","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348220","url":null,"abstract":"High-performance FPGA accelerating software applications are a growing demand in fields as communications, image processing, and scientific computing among others. Moreover, as the cost per gate of FPGAs declines, embedded and high-performance systems designers are being presented with new opportunities for creating accelerated software applications using FPGA-based programmable hardware platforms. Powerful high-level language to RTL generators are now emerging. One of the promises of these tools is to allow software and systems engineers to implement algorithms quickly in a familiar language and target the design to a programmable device. The generators available today support syntaxes with different degrees of fidelity to the original language. This paper focuses on the efficient use of C to RTL generators that have a high degree of fidelity to the original C language. The objective of this project is to study some tools that starting from languages of high level as ANSI-C, and generate FPGA accelerating software applications automatically. In this paper are presented tools and partial results of the hardware generated by them","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114315323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348265
H. El-Madbouly, Mohamed Hamdy
In estimating cell loss probability (CLP) and mean cell delay which are often specified to be less than 10-9 and less than 10 musec respectively. Fuzzy based control techniques have been introduced to be more promising over crisp statistical techniques. In this paper a novel fuzzy logic algorithm has been proposed to estimate CLP and the mean cell delay in the real time for self-similar ATM networks. The proposed fuzzy approach is validating by comparing the estimated values of CLP and delay with the theoretical values. The new approach not only estimates accurate real time CLP and delay, but also achieves it by using fewer theoretical data
{"title":"Call Admission Control for ATM System using Fuzzy Control Approach","authors":"H. El-Madbouly, Mohamed Hamdy","doi":"10.1109/IWSOC.2006.348265","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348265","url":null,"abstract":"In estimating cell loss probability (CLP) and mean cell delay which are often specified to be less than 10-9 and less than 10 musec respectively. Fuzzy based control techniques have been introduced to be more promising over crisp statistical techniques. In this paper a novel fuzzy logic algorithm has been proposed to estimate CLP and the mean cell delay in the real time for self-similar ATM networks. The proposed fuzzy approach is validating by comparing the estimated values of CLP and delay with the theoretical values. The new approach not only estimates accurate real time CLP and delay, but also achieves it by using fewer theoretical data","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133863401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348253
M. Nakkar, N. Ahmed
Power consumption is becoming a pressing issue in microprocessor design. Caches usually consume large part of the total power consumption of the chip. This paper introduces a novel low power cache architecture which is based on separating the in-coming cache data. Data is separated in two different banks: bank1 that mostly contains 1s data and bank0 that mostly contains 0s data. This separation in part reduces transistor switching activity inside the on-chip cache and hence dynamic power consumption. This papers shows up to 35% reduction for small sized cache of 1K and 9% for typical sized caches of 32K
{"title":"Low Power Cache Architecture","authors":"M. Nakkar, N. Ahmed","doi":"10.1109/IWSOC.2006.348253","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348253","url":null,"abstract":"Power consumption is becoming a pressing issue in microprocessor design. Caches usually consume large part of the total power consumption of the chip. This paper introduces a novel low power cache architecture which is based on separating the in-coming cache data. Data is separated in two different banks: bank1 that mostly contains 1s data and bank0 that mostly contains 0s data. This separation in part reduces transistor switching activity inside the on-chip cache and hence dynamic power consumption. This papers shows up to 35% reduction for small sized cache of 1K and 9% for typical sized caches of 32K","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128149883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348232
Xiaoguang Li, S. Areibi, R. Dony
The processing elements, logic resources, and on-chip block RAMs of modern FPGAs can not only be used for prototyping custom hardware modules, but also for parallel processing purposes by implementing multiple processors for a single task. This paper compares the performance of a single-processor implementation with two types of dual-processor implementations for a widely used radix-2 n-point FFT algorithm (Kooley and Tuckey, 1965) in terms of processing speed and FPGA resource utilization. In the first dual-processor implementation, the partitioning is performed based on the computation complexity - O(nlog(n)) of the radix-2 FFT algorithm. In the second implementation, the partitioning is based on a detailed profiling procedure applied to each line of the code in the single-processor implementation. Results obtained show that the speedup of the first dual-processor implementation is on average 1.3times faster than the single-processor implementation, whereas the second dual-processor implementation is about 1.9times faster which is very close to the expected speedup. This result shows that detailed profiling is crucial in identifying the bottlenecks of an algorithm (i.e., all the factors are taken into consideration) and consequently the algorithm can be efficiently mapped on a multiprocessor system based on the correct decision
{"title":"Parallel Processing on FPGAs: The Effect of Profiling on Performance","authors":"Xiaoguang Li, S. Areibi, R. Dony","doi":"10.1109/IWSOC.2006.348232","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348232","url":null,"abstract":"The processing elements, logic resources, and on-chip block RAMs of modern FPGAs can not only be used for prototyping custom hardware modules, but also for parallel processing purposes by implementing multiple processors for a single task. This paper compares the performance of a single-processor implementation with two types of dual-processor implementations for a widely used radix-2 n-point FFT algorithm (Kooley and Tuckey, 1965) in terms of processing speed and FPGA resource utilization. In the first dual-processor implementation, the partitioning is performed based on the computation complexity - O(nlog(n)) of the radix-2 FFT algorithm. In the second implementation, the partitioning is based on a detailed profiling procedure applied to each line of the code in the single-processor implementation. Results obtained show that the speedup of the first dual-processor implementation is on average 1.3times faster than the single-processor implementation, whereas the second dual-processor implementation is about 1.9times faster which is very close to the expected speedup. This result shows that detailed profiling is crucial in identifying the bottlenecks of an algorithm (i.e., all the factors are taken into consideration) and consequently the algorithm can be efficiently mapped on a multiprocessor system based on the correct decision","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121289580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348239
N. Tabrizi, N. Bagherzadeh
The authors have developed 116 times 32-bit 1-write-port, 2-read-port, 4-read/write-port register file to be shared by five processors in a multiprocessor-on-a-chip, supporting conditional operands in both read and write operations. This register file provides the underlying SoC with an inter-processor transparent communication layer in which each processor shares a distributed (register) address space (comprised of 32 registers) with eight other processors to reach a tightly-coupled array of processors with high-performance inter-processor communication facilitating real-time applications
{"title":"A Distributed and Shared Register File for a Multiprocessor-on-Chip to Support Real-Time Applications","authors":"N. Tabrizi, N. Bagherzadeh","doi":"10.1109/IWSOC.2006.348239","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348239","url":null,"abstract":"The authors have developed 116 times 32-bit 1-write-port, 2-read-port, 4-read/write-port register file to be shared by five processors in a multiprocessor-on-a-chip, supporting conditional operands in both read and write operations. This register file provides the underlying SoC with an inter-processor transparent communication layer in which each processor shares a distributed (register) address space (comprised of 32 registers) with eight other processors to reach a tightly-coupled array of processors with high-performance inter-processor communication facilitating real-time applications","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114520335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348223
Y. Oddos, K. Morin-Allory, D. Bomone
The authors propose an efficient solution to automatically generate test vectors that satisfy an assumed property written in PSL. From a SERE formula, the authors build a synthesizable generator that produces random temporal test vectors compliant with the formula. Generators are space and speed efficient when synthesized on FPGA, and their connection to the device under test is a portable solution across verification platforms for simulation and emulation
{"title":"On-Line Test Vector Generation from Temporal Regular Expressions","authors":"Y. Oddos, K. Morin-Allory, D. Bomone","doi":"10.1109/IWSOC.2006.348223","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348223","url":null,"abstract":"The authors propose an efficient solution to automatically generate test vectors that satisfy an assumed property written in PSL. From a SERE formula, the authors build a synthesizable generator that produces random temporal test vectors compliant with the formula. Generators are space and speed efficient when synthesized on FPGA, and their connection to the device under test is a portable solution across verification platforms for simulation and emulation","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130665598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348263
Kisun You, Hyun-Sub Lim, Wonyong Sung
In spite of ever increasing logic capacity of FPGAs, the implementation of a large vocabulary speech recognition system encounters insufficient I/O bandwidth and internal memory capacity problems. In this paper, a speech recognition system architecture was described based on a softcore with hardware accelerators for the emission probability computation and the Viterbi beam search. The hardware accelerator for emission probability computation is equipped with the internal memory to effectively capture the access pattern of the acoustic model data which depend on the language model. The optimal memory configuration is determined by the proposed data partitioning strategy. The developed system has been implemented on a Xilinx Virtex-4 FPGA with MicroBlaze softcore processor along with various peripherals. The experimental results show that the proposed architecture speeds up the recognition by reducing the memory bandwidth requirement thereby the system is capable of performing real-time recognition for the DARPA resource management task which supports about 1000 words continuous speech recognition
{"title":"Architectural Design and Implementation of an FPGA Softcore Based Speech Recognition System","authors":"Kisun You, Hyun-Sub Lim, Wonyong Sung","doi":"10.1109/IWSOC.2006.348263","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348263","url":null,"abstract":"In spite of ever increasing logic capacity of FPGAs, the implementation of a large vocabulary speech recognition system encounters insufficient I/O bandwidth and internal memory capacity problems. In this paper, a speech recognition system architecture was described based on a softcore with hardware accelerators for the emission probability computation and the Viterbi beam search. The hardware accelerator for emission probability computation is equipped with the internal memory to effectively capture the access pattern of the acoustic model data which depend on the language model. The optimal memory configuration is determined by the proposed data partitioning strategy. The developed system has been implemented on a Xilinx Virtex-4 FPGA with MicroBlaze softcore processor along with various peripherals. The experimental results show that the proposed architecture speeds up the recognition by reducing the memory bandwidth requirement thereby the system is capable of performing real-time recognition for the DARPA resource management task which supports about 1000 words continuous speech recognition","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126405534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348267
H. El-Madbouly, M. Nassef
In this paper, an on line genetic algorithm (GA) is proposed for estimating the cell loss probability (CLP) and the cell delay in real time. They are key parameters to many vital functions in the network such as call admission (CAC), bandwidth allocation, etc. However, the CLR and delay depend usually on many unknown and unpredictable traffic parameters such as input traffic correlations. In this paper, a novel genetic algorithm to predict the CLR and delay in different sized systems based on both a small amount of information from these systems. This algorithm is used with real time traffic measurement to maintain and design the ATM network
{"title":"Estimation of Cell Loss Ratio and Cell Delay for ATM Networks using Novel Genetic Algorithm Approach","authors":"H. El-Madbouly, M. Nassef","doi":"10.1109/IWSOC.2006.348267","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348267","url":null,"abstract":"In this paper, an on line genetic algorithm (GA) is proposed for estimating the cell loss probability (CLP) and the cell delay in real time. They are key parameters to many vital functions in the network such as call admission (CAC), bandwidth allocation, etc. However, the CLR and delay depend usually on many unknown and unpredictable traffic parameters such as input traffic correlations. In this paper, a novel genetic algorithm to predict the CLR and delay in different sized systems based on both a small amount of information from these systems. This algorithm is used with real time traffic measurement to maintain and design the ATM network","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129662003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348255
Jeong-Gun Lee, Jeong-A Lee, Deok-Young Lee
Many adder designs exist for a designer to choose the fastest or the smallest or power efficient one. However, the performance of existing adders varies widely in their speed and area requirements, which in turn sometimes makes designers pay a high cost in area especially when the delay requirements exceeds the fastest speed of a specific adder, no matter how small the difference it is. To smooth such an increase in cost, we propose new adder architecture with expanded design space for better design tradeoffs. The new adder architecture, named a mutated adder architecture, restructures an adder with blocks of various carry propagated adders as sub-adder-components to aid a designer in selecting his/her adder with favorable characteristics. We formulate the problem of determining the bit-width of various carry propagate component adders in integer linear programming. We demonstrate the effectiveness of the new adder architecture using 128-bit adder design
{"title":"Better Area-Time Tradeoffs in an Expanded Design Space of Adder Architecture by Parameterizing Bit-width of Various Carry Propagated Sub-adder-blocks","authors":"Jeong-Gun Lee, Jeong-A Lee, Deok-Young Lee","doi":"10.1109/IWSOC.2006.348255","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348255","url":null,"abstract":"Many adder designs exist for a designer to choose the fastest or the smallest or power efficient one. However, the performance of existing adders varies widely in their speed and area requirements, which in turn sometimes makes designers pay a high cost in area especially when the delay requirements exceeds the fastest speed of a specific adder, no matter how small the difference it is. To smooth such an increase in cost, we propose new adder architecture with expanded design space for better design tradeoffs. The new adder architecture, named a mutated adder architecture, restructures an adder with blocks of various carry propagated adders as sub-adder-components to aid a designer in selecting his/her adder with favorable characteristics. We formulate the problem of determining the bit-width of various carry propagate component adders in integer linear programming. We demonstrate the effectiveness of the new adder architecture using 128-bit adder design","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125932453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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