Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348226
Ibrahim Elshafiey, Ashraf Mohra
Advances in magnetoresistive (MR) type sensors provide a new technique for nondestructive evaluation NDE of metal structures. MR sensors include high sensitivity and reduced size being produced by thin film processing techniques, the manufacturing cost of these sensors is low. This paper provides an attempt to develop an NDE system that depends on one type of MR sensors, namely the giant MR (GMR) elements. An example is considered of detecting defects in printed circuit boards. System details and experimental results are provided. Computational modeling validation is introduced based on finite element analysis
{"title":"Development of Metal Inspection System Exploiting Magnetoresistive Sensors","authors":"Ibrahim Elshafiey, Ashraf Mohra","doi":"10.1109/IWSOC.2006.348226","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348226","url":null,"abstract":"Advances in magnetoresistive (MR) type sensors provide a new technique for nondestructive evaluation NDE of metal structures. MR sensors include high sensitivity and reduced size being produced by thin film processing techniques, the manufacturing cost of these sensors is low. This paper provides an attempt to develop an NDE system that depends on one type of MR sensors, namely the giant MR (GMR) elements. An example is considered of detecting defects in printed circuit boards. System details and experimental results are provided. Computational modeling validation is introduced based on finite element analysis","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132049191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348240
A. Elshurafa, E. El-Masry
This paper presents extensive simulations of MEMS parallel plate variable capacitors with attention dedicated towards variations in etching holes' properties. For various separation distances between the plates, different hole sizes and density were created and capacitances were extracted. Within typical values, it was found that the configuration of the holes might affect the tuning range by no more than 16% at extreme cases of their theoretical counterparts. Simulations were done using finite element modeling
{"title":"Effects of Etching Holes on Capacitance and Tuning Range in MEMS Parallel Plate Variable Capacitors","authors":"A. Elshurafa, E. El-Masry","doi":"10.1109/IWSOC.2006.348240","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348240","url":null,"abstract":"This paper presents extensive simulations of MEMS parallel plate variable capacitors with attention dedicated towards variations in etching holes' properties. For various separation distances between the plates, different hole sizes and density were created and capacitances were extracted. Within typical values, it was found that the configuration of the holes might affect the tuning range by no more than 16% at extreme cases of their theoretical counterparts. Simulations were done using finite element modeling","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133023013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348270
J. Cetin, A. Balasinski
Technology, CAD, and design are increasingly more challenged by design-for-manufacturability rules and guidelines required to improve pattern transfer quality to the reticle and silicon wafer. One key reason for this challenge is the variability of the layout, which for SoC designs beyond the 100 nm technology node should no longer be subject only to short range design rule checks concerning individual layout features. To include the impact of medium and long-range pattern interactions (across-die or exposure field) into the design process, one should change layout architecture methodology distributed so far among technology, CAD, and design groups and using manual drawing techniques or semi-automated tools with different quality standards. This task becomes even more important for the SoC layout for analog/RF applications where signal propagation is sensitive to device matching requirements and capacitive coupling. At that point, IC designer had two options to control the layout freedom: by enforcing new, more restrictive design rules or by using parameterized layout based on standard cells proven on silicon, including all electrically extracted RET, OPC, and dummy features. In this work, it was shown that the standardized layout is the preferred option leading to the improved quality, reduced cycletime, and higher yields
{"title":"SoC Design Quality, Cycletime, and Yield Improvement Through DfM","authors":"J. Cetin, A. Balasinski","doi":"10.1109/IWSOC.2006.348270","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348270","url":null,"abstract":"Technology, CAD, and design are increasingly more challenged by design-for-manufacturability rules and guidelines required to improve pattern transfer quality to the reticle and silicon wafer. One key reason for this challenge is the variability of the layout, which for SoC designs beyond the 100 nm technology node should no longer be subject only to short range design rule checks concerning individual layout features. To include the impact of medium and long-range pattern interactions (across-die or exposure field) into the design process, one should change layout architecture methodology distributed so far among technology, CAD, and design groups and using manual drawing techniques or semi-automated tools with different quality standards. This task becomes even more important for the SoC layout for analog/RF applications where signal propagation is sensitive to device matching requirements and capacitive coupling. At that point, IC designer had two options to control the layout freedom: by enforcing new, more restrictive design rules or by using parameterized layout based on standard cells proven on silicon, including all electrically extracted RET, OPC, and dummy features. In this work, it was shown that the standardized layout is the preferred option leading to the improved quality, reduced cycletime, and higher yields","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114237046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348271
M. H. El-Malaki, M. El-Kharashi, S. Hammad, Ashraf Salem, A. Wahdan
This paper aims at providing a study on the effect of platform-based hardware/software co-design on the performance of RTOS-based systems. The followed co-design methodology is summarized, how RTOS design flow can fit into this methodology is proposed, and finally an RTOS-based system are co-designed with two configurations to illustrate the idea. The results show the suitability of the methodology followed in co-designing RTOS-based systems
{"title":"Hardware/Software Co-Design of RTOS-Based Platforms","authors":"M. H. El-Malaki, M. El-Kharashi, S. Hammad, Ashraf Salem, A. Wahdan","doi":"10.1109/IWSOC.2006.348271","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348271","url":null,"abstract":"This paper aims at providing a study on the effect of platform-based hardware/software co-design on the performance of RTOS-based systems. The followed co-design methodology is summarized, how RTOS design flow can fit into this methodology is proposed, and finally an RTOS-based system are co-designed with two configurations to illustrate the idea. The results show the suitability of the methodology followed in co-designing RTOS-based systems","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129425775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348233
M. Mostafa, M. Shalan, S. Hammad
The paper proposes a new approach for testing a CAN bus at the bit-level. It depends on generation of bus errors to cover crucial corner cases. The design makes it possible to go beyond regular frame level testing that is provided by many commercial tools. It goes deep in bit-stream level testing and injection. The proposed design is verified using an FPGA system on chip. Verification results are good against design requirements
{"title":"FPGA-Based Low-level CAN Protocol Testing","authors":"M. Mostafa, M. Shalan, S. Hammad","doi":"10.1109/IWSOC.2006.348233","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348233","url":null,"abstract":"The paper proposes a new approach for testing a CAN bus at the bit-level. It depends on generation of bus errors to cover crucial corner cases. The design makes it possible to go beyond regular frame level testing that is provided by many commercial tools. It goes deep in bit-stream level testing and injection. The proposed design is verified using an FPGA system on chip. Verification results are good against design requirements","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114065348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348261
Ahmed Abou ElFarag, H. M. El-Boghdadi, S. Shaheen
Partially reconfigurable field-programmable gate arrays (FPGAs) allow parts of the chip to be configured at runtime where each part could hold an independent task. Online placements of these tasks result in area fragmentation leading to a poor utilization of chip resources. In this paper, we propose a new metric for measuring area fragmentation. The new fragmentation metric gives an indication to the continuity of the occupied (or free) space and not the amount of occupied space. We show how this metric can be extended for multidimensional structures. We also show how this metric can be computed efficiently at run time. Next we use this measure during online placement of tasks on FPGAs, such that the chip fragmentation is reduced. Our results show improvement of chip utilization when using this fragmentation aware placement method over other placement methods with well known bottom left first fit, and best fit placement strategies
{"title":"Fragmentation Aware Placement in Reconfigurable Devices","authors":"Ahmed Abou ElFarag, H. M. El-Boghdadi, S. Shaheen","doi":"10.1109/IWSOC.2006.348261","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348261","url":null,"abstract":"Partially reconfigurable field-programmable gate arrays (FPGAs) allow parts of the chip to be configured at runtime where each part could hold an independent task. Online placements of these tasks result in area fragmentation leading to a poor utilization of chip resources. In this paper, we propose a new metric for measuring area fragmentation. The new fragmentation metric gives an indication to the continuity of the occupied (or free) space and not the amount of occupied space. We show how this metric can be extended for multidimensional structures. We also show how this metric can be computed efficiently at run time. Next we use this measure during online placement of tasks on FPGAs, such that the chip fragmentation is reduced. Our results show improvement of chip utilization when using this fragmentation aware placement method over other placement methods with well known bottom left first fit, and best fit placement strategies","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114418623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348230
S. Saif, H. M. Abbas, S. Nassar, A. Wahdan
This paper presents an implementation for image compression using variable block truncation coding (BTC) on a field programmable gate array (FPGA). The compression technique is improved by employing a cost function obtained using Hopfield neural network (HNN), upon which a block is classified as either a high- or a low-detail block. Accordingly, different blocks are coded with different bit rates and thus better compression ratios are achieved. The paper formulates the utilization of HNN within the BTC algorithm in such a way that a viable FPGA implementation is produced. The Xilinx Virtex EBTC implementation has shown to provide a processing speed of about 1.113 times 106 of pixels per second with a compression ratio which varies between 1.25 and 2 bits per pixel, according to the image homogeneity
{"title":"An FPGA Implementation of a Hopfield Optimized Block Truncation Coding","authors":"S. Saif, H. M. Abbas, S. Nassar, A. Wahdan","doi":"10.1109/IWSOC.2006.348230","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348230","url":null,"abstract":"This paper presents an implementation for image compression using variable block truncation coding (BTC) on a field programmable gate array (FPGA). The compression technique is improved by employing a cost function obtained using Hopfield neural network (HNN), upon which a block is classified as either a high- or a low-detail block. Accordingly, different blocks are coded with different bit rates and thus better compression ratios are achieved. The paper formulates the utilization of HNN within the BTC algorithm in such a way that a viable FPGA implementation is produced. The Xilinx Virtex EBTC implementation has shown to provide a processing speed of about 1.113 times 106 of pixels per second with a compression ratio which varies between 1.25 and 2 bits per pixel, according to the image homogeneity","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129080432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348234
Mohamed B. Abdelhalim, A. E. Salama, S.E.-D. Habib
In this paper the authors investigate the application of the particle swarm optimization (PSO) technique for solving the hardware/software partitioning problem. The PSO is attractive for the hardware/software partitioning problem as it offers reasonable coverage of the design space together with O(n) main loop's execution time, where n is the number of proposed solutions that will evolve to provide the final solution. The authors carried out several tests on a hypothetical, relatively-large hardware/software partitioning problem using the PSO algorithm as well as the genetic algorithm (GA), which is another evolutionary technique. The authors found that PSO outperforms GA in the cost function and the execution time. For the case of unconstrained design problem, the authors tested several hybrid combinations of PSO and GA algorithm; including PSO then GA, GA then PSO, GA followed by GA, and finally PSO followed by PSO. We found that a PSO followed by GA algorithm gives small or no improvement at all, while a GA then PSO algorithm gives the same results as the PSO alone. The PSO algorithm followed by another PSO round gave the best result as it allows another round of domain exploration. The second PSO round assign new randomized velocities to the particles, while keeping best particle positions obtained in the first round. The paper proposes to name this successive PSO algorithm as the re-excited PSO algorithm
{"title":"Hardware Software Partitioning using Particle Swarm Optimization Technique","authors":"Mohamed B. Abdelhalim, A. E. Salama, S.E.-D. Habib","doi":"10.1109/IWSOC.2006.348234","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348234","url":null,"abstract":"In this paper the authors investigate the application of the particle swarm optimization (PSO) technique for solving the hardware/software partitioning problem. The PSO is attractive for the hardware/software partitioning problem as it offers reasonable coverage of the design space together with O(n) main loop's execution time, where n is the number of proposed solutions that will evolve to provide the final solution. The authors carried out several tests on a hypothetical, relatively-large hardware/software partitioning problem using the PSO algorithm as well as the genetic algorithm (GA), which is another evolutionary technique. The authors found that PSO outperforms GA in the cost function and the execution time. For the case of unconstrained design problem, the authors tested several hybrid combinations of PSO and GA algorithm; including PSO then GA, GA then PSO, GA followed by GA, and finally PSO followed by PSO. We found that a PSO followed by GA algorithm gives small or no improvement at all, while a GA then PSO algorithm gives the same results as the PSO alone. The PSO algorithm followed by another PSO round gave the best result as it allows another round of domain exploration. The second PSO round assign new randomized velocities to the particles, while keeping best particle positions obtained in the first round. The paper proposes to name this successive PSO algorithm as the re-excited PSO algorithm","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125746118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348225
E. Mahrous, N. Rahim, P. Hew
This paper presents an analysis and design procedure of a three-phase three-level nine switches voltage source inverter using the space vector pulse width modulation (SVPWM) control scheme. The proposed inverter consists from a main inverter switches Q1, Q2 , Q3, Q4, Q5 and Q6, an auxiliary three bidirectional switches S1 S2, and S3 and two capacitor banks C1 and C2. Where ideal switches and diodes will be assumed and the dc bus capacitor bank voltages fluctuations will be absent. The effectiveness of the SVPWM control scheme is verified by the simulations results in the worst case where two very low switching frequencies values of 1 kHz and 5 kHz will be considered
{"title":"Analysis Design and Simulation of a Three-Phase Three-Level Nine Switches Inverter Using Space Vector Modulation","authors":"E. Mahrous, N. Rahim, P. Hew","doi":"10.1109/IWSOC.2006.348225","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348225","url":null,"abstract":"This paper presents an analysis and design procedure of a three-phase three-level nine switches voltage source inverter using the space vector pulse width modulation (SVPWM) control scheme. The proposed inverter consists from a main inverter switches Q<sub>1</sub>, Q<sub>2 </sub>, Q<sub>3</sub>, Q<sub>4</sub>, Q<sub>5</sub> and Q<sub>6</sub>, an auxiliary three bidirectional switches S<sub>1</sub> S<sub>2</sub>, and S<sub>3</sub> and two capacitor banks C<sub>1</sub> and C<sub>2</sub>. Where ideal switches and diodes will be assumed and the dc bus capacitor bank voltages fluctuations will be absent. The effectiveness of the SVPWM control scheme is verified by the simulations results in the worst case where two very low switching frequencies values of 1 kHz and 5 kHz will be considered","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126949591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348273
S. Aly, A. Salem
In this paper, we are inspired by similarities between system on chip (SoC) and networked systems to introduce a new modeling abstraction above transaction level modeling (TLM). We use concepts of the famous session initiation protocol (SIP) to introduce a new abstraction level for bus protocol modeling above the transaction modeling layer, namely session level modeling. Primitives of our proposed session modeling layer are directly inspired from SIP. In our modeling approach, session establishment expresses the semantics of acquiring the bus, along with the readiness of the slave device. We implemented the session level primitives using Java, a very capable language for modeling SoC, and demonstrated how such primitives could be used in multilevel modeling
{"title":"SoC Session Level Modeling using Java","authors":"S. Aly, A. Salem","doi":"10.1109/IWSOC.2006.348273","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348273","url":null,"abstract":"In this paper, we are inspired by similarities between system on chip (SoC) and networked systems to introduce a new modeling abstraction above transaction level modeling (TLM). We use concepts of the famous session initiation protocol (SIP) to introduce a new abstraction level for bus protocol modeling above the transaction modeling layer, namely session level modeling. Primitives of our proposed session modeling layer are directly inspired from SIP. In our modeling approach, session establishment expresses the semantics of acquiring the bus, along with the readiness of the slave device. We implemented the session level primitives using Java, a very capable language for modeling SoC, and demonstrated how such primitives could be used in multilevel modeling","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115325159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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