Pub Date : 2016-12-31DOI: 10.6109/JKIICE.2016.20.12.2289
Jongmun Jeong, Mintae Hwang
The password rules to be applied for the user account creation are often different by websites. Thus we often forget the password to sign in website and it creates waste of time for frequent password reset. In order to solve this problem we propose a new authentication method in this paper. When user forget the password to sign in, the existing methods require a password reset step but our proposed method provides new sign in scheme through the additional authentication step with base password and personal information registered at the member sign up stage. From the result of performance comparison the proposed method is considered to be more efficient than others because it provides not only an equivalent level of security with others but also requires only a half of the number of transactions and the time required for password reset step.
{"title":"User Authentication System using Base Password and Member Registration Information","authors":"Jongmun Jeong, Mintae Hwang","doi":"10.6109/JKIICE.2016.20.12.2289","DOIUrl":"https://doi.org/10.6109/JKIICE.2016.20.12.2289","url":null,"abstract":"The password rules to be applied for the user account creation are often different by websites. Thus we often forget the password to sign in website and it creates waste of time for frequent password reset. In order to solve this problem we propose a new authentication method in this paper. When user forget the password to sign in, the existing methods require a password reset step but our proposed method provides new sign in scheme through the additional authentication step with base password and personal information registered at the member sign up stage. From the result of performance comparison the proposed method is considered to be more efficient than others because it provides not only an equivalent level of security with others but also requires only a half of the number of transactions and the time required for password reset step.","PeriodicalId":136663,"journal":{"name":"The Journal of the Korean Institute of Information and Communication Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130118506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-31DOI: 10.6109/JKIICE.2016.20.12.2333
Mi-Ji Sung, K. Shin
A LEA (Lightweight Encryption Algorithm) crypto-processor was designed, which supports three master key lengths of 128/ 192/256-bit, ECB and CTR modes of operation. To achieve high throughput rate, the round transformation block was designed with 128 bits datapath and a pipelined structure of 16 stages. Encryption/decryption is carried out through 12/14/16 pipelined stages according to the master key length, and each pipelined stage performs round transformation twice. The key scheduler block was optimized to share hardware resources that are required for encryption, decryption, and three master key lengths. The round keys generated by key scheduler are stored in 32 round key registers, and are repeatedly used in round transformation until master key is updated. The pipelined LEA processor was verified by FPGA implementation, and the estimated performance is about 8.3 Gbps at the maximum clock frequency of 130 MHz. 키워드 : LEA, 블록암호, 정보보안, 고성능 암호, 운영모드 Key word : LEA, block cipher, information security, high performance encryption, modes of operation Received 08 July 2016, Revised 11 July 2016, Accepted 18 July 2016 * Corresponding Author Kyung-Wook Shin(E-mail:kwshin@kumoh.ac.kr, Tel:+82-54-478-7427) School of Electronic Engineering, Kumoh National Institute of Technology, Gumi, Kyungbuk, 39177, Korea Open Access http://doi.org/10.6109/jkiice.2016.20.12.2333 print ISSN: 2234-4772 online ISSN: 2288-4165 This is an Open Access article distributed under the terms of the Creative Commons Attribution Non-Commercial License(http://creativecommons.org/li-censes/ by-nc/3.0/) which permits unrestricted non-commercial use, distribution, and reproduction in any medium, provided the original work is properly cited. Copyright C The Korea Institute of Information and Communication Engineering. Journal of the Korea Institute of Information and Communication Engineering 한국정보통신학회논문지(J. Korea Inst. Inf. Commun. Eng.) Vol. 20, No. 12 : 2333~2340 Dec. 2016
{"title":"8.3 Gbps pipelined LEA Crypto-Processor Supporting ECB/CTR Modes of operation","authors":"Mi-Ji Sung, K. Shin","doi":"10.6109/JKIICE.2016.20.12.2333","DOIUrl":"https://doi.org/10.6109/JKIICE.2016.20.12.2333","url":null,"abstract":"A LEA (Lightweight Encryption Algorithm) crypto-processor was designed, which supports three master key lengths of 128/ 192/256-bit, ECB and CTR modes of operation. To achieve high throughput rate, the round transformation block was designed with 128 bits datapath and a pipelined structure of 16 stages. Encryption/decryption is carried out through 12/14/16 pipelined stages according to the master key length, and each pipelined stage performs round transformation twice. The key scheduler block was optimized to share hardware resources that are required for encryption, decryption, and three master key lengths. The round keys generated by key scheduler are stored in 32 round key registers, and are repeatedly used in round transformation until master key is updated. The pipelined LEA processor was verified by FPGA implementation, and the estimated performance is about 8.3 Gbps at the maximum clock frequency of 130 MHz. 키워드 : LEA, 블록암호, 정보보안, 고성능 암호, 운영모드 Key word : LEA, block cipher, information security, high performance encryption, modes of operation Received 08 July 2016, Revised 11 July 2016, Accepted 18 July 2016 * Corresponding Author Kyung-Wook Shin(E-mail:kwshin@kumoh.ac.kr, Tel:+82-54-478-7427) School of Electronic Engineering, Kumoh National Institute of Technology, Gumi, Kyungbuk, 39177, Korea Open Access http://doi.org/10.6109/jkiice.2016.20.12.2333 print ISSN: 2234-4772 online ISSN: 2288-4165 This is an Open Access article distributed under the terms of the Creative Commons Attribution Non-Commercial License(http://creativecommons.org/li-censes/ by-nc/3.0/) which permits unrestricted non-commercial use, distribution, and reproduction in any medium, provided the original work is properly cited. Copyright C The Korea Institute of Information and Communication Engineering. Journal of the Korea Institute of Information and Communication Engineering 한국정보통신학회논문지(J. Korea Inst. Inf. Commun. Eng.) Vol. 20, No. 12 : 2333~2340 Dec. 2016","PeriodicalId":136663,"journal":{"name":"The Journal of the Korean Institute of Information and Communication Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114613266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-31DOI: 10.6109/JKIICE.2016.20.12.2401
S. Tak
Android CPU governors exploit the DVFS (Dynamic Voltage Frequency Scaling) technique. The DVFS is a power management technique where the CPU operating frequency is decreased to allow a corresponding reduction in the CPU supply voltage. The power consumed by a CPU is approximately proportional to the square of the CPU supply voltage. Therefore, lower CPU operating frequency allows the CPU supply voltage to be lowered. This helps to reduce the CPU power consumption. However, lower CPU operating frequency increases a task’s execution time. Such an increase in the task’s execution time makes the task’s response time longer and makes the task’s deadline miss occur. This finally leads to degrading the quality of service provided by the task. In this paper, we evaluated the performance of Android CPU governors in terms of the power consumption, tasks‘s response time and deadline miss ratio. 키워드 : 안드로이드 거버너, 저전력, 실시간, 동적 전압 주파수 조절 Key word : Android governor, Low-power, Real-time, Dynamic voltage frequency scaling Received 18 July 2016, Revised 21 July 2016, Accepted 04 August 2016 * Corresponding Author Sungwoo Tak(E-mail:swtak@pusan.ac.kr, Tel:+82-51-510-2387) Department of Computer Science and Engineering, Pusan National University, Pusan 46241, Korea Open Access http://doi.org/10.6109/jkiice.2016.20.12.2401 print ISSN: 2234-4772 online ISSN: 2288-4165 This is an Open Access article distributed under the terms of the Creative Commons Attribution Non-Commercial License(http://creativecommons.org/li-censes/ by-nc/3.0/) which permits unrestricted non-commercial use, distribution, and reproduction in any medium, provided the original work is properly cited. Copyright C The Korea Institute of Information and Communication Engineering. Journal of the Korea Institute of Information and Communication Engineering 한국정보통신학회논문지(J. Korea Inst. Inf. Commun. Eng.) Vol. 20, No. 12 : 2401~2409 Dec. 2016
{"title":"Evaluating Power Consumption and Real-time Performance of Android CPU Governors","authors":"S. Tak","doi":"10.6109/JKIICE.2016.20.12.2401","DOIUrl":"https://doi.org/10.6109/JKIICE.2016.20.12.2401","url":null,"abstract":"Android CPU governors exploit the DVFS (Dynamic Voltage Frequency Scaling) technique. The DVFS is a power management technique where the CPU operating frequency is decreased to allow a corresponding reduction in the CPU supply voltage. The power consumed by a CPU is approximately proportional to the square of the CPU supply voltage. Therefore, lower CPU operating frequency allows the CPU supply voltage to be lowered. This helps to reduce the CPU power consumption. However, lower CPU operating frequency increases a task’s execution time. Such an increase in the task’s execution time makes the task’s response time longer and makes the task’s deadline miss occur. This finally leads to degrading the quality of service provided by the task. In this paper, we evaluated the performance of Android CPU governors in terms of the power consumption, tasks‘s response time and deadline miss ratio. 키워드 : 안드로이드 거버너, 저전력, 실시간, 동적 전압 주파수 조절 Key word : Android governor, Low-power, Real-time, Dynamic voltage frequency scaling Received 18 July 2016, Revised 21 July 2016, Accepted 04 August 2016 * Corresponding Author Sungwoo Tak(E-mail:swtak@pusan.ac.kr, Tel:+82-51-510-2387) Department of Computer Science and Engineering, Pusan National University, Pusan 46241, Korea Open Access http://doi.org/10.6109/jkiice.2016.20.12.2401 print ISSN: 2234-4772 online ISSN: 2288-4165 This is an Open Access article distributed under the terms of the Creative Commons Attribution Non-Commercial License(http://creativecommons.org/li-censes/ by-nc/3.0/) which permits unrestricted non-commercial use, distribution, and reproduction in any medium, provided the original work is properly cited. Copyright C The Korea Institute of Information and Communication Engineering. Journal of the Korea Institute of Information and Communication Engineering 한국정보통신학회논문지(J. Korea Inst. Inf. Commun. Eng.) Vol. 20, No. 12 : 2401~2409 Dec. 2016","PeriodicalId":136663,"journal":{"name":"The Journal of the Korean Institute of Information and Communication Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116104045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-31DOI: 10.6109/JKIICE.2016.20.12.2363
김영준, 조기옥, 한재승, 조명진
본 논문에서는 집적 영상과 컴퓨터 재생 기술을 활용한 3차원 QR 코드 생성 기술을 제안한다. 제안하는 기술에서는 2차원 QR 코드를 네 개의 면으로 나누어 각각의 면을 서로 다른 깊이에 배치한 뒤 깊이가 추가된 3차원 QR 코드를 합성조리개 집적 영상과 컴퓨터 재생 기술을 사용하여 생성한다. 이 과정에서 3차원 영상 기술 중 하나인 집적 영상 기술을 사용한다. 마지막으로, 3차원 QR 코드를 집적영상을 이용하여 컴퓨터 재생을 한 뒤 각 면을 배치했던 깊이 부분에서 영상을 재생하고 조합하면 3차원 QR 코드를 읽을 수 있다. 따라서 QR 코드를 읽을 때 보안을 강화할 수 있다. 본 논문에서는 제안된 기술이 QR 코드를 읽을 때 보안을 강화할 수 있음을 보이기 위하여 광학적 실험과 컴퓨터 재생을 수행하였다. 또한, 재생 깊이를 알고 있을 때, 3차원 QR 코드를 읽을 수 있음을 보였다.
{"title":"집적 영상을 활용한 3차원 QR code","authors":"김영준, 조기옥, 한재승, 조명진","doi":"10.6109/JKIICE.2016.20.12.2363","DOIUrl":"https://doi.org/10.6109/JKIICE.2016.20.12.2363","url":null,"abstract":"본 논문에서는 집적 영상과 컴퓨터 재생 기술을 활용한 3차원 QR 코드 생성 기술을 제안한다. 제안하는 기술에서는 2차원 QR 코드를 네 개의 면으로 나누어 각각의 면을 서로 다른 깊이에 배치한 뒤 깊이가 추가된 3차원 QR 코드를 합성조리개 집적 영상과 컴퓨터 재생 기술을 사용하여 생성한다. 이 과정에서 3차원 영상 기술 중 하나인 집적 영상 기술을 사용한다. 마지막으로, 3차원 QR 코드를 집적영상을 이용하여 컴퓨터 재생을 한 뒤 각 면을 배치했던 깊이 부분에서 영상을 재생하고 조합하면 3차원 QR 코드를 읽을 수 있다. 따라서 QR 코드를 읽을 때 보안을 강화할 수 있다. 본 논문에서는 제안된 기술이 QR 코드를 읽을 때 보안을 강화할 수 있음을 보이기 위하여 광학적 실험과 컴퓨터 재생을 수행하였다. 또한, 재생 깊이를 알고 있을 때, 3차원 QR 코드를 읽을 수 있음을 보였다.","PeriodicalId":136663,"journal":{"name":"The Journal of the Korean Institute of Information and Communication Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115998942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-31DOI: 10.6109/JKIICE.2016.20.12.2226
Seung-kuk Choi
{"title":"Performance Degradation of OFDMA Systems owing to Multi-User Interference","authors":"Seung-kuk Choi","doi":"10.6109/JKIICE.2016.20.12.2226","DOIUrl":"https://doi.org/10.6109/JKIICE.2016.20.12.2226","url":null,"abstract":"","PeriodicalId":136663,"journal":{"name":"The Journal of the Korean Institute of Information and Communication Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131533790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-31DOI: 10.6109/JKIICE.2016.20.12.2317
손지수, 이한열, 김영웅, 장영찬
본 논문은 reference driver를 이용한 10비트 10MS/s 축차근사형(SAR: Successive Approximation Register) 아날로그-디지털 변환기(ADC: Analog-to-Digital Converter)를 제안한다. 제안하는 SAR ADC는 커패시터형 디지털-아날로그 변환기(CDAC: Capacitive Digital-to-Analog Converter), 비교기, SAR 로직, 그리고 공급 전압 노이즈에 대한 내성을 향상시키는 reference driver로 구성된다. ±0.9V의 아날로그 입력전압을 가지는 SAR ADC를 위해 reference driver는 0.45V, 1.35V의 기준 전압을 생성한다. 설계된 SAR ADC는 0.18μm CMOS 공정을 이용하여 제작되었으며 1.8V의 공급전압을 사용하였다. 제안된 SAR ADC는 reference driver를 이용하여 +/- 200mV의 공급 전압 변화에서도 ±0.9V의 입력 범위를 유지한다. 10MS/s의 샘플링 주파수에서 5.32mW의 전력을 소모한다. 측정된 ENOB는 9.11 비트 이며, DNL과 INL은 각각 +0.60/-0.74 LSB와 +0.69/-0.65 LSB이다.
{"title":"Reference Driver를 사용한 10비트 10MS/s 축차근사형 아날로그-디지털 변환기","authors":"손지수, 이한열, 김영웅, 장영찬","doi":"10.6109/JKIICE.2016.20.12.2317","DOIUrl":"https://doi.org/10.6109/JKIICE.2016.20.12.2317","url":null,"abstract":"본 논문은 reference driver를 이용한 10비트 10MS/s 축차근사형(SAR: Successive Approximation Register) 아날로그-디지털 변환기(ADC: Analog-to-Digital Converter)를 제안한다. 제안하는 SAR ADC는 커패시터형 디지털-아날로그 변환기(CDAC: Capacitive Digital-to-Analog Converter), 비교기, SAR 로직, 그리고 공급 전압 노이즈에 대한 내성을 향상시키는 reference driver로 구성된다. ±0.9V의 아날로그 입력전압을 가지는 SAR ADC를 위해 reference driver는 0.45V, 1.35V의 기준 전압을 생성한다. 설계된 SAR ADC는 0.18μm CMOS 공정을 이용하여 제작되었으며 1.8V의 공급전압을 사용하였다. 제안된 SAR ADC는 reference driver를 이용하여 +/- 200mV의 공급 전압 변화에서도 ±0.9V의 입력 범위를 유지한다. 10MS/s의 샘플링 주파수에서 5.32mW의 전력을 소모한다. 측정된 ENOB는 9.11 비트 이며, DNL과 INL은 각각 +0.60/-0.74 LSB와 +0.69/-0.65 LSB이다.","PeriodicalId":136663,"journal":{"name":"The Journal of the Korean Institute of Information and Communication Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125668362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-31DOI: 10.6109/JKIICE.2016.20.12.2252
Choon-Seo Jang
CCMP(centralized conferencing manipulation protocol) enables adding and removing conference participants, changing their roles, adding and removing media streams in conference system. In this paper, by using extended CCMP, a new distributed conference system architecture which can be used to multiple servers distributed conference system in SIP(session initiation protocol) environment has been presented. In this study, according to increasing number of participants, a new extended CCMP architecture which can distribute conference system loads to multiple servers dynamically to decrease loads of servers has been designed. This extended CCMP architecture also can add dynamically new servers from the prepared servers pool. Furthermore, new conference information data format which can represent extended CCMP has been designed, and exchange procedures of extended CCMP control messages which can distribute loads between servers have also been presented. The performance of the proposed system has been analysed by simulation.
{"title":"A New Distributed Conference System Architecture using Extended CCMP in SIP Environment","authors":"Choon-Seo Jang","doi":"10.6109/JKIICE.2016.20.12.2252","DOIUrl":"https://doi.org/10.6109/JKIICE.2016.20.12.2252","url":null,"abstract":"CCMP(centralized conferencing manipulation protocol) enables adding and removing conference participants, changing their roles, adding and removing media streams in conference system. In this paper, by using extended CCMP, a new distributed conference system architecture which can be used to multiple servers distributed conference system in SIP(session initiation protocol) environment has been presented. In this study, according to increasing number of participants, a new extended CCMP architecture which can distribute conference system loads to multiple servers dynamically to decrease loads of servers has been designed. This extended CCMP architecture also can add dynamically new servers from the prepared servers pool. Furthermore, new conference information data format which can represent extended CCMP has been designed, and exchange procedures of extended CCMP control messages which can distribute loads between servers have also been presented. The performance of the proposed system has been analysed by simulation.","PeriodicalId":136663,"journal":{"name":"The Journal of the Korean Institute of Information and Communication Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124702091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-31DOI: 10.6109/JKIICE.2016.20.12.2267
Kyeong Hur
{"title":"Performance Analysis of Multicast Relay Transmissions in WiMedia D-MAC for OSMU N-Screen Services","authors":"Kyeong Hur","doi":"10.6109/JKIICE.2016.20.12.2267","DOIUrl":"https://doi.org/10.6109/JKIICE.2016.20.12.2267","url":null,"abstract":"","PeriodicalId":136663,"journal":{"name":"The Journal of the Korean Institute of Information and Communication Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128110170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-31DOI: 10.6109/JKIICE.2016.20.12.2341
Sehum Park, Youngchoong Geum, Hyun-jae Kim
{"title":"Monitoring system for grain sorting using embedded Linux-based servers and Web applications","authors":"Sehum Park, Youngchoong Geum, Hyun-jae Kim","doi":"10.6109/JKIICE.2016.20.12.2341","DOIUrl":"https://doi.org/10.6109/JKIICE.2016.20.12.2341","url":null,"abstract":"","PeriodicalId":136663,"journal":{"name":"The Journal of the Korean Institute of Information and Communication Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132629798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-31DOI: 10.6109/JKIICE.2016.20.12.2310
Jong-yeol Kim, N. Lee, Hyunkyu Jung
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