Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302209
D. M. Miller
This paper describes an algorithm which performs a spectral transformation of a multiple-valued function directly from a decision diagram representation. The spectrum is in turn represented as a decision diagram. The advantage of adding cycle operations to a spectral decision diagram is shown. The complexity of the representation of the spectrum is not fixed as in the matrix case and is shown to be quite compact for many 'practical' functions. Likewise, the execution time of the algorithm is not fixed as it depends on the complexity of the decision diagram representations of the function and the spectrum. This transformation algorithm opens the possibility of broader application of spectral logic design techniques particularly to functions with more variables than could be considered using earlier matrix transformation techniques. The algorithm is applicable to binary functions and to systems of functions. It is readily extended to other transformations with a recursive matrix definition.<>
{"title":"Spectral transformation of multiple-valued decision diagrams","authors":"D. M. Miller","doi":"10.1109/ISMVL.1994.302209","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302209","url":null,"abstract":"This paper describes an algorithm which performs a spectral transformation of a multiple-valued function directly from a decision diagram representation. The spectrum is in turn represented as a decision diagram. The advantage of adding cycle operations to a spectral decision diagram is shown. The complexity of the representation of the spectrum is not fixed as in the matrix case and is shown to be quite compact for many 'practical' functions. Likewise, the execution time of the algorithm is not fixed as it depends on the complexity of the decision diagram representations of the function and the spectrum. This transformation algorithm opens the possibility of broader application of spectral logic design techniques particularly to functions with more variables than could be considered using earlier matrix transformation techniques. The algorithm is applicable to binary functions and to systems of functions. It is readily extended to other transformations with a recursive matrix definition.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124685688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302214
Z. Stachniak
We study classes of logical calculi which have the same inconsistent sets of formulas. We investigate the algebraic structure of these classes as well as general properties of logical calculi in these classes in the context of the search for efficient resolution based automated reasoning methods.<>
{"title":"Lattices of resolution logics","authors":"Z. Stachniak","doi":"10.1109/ISMVL.1994.302214","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302214","url":null,"abstract":"We study classes of logical calculi which have the same inconsistent sets of formulas. We investigate the algebraic structure of these classes as well as general properties of logical calculi in these classes in the context of the search for efficient resolution based automated reasoning methods.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124584210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302206
C. Moraga, J. Cañas, R. Monge, L. Salinas, Manuel Gómez
Rule based systems are computationally very demanding, since a large number of rules has to be evaluated every time new input data are observed in order to undertake a corresponding action. The authors study the possible improvements in performance by using parallel processing. Both fine grade algorithms and standard multiprocessor architectures for Mamdani-type fuzzy systems with two inputs and one output are considered. It is shown, that a speed-up close to linear may be achieved. The results may be extended to systems with more than two inputs.<>
{"title":"Parallel processing of fuzzy inferences","authors":"C. Moraga, J. Cañas, R. Monge, L. Salinas, Manuel Gómez","doi":"10.1109/ISMVL.1994.302206","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302206","url":null,"abstract":"Rule based systems are computationally very demanding, since a large number of rules has to be evaluated every time new input data are observed in order to undertake a corresponding action. The authors study the possible improvements in performance by using parallel processing. Both fine grade algorithms and standard multiprocessor architectures for Mamdani-type fuzzy systems with two inputs and one output are considered. It is shown, that a speed-up close to linear may be achieved. The results may be extended to systems with more than two inputs.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123008325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302217
G. Dueck, J. T. Butler
We propose the use of universal literals as a means of reducing the cost of multiple-valued circuits. A universal literal is any function on one variable. The target architecture is a sum-of-products structure, where sum is the truncated sum and product terms consist of the minimum of universal literals. A significant cost reduction is demonstrated over the conventional window literal. The proposed synthesis method starts with a sum-of-products expression. Simplification occurs as pairs of product terms are merged and reshaped. We show under what conditions such operations can be applied.<>
{"title":"Multiple-valued logic operations with universal literals","authors":"G. Dueck, J. T. Butler","doi":"10.1109/ISMVL.1994.302217","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302217","url":null,"abstract":"We propose the use of universal literals as a means of reducing the cost of multiple-valued circuits. A universal literal is any function on one variable. The target architecture is a sum-of-products structure, where sum is the truncated sum and product terms consist of the minimum of universal literals. A significant cost reduction is demonstrated over the conventional window literal. The proposed synthesis method starts with a sum-of-products expression. Simplification occurs as pairs of product terms are merged and reshaped. We show under what conditions such operations can be applied.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127244890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302190
E. Sanchez
Soft computing stands for methods and techniques in fuzzy logic, probabilistic reasoning, neural networks, genetic algorithms, chaos or other approaches related to cognitive modeling. These overlapping domains can reinforce each other, thus offering suitable tools to represent and solve real world problems. Genetic algorithms and classifier systems are introduced in the framework of soft computing. Their interactions with other fields are discussed, especially in relation to neural networks and fuzzy logic based systems of If-Then rules. It finally presents fuzzy genetic algorithms involving soft (fuzzy) crossover operators.<>
{"title":"Soft computing perspectives","authors":"E. Sanchez","doi":"10.1109/ISMVL.1994.302190","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302190","url":null,"abstract":"Soft computing stands for methods and techniques in fuzzy logic, probabilistic reasoning, neural networks, genetic algorithms, chaos or other approaches related to cognitive modeling. These overlapping domains can reinforce each other, thus offering suitable tools to represent and solve real world problems. Genetic algorithms and classifier systems are introduced in the framework of soft computing. Their interactions with other fields are discussed, especially in relation to neural networks and fuzzy logic based systems of If-Then rules. It finally presents fuzzy genetic algorithms involving soft (fuzzy) crossover operators.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121952849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302225
W. Chu, K. Current
A new quaternary multiplier circuit is presented. This current-mode CMOS circuit multiplies the values of two quaternary-valued input currents and adds a ternary-valued carry input current to generate the two-quaternary-digit output: a most-significant-digit ternary-valued CARRY output current and a quaternary-valued PRODUCT output current. This multiplier circuit uses 49 MOS transistors and generates its outputs in about 10 microseconds, worst case.<>
{"title":"Quaternary multiplier circuit","authors":"W. Chu, K. Current","doi":"10.1109/ISMVL.1994.302225","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302225","url":null,"abstract":"A new quaternary multiplier circuit is presented. This current-mode CMOS circuit multiplies the values of two quaternary-valued input currents and adds a ternary-valued carry input current to generate the two-quaternary-digit output: a most-significant-digit ternary-valued CARRY output current and a quaternary-valued PRODUCT output current. This multiplier circuit uses 49 MOS transistors and generates its outputs in about 10 microseconds, worst case.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125318674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302221
Hui Min Wang, Chung-Len Lee, Jwu-E Chen
Presents the concept of algebraic division for multilevel logic synthesis of multi-valued logic (MVL). At first, an MVL algebraic division procedure is developed based on a basic set of gates. By introducing two MVL Boolean properties: "identical" and "complementary" into the division operation, the procedure is further improved to be a mix-algebraic division procedure, which can obtain more efficient algebraic division to facilitate multilevel logic synthesis of MVL functions. Experimental results show that, in average, the multilevel implementation cost for an MVL function can have 30.1% cost saving over the two-level implementation, and the improved mix-algebraic division procedure can have 19.4% cost saving over the algebraic division procedure.<>
{"title":"Algebraic division for multilevel logic synthesis of multi-valued logic circuits","authors":"Hui Min Wang, Chung-Len Lee, Jwu-E Chen","doi":"10.1109/ISMVL.1994.302221","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302221","url":null,"abstract":"Presents the concept of algebraic division for multilevel logic synthesis of multi-valued logic (MVL). At first, an MVL algebraic division procedure is developed based on a basic set of gates. By introducing two MVL Boolean properties: \"identical\" and \"complementary\" into the division operation, the procedure is further improved to be a mix-algebraic division procedure, which can obtain more efficient algebraic division to facilitate multilevel logic synthesis of MVL functions. Experimental results show that, in average, the multilevel implementation cost for an MVL function can have 30.1% cost saving over the two-level implementation, and the improved mix-algebraic division procedure can have 19.4% cost saving over the algebraic division procedure.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116987243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302226
C. Seger, R. Bryant
Many aspects of digital circuit operation can be efficiently verified by simulating circuit operation over "weakened" state values. This technique has long been practiced with logic simulators, using the value X to indicate a signal that could be either 0 or 1. This concept can be formally extended to a wider class of circuit models and signal values, yielding lattice-structured state domains. For more precise modeling of circuit operation, these values can be encoded in binary and hence represented symbolically as ordered binary decision diagrams. The net result is a tool for formal verification that can apply a hybrid of symbolic and partially-ordered evaluation.<>
{"title":"Digital circuit verification using partially-ordered state models","authors":"C. Seger, R. Bryant","doi":"10.1109/ISMVL.1994.302226","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302226","url":null,"abstract":"Many aspects of digital circuit operation can be efficiently verified by simulating circuit operation over \"weakened\" state values. This technique has long been practiced with logic simulators, using the value X to indicate a signal that could be either 0 or 1. This concept can be formally extended to a wider class of circuit models and signal values, yielding lattice-structured state domains. For more precise modeling of circuit operation, these values can be encoded in binary and hence represented symbolically as ordered binary decision diagrams. The net result is a tool for formal verification that can apply a hybrid of symbolic and partially-ordered evaluation.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115839091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302184
C. Reischer, D. Simovici, I. Stojmenovic
Following our previous results on axiomatization of entropy of finite functions we introduce an axiomatization of the notion of entropy for equivalence relations. Also, we examine entropic properties of several classes of functions.<>
{"title":"Several remarks on algebraic entropy","authors":"C. Reischer, D. Simovici, I. Stojmenovic","doi":"10.1109/ISMVL.1994.302184","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302184","url":null,"abstract":"Following our previous results on axiomatization of entropy of finite functions we introduce an axiomatization of the notion of entropy for equivalence relations. Also, we examine entropic properties of several classes of functions.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131690155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302196
T. Takimoto, T. Aoki, T. Higuchi
The concept of multiplex interconnection networks is proposed to attack the communication crisis in massively parallel computing in the next generation. In the multiplex interconnection network, multiplexable information carriers, such as optical wavelengths, are employed so that large-scale communication topologies can be embedded in the virtual space of multiplexable carriers with reduced interconnections. This paper discusses a systematic multiplexing scheme for the class of interconnection networks defined by bit-permute-complement (BPC) permutations. It is shown that by using the proposed technique, the wiring area can be reduced by less than the factor of 1/r using r kinds of multiplexable components.<>
{"title":"Design of multiplex interconnection networks for massively parallel computing systems","authors":"T. Takimoto, T. Aoki, T. Higuchi","doi":"10.1109/ISMVL.1994.302196","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302196","url":null,"abstract":"The concept of multiplex interconnection networks is proposed to attack the communication crisis in massively parallel computing in the next generation. In the multiplex interconnection network, multiplexable information carriers, such as optical wavelengths, are employed so that large-scale communication topologies can be embedded in the virtual space of multiplexable carriers with reduced interconnections. This paper discusses a systematic multiplexing scheme for the class of interconnection networks defined by bit-permute-complement (BPC) permutations. It is shown that by using the proposed technique, the wiring area can be reduced by less than the factor of 1/r using r kinds of multiplexable components.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124621190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：