Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302204
Feb J. Cabrasawan, T. Wesselkamper
Recent advances in laser and fiber optic technology have made it feasible to build optical processors which are based upon value systems larger than E(2)={0,1}. The problem of designing a transistor which can be used as the basis for the circuits of such a processor involves a detailed study of functions which are either complete or complete with constants over E(3) and E(4). The radii of all complete functions over E(3) have been calculated but the sequential methods used cannot be applied over E(4). The authors use the known results for E(3) to develop genetic algorithm techniques to "grow" functions over E(3) with small radii. The paper ends with a discussion of the modifications needed to move the techniques developed for E(3) to a massively parallel environment so that complete functions over E(4) with small radii may be developed.<>
{"title":"Searching for complete functions over E(3) with small radii","authors":"Feb J. Cabrasawan, T. Wesselkamper","doi":"10.1109/ISMVL.1994.302204","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302204","url":null,"abstract":"Recent advances in laser and fiber optic technology have made it feasible to build optical processors which are based upon value systems larger than E(2)={0,1}. The problem of designing a transistor which can be used as the basis for the circuits of such a processor involves a detailed study of functions which are either complete or complete with constants over E(3) and E(4). The radii of all complete functions over E(3) have been calculated but the sequential methods used cannot be applied over E(4). The authors use the known results for E(3) to develop genetic algorithm techniques to \"grow\" functions over E(3) with small radii. The paper ends with a discussion of the modifications needed to move the techniques developed for E(3) to a massively parallel environment so that complete functions over E(4) with small radii may be developed.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121331643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302210
A. Kazeminejad, K. Navi, D. Etiemble
We present the basic structure and performance of CML current mode full adders, that are used as carry save adders (CSA) in combinatorial multipliers. A 1.2 /spl mu/m BiCMOS technology is used for simulations but the schematic assumes a 2.5-V power supply. Compared with binary voltage mode CSAs, the multivalued current mode CSAs have chip area and power dissipation advantage, but speed disadvantage. The current mode version is far more sensitive to power supply and temperature shifts.<>
{"title":"CML current mode full adders for 2.5-V power supply","authors":"A. Kazeminejad, K. Navi, D. Etiemble","doi":"10.1109/ISMVL.1994.302210","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302210","url":null,"abstract":"We present the basic structure and performance of CML current mode full adders, that are used as carry save adders (CSA) in combinatorial multipliers. A 1.2 /spl mu/m BiCMOS technology is used for simulations but the schematic assumes a 2.5-V power supply. Compared with binary voltage mode CSAs, the multivalued current mode CSAs have chip area and power dissipation advantage, but speed disadvantage. The current mode version is far more sensitive to power supply and temperature shifts.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116344811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302193
M. Baaz, R. Zach
The problem of approximating a propositional calculus is to find many-valued logics which are sound for the calculus (i.e., all theorems of the calculus are tautologies) with as few tautologies as possible. This has potential applications for representing (computationally complex) logics used in AI by (computationally easy) many-valued logics. It is investigated how far this method can be carried using (1) one or (2) an infinite sequence of many-valued logics. It is shown that the optimal candidate matrices for (1) can be computed from the calculus.<>
{"title":"Approximating propositional calculi by finite-valued logics","authors":"M. Baaz, R. Zach","doi":"10.1109/ISMVL.1994.302193","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302193","url":null,"abstract":"The problem of approximating a propositional calculus is to find many-valued logics which are sound for the calculus (i.e., all theorems of the calculus are tautologies) with as few tautologies as possible. This has potential applications for representing (computationally complex) logics used in AI by (computationally easy) many-valued logics. It is investigated how far this method can be carried using (1) one or (2) an infinite sequence of many-valued logics. It is shown that the optimal candidate matrices for (1) can be computed from the calculus.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131843103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302187
N. Kamiura, Y. Hata, K. Yamato
This paper discusses the problems of the design and the fault tolerance in multiple-valued cellular arrays by considering the single-level array, the two-level array and the three-level array. These arrays are constructed by some cells that have the unique switch operation. It assumes the stuck-at-0 fault and the stuck-at-(k-1) fault of the switch cells on k-valued cellular arrays. The fault-tolerant arrays for the single fault are constructed by building a duplicate row and a duplicate column iteratively in the arrays. By evaluating three types for the design, the fault tolerance and the testability for multiple faults, it clarifies that the two-level array is the most suitable structure. Finally, the comparison with formerly presented arrays shows advantages for our fault-tolerant two-level array.<>
{"title":"Design of fault-tolerant cellular arrays on multiple-valued logic","authors":"N. Kamiura, Y. Hata, K. Yamato","doi":"10.1109/ISMVL.1994.302187","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302187","url":null,"abstract":"This paper discusses the problems of the design and the fault tolerance in multiple-valued cellular arrays by considering the single-level array, the two-level array and the three-level array. These arrays are constructed by some cells that have the unique switch operation. It assumes the stuck-at-0 fault and the stuck-at-(k-1) fault of the switch cells on k-valued cellular arrays. The fault-tolerant arrays for the single fault are constructed by building a duplicate row and a duplicate column iteratively in the arrays. By evaluating three types for the design, the fault tolerance and the testability for multiple faults, it clarifies that the two-level array is the most suitable structure. Finally, the comparison with formerly presented arrays shows advantages for our fault-tolerant two-level array.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114065922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302220
Y. Hata, K. Yamato
This paper presents a new multiple-valued sum-of-products expression structure and shows its minimization to reduce the number of implicants needed in the minimal sum-of-products expressions. The new expression is introduced as the MAX-of-MIN's expression of Kleenean coefficients and one or more literals, where Kleenean coefficients are defined as the logic formulas built from MIN, constants and variables xi and x~i~. It shows a minimization of the above expressions based on binary Quine McCluskey algorithm. The result of computer simulation shows that a saving of approximately 9% on the average can be had for some random functions. A result for some arithmetic functions shows that the minimal solutions of MOD radix SUM, MAX and MIN functions require much fewer implicants than those of the standard sum-of-products expressions.<>
{"title":"A multiple-valued logic synthesis using the Kleenean coefficients","authors":"Y. Hata, K. Yamato","doi":"10.1109/ISMVL.1994.302220","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302220","url":null,"abstract":"This paper presents a new multiple-valued sum-of-products expression structure and shows its minimization to reduce the number of implicants needed in the minimal sum-of-products expressions. The new expression is introduced as the MAX-of-MIN's expression of Kleenean coefficients and one or more literals, where Kleenean coefficients are defined as the logic formulas built from MIN, constants and variables xi and x~i~. It shows a minimization of the above expressions based on binary Quine McCluskey algorithm. The result of computer simulation shows that a saving of approximately 9% on the average can be had for some random functions. A result for some arithmetic functions shows that the minimal solutions of MOD radix SUM, MAX and MIN functions require much fewer implicants than those of the standard sum-of-products expressions.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124569060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302215
Tsutomu Sasao, J. T. Butler
In FPGA design, interconnections are often more expensive than logic. FPGAs using 3-input lookup tables (LUTs) require many logical levels and complex interconnections. On the other hand, FPGAs using 6-input LUTs require fewer interconnections and fewer logical levels. We show a method to represent logic functions by using pseudo-Kronecker diagrams (PKDD's). Experimental results show that 2-valued PKDDs require 29% fewer nodes than BDDs, and 4-valued PKDDs require 23% fewer than QDDs, the 4-valued extension of BDDs. Thus, this method is useful for the design of FPGAs with 6-input LUTs. However, when LUTs have less than 6-inputs, this method is not applicable.<>
{"title":"A design method for look-up table type FPGA by pseudo-Kronecker expansion","authors":"Tsutomu Sasao, J. T. Butler","doi":"10.1109/ISMVL.1994.302215","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302215","url":null,"abstract":"In FPGA design, interconnections are often more expensive than logic. FPGAs using 3-input lookup tables (LUTs) require many logical levels and complex interconnections. On the other hand, FPGAs using 6-input LUTs require fewer interconnections and fewer logical levels. We show a method to represent logic functions by using pseudo-Kronecker diagrams (PKDD's). Experimental results show that 2-valued PKDDs require 29% fewer nodes than BDDs, and 4-valued PKDDs require 23% fewer than QDDs, the 4-valued extension of BDDs. Thus, this method is useful for the design of FPGAs with 6-input LUTs. However, when LUTs have less than 6-inputs, this method is not applicable.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116403926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302181
M. Perkowski, M. Chrzanowska-Jeske
The paper proposes mvTANTs, three-level networks with multiple-valued inputs and binary outputs. These networks are a generalization of binary TANTs (Three level And Not networks with True Inputs). One of possible interpretations of mvTANT is a four-level binary network with input decoders which realize multiple-valued literals. Similar to mvPLAs, mvTANTs have regular structures with predictable timing. Compared with mvPLAs, however, they have at least 25% less input wires to the third-level (NAND) plane and not more outputs from the second-level (AND) plane than the mvPLA. Thus, in many cases they have less gates and connections, and are useful to minimize Boolean functions in cellular FPGAs and other regular structures.<>
{"title":"Multiple-valued-input TANT networks","authors":"M. Perkowski, M. Chrzanowska-Jeske","doi":"10.1109/ISMVL.1994.302181","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302181","url":null,"abstract":"The paper proposes mvTANTs, three-level networks with multiple-valued inputs and binary outputs. These networks are a generalization of binary TANTs (Three level And Not networks with True Inputs). One of possible interpretations of mvTANT is a four-level binary network with input decoders which realize multiple-valued literals. Similar to mvPLAs, mvTANTs have regular structures with predictable timing. Compared with mvPLAs, however, they have at least 25% less input wires to the third-level (NAND) plane and not more outputs from the second-level (AND) plane than the mvPLA. Thus, in many cases they have less gates and connections, and are useful to minimize Boolean functions in cellular FPGAs and other regular structures.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114870939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302218
B. Becker, R. Drechsler
We present a new general data structure for representation of multi-valued input, multi-valued output functions, called function graphs (FG). Ordered FGs are shown to be a canonical form. We investigate read-once FGs and show that type-restricted FGs are also canonical. We use FGs for multi-valued set representation and manipulation. They allow efficient manipulation algorithms for set operations, e.g. union and intersection. An application to genetic algorithms (GAs) is presented in more detail. A population is represented by a multi-rooted FG. It is shown by experimental results that this new representation is very efficient and superior to other data structures for GAs.<>
{"title":"Efficient graph based representation of multi-valued functions with an application to genetic algorithms","authors":"B. Becker, R. Drechsler","doi":"10.1109/ISMVL.1994.302218","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302218","url":null,"abstract":"We present a new general data structure for representation of multi-valued input, multi-valued output functions, called function graphs (FG). Ordered FGs are shown to be a canonical form. We investigate read-once FGs and show that type-restricted FGs are also canonical. We use FGs for multi-valued set representation and manipulation. They allow efficient manipulation algorithms for set operations, e.g. union and intersection. An application to genetic algorithms (GAs) is presented in more detail. A population is represented by a multi-rooted FG. It is shown by experimental results that this new representation is very efficient and superior to other data structures for GAs.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125102131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302219
G. Abdel-Hamid, M. Abd-El-Barr
In this paper, a sub-optimal algorithm for reducing the number of threshold elements required to realize a given binary function is presented. The algorithm uses a matching-count matrix to obtain the input-output pairing that results the maximum total matching count, thus minimizing the number of switching operations required. The concept of output phase assignment is used to extend the approach to handle multiple-valued logic functions. Experimental results are given to illustrate the merits of the proposed algorithms.<>
{"title":"Decomposition-based synthesis of multiple-valued functions for threshold logic network realization","authors":"G. Abdel-Hamid, M. Abd-El-Barr","doi":"10.1109/ISMVL.1994.302219","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302219","url":null,"abstract":"In this paper, a sub-optimal algorithm for reducing the number of threshold elements required to realize a given binary function is presented. The algorithm uses a matching-count matrix to obtain the input-output pairing that results the maximum total matching count, thus minimizing the number of switching operations required. The concept of output phase assignment is used to extend the approach to handle multiple-valued logic functions. Experimental results are given to illustrate the merits of the proposed algorithms.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130410953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302216
R. Stankovic, M. Stankovic, C. Moraga, Tsutomu Sasao
We extend the method for the calculation of Walsh transform of binary switching functions through the binary decision diagrams to the calculation of Reed-Muller-Fourier transform of p-valued through multiple-place decision diagrams functions through multiple-place decision diagrams. The calculation of Reed-Muller coefficients of binary switching functions is involved as a special case for p=2.<>
{"title":"Calculation of Reed-Muller-Fourier coefficients of multiple-valued functions through multiple-place decision diagrams","authors":"R. Stankovic, M. Stankovic, C. Moraga, Tsutomu Sasao","doi":"10.1109/ISMVL.1994.302216","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302216","url":null,"abstract":"We extend the method for the calculation of Walsh transform of binary switching functions through the binary decision diagrams to the calculation of Reed-Muller-Fourier transform of p-valued through multiple-place decision diagrams functions through multiple-place decision diagrams. The calculation of Reed-Muller coefficients of binary switching functions is involved as a special case for p=2.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132225595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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