Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302224
T. Hanyu, A. Mochizuki, M. Kameyama
This paper presents a design of new multiple-valued current-mode MOS integrated circuits based on dual-rail source-coupled logic. This circuit can be efficiently utilized in implementing high-speed arithmetic VLSI systems. The use of dual-rail source-coupled logic makes it possible to reduce an input voltage swing for a threshold detector, so that the switching delay of the threshold detector can be reduced. This property is suitable for implementing high-speed multiple-valued integrated circuits with low supply voltage. It is demonstrated that the delay of the proposed radix-2 signed-digit (SD) adder based on dual-rail source-coupled logic is reduced to 67 percent in comparison with that of the corresponding binary CMOS implementation.<>
{"title":"Multiple-valued current-mode MOS integrated circuits based on dual-rail source-coupled logic","authors":"T. Hanyu, A. Mochizuki, M. Kameyama","doi":"10.1109/ISMVL.1994.302224","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302224","url":null,"abstract":"This paper presents a design of new multiple-valued current-mode MOS integrated circuits based on dual-rail source-coupled logic. This circuit can be efficiently utilized in implementing high-speed arithmetic VLSI systems. The use of dual-rail source-coupled logic makes it possible to reduce an input voltage swing for a threshold detector, so that the switching delay of the threshold detector can be reduced. This property is suitable for implementing high-speed multiple-valued integrated circuits with low supply voltage. It is demonstrated that the delay of the proposed radix-2 signed-digit (SD) adder based on dual-rail source-coupled logic is reduced to 67 percent in comparison with that of the corresponding binary CMOS implementation.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129468270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302202
B. A. Romov
Gives a general completeness criterion for the arity-calibrated product P/sub k/xP/sub m/ of the algebras of all functions of the k-valued and m-valued logics (k,m/spl ges/2). The Galois connection between the lattice of subalgebras P/sub k/xP/sub m/ and the lattice of subalgebras of the double-base invariant relations algebra (with operations of restricted first order calculus) is established. This is used to obtain a Slupecki type criterion for P/sub k/xP/sub m/ and to solve the completeness problem in P/sub k/xP/sub m/ (m/spl ges/2).<>
{"title":"The completeness problem on the product of algebras of finite-valued logic","authors":"B. A. Romov","doi":"10.1109/ISMVL.1994.302202","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302202","url":null,"abstract":"Gives a general completeness criterion for the arity-calibrated product P/sub k/xP/sub m/ of the algebras of all functions of the k-valued and m-valued logics (k,m/spl ges/2). The Galois connection between the lattice of subalgebras P/sub k/xP/sub m/ and the lattice of subalgebras of the double-base invariant relations algebra (with operations of restricted first order calculus) is established. This is used to obtain a Slupecki type criterion for P/sub k/xP/sub m/ and to solve the completeness problem in P/sub k/xP/sub m/ (m/spl ges/2).<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133460666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302189
E. Dubrova, D. Gurov, J. Muzio
The notion of full sensitivity in a multiple-valued logic (MVL) circuit is introduced. A formalization of this notion using a specially defined operator, called mutual exclusion, is given. An expression of full sensitivity in the functional base of J.B. Rosser and A.R. Turquette (1952) is presented. The usefulness of this functional transformation with respect to test generation for MVL circuits is investigated.<>
{"title":"Full sensitivity and test generation for multiple-valued logic circuits","authors":"E. Dubrova, D. Gurov, J. Muzio","doi":"10.1109/ISMVL.1994.302189","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302189","url":null,"abstract":"The notion of full sensitivity in a multiple-valued logic (MVL) circuit is introduced. A formalization of this notion using a specially defined operator, called mutual exclusion, is given. An expression of full sensitivity in the functional base of J.B. Rosser and A.R. Turquette (1952) is presented. The usefulness of this functional transformation with respect to test generation for MVL circuits is investigated.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133528907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302185
G. Denham
E.L. Post's study (1941) shows that, although the lattice of clones in 2-valued logic is countably infinite, there exist only finitely many clones which contain both constants, and only finitely many which contain the negation function (neg). There are, however, uncountably many k-valued clones for all k>2; in fact, I. Agoston, et al. (1983) have shown that there are uncountably many containing all constants. One may also regard the set of constant functions of two-valued logic as an instance of the set of all noninvertible, unary functions over any finite domain. We show here that, for all k, there are indeed only finitely many clones containing all such functions. We also generalize those clones in Post's lattice which contain neg to the clones containing all permutation functions. Once again, it can be shown that there are only finitely many such clones. The latter result also serves to characterize the homogeneous relation algebras of R. Poschel (1979).<>
{"title":"Many-valued generalizations of two finite intervals in Post's lattice","authors":"G. Denham","doi":"10.1109/ISMVL.1994.302185","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302185","url":null,"abstract":"E.L. Post's study (1941) shows that, although the lattice of clones in 2-valued logic is countably infinite, there exist only finitely many clones which contain both constants, and only finitely many which contain the negation function (neg). There are, however, uncountably many k-valued clones for all k>2; in fact, I. Agoston, et al. (1983) have shown that there are uncountably many containing all constants. One may also regard the set of constant functions of two-valued logic as an instance of the set of all noninvertible, unary functions over any finite domain. We show here that, for all k, there are indeed only finitely many clones containing all such functions. We also generalize those clones in Post's lattice which contain neg to the clones containing all permutation functions. Once again, it can be shown that there are only finitely many such clones. The latter result also serves to characterize the homogeneous relation algebras of R. Poschel (1979).<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114977149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302205
J. Demetrovics, C. Reischer, D. Simovici, I. Stojmenovic
This paper discusses some classification and enumeration problems in r-valued set logic, which is the logic of functions mapping n-tuples of subsets into subsets over r values. Boolean functions are convenient choice as building blocks in the design of set logic functions. Weak maximal sets are these containing all Boolean functions. The authors give the number of n-ary functions in each weak maximal set and and some properties of intersections of weak maximal sets in r-valued set logic. These properties are used to classify all three-valued set logic functions according to the weak maximal sets they belong to. They prove that there are 29 such classes of functions and give a unary function representative for each of them. Finally, they find the number of n-ary weak Sheffer functions of three-valued set logic, i.e. functions which are complete under compositions with Boolean functions.<>
{"title":"Enumeration of function and bases of three-valued set logic under compositions with Boolean functions","authors":"J. Demetrovics, C. Reischer, D. Simovici, I. Stojmenovic","doi":"10.1109/ISMVL.1994.302205","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302205","url":null,"abstract":"This paper discusses some classification and enumeration problems in r-valued set logic, which is the logic of functions mapping n-tuples of subsets into subsets over r values. Boolean functions are convenient choice as building blocks in the design of set logic functions. Weak maximal sets are these containing all Boolean functions. The authors give the number of n-ary functions in each weak maximal set and and some properties of intersections of weak maximal sets in r-valued set logic. These properties are used to classify all three-valued set logic functions according to the weak maximal sets they belong to. They prove that there are 29 such classes of functions and give a unary function representative for each of them. Finally, they find the number of n-ary weak Sheffer functions of three-valued set logic, i.e. functions which are complete under compositions with Boolean functions.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128697290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302223
K. Navi, A. Kazeminejad, D. Etiemble
We present the performance of three different multivalued current mode 1-bit adders. These circuits have been simulated with the electrical parameters of a standard 1.2 /spl mu/m CMOS technology. The performance of a binary voltage mode 1-bit adder is also presented. The binary version uses twice more transistors comparing with multivalued ones, but it is two or three times faster. Multivalued versions are more complicated to design and optimize. These results confirm the chip density advantage of multivalued circuits and the speed advantage of binary versions when using CMOS technologies.<>
介绍了三种不同的多值电流模式1位加法器的性能。这些电路采用标准的1.2 /spl μ m CMOS技术的电学参数进行了仿真。文中还介绍了一种二进制电压模式1位加法器的性能。二进制版本使用的晶体管比多值版本多一倍，但速度是多值版本的两到三倍。多值版本的设计和优化更为复杂。这些结果证实了在使用CMOS技术时，多值电路的芯片密度优势和二进制版本的速度优势。
{"title":"Performance of CMOS current mode full adders","authors":"K. Navi, A. Kazeminejad, D. Etiemble","doi":"10.1109/ISMVL.1994.302223","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302223","url":null,"abstract":"We present the performance of three different multivalued current mode 1-bit adders. These circuits have been simulated with the electrical parameters of a standard 1.2 /spl mu/m CMOS technology. The performance of a binary voltage mode 1-bit adder is also presented. The binary version uses twice more transistors comparing with multivalued ones, but it is two or three times faster. Multivalued versions are more complicated to design and optimize. These results confirm the chip density advantage of multivalued circuits and the speed advantage of binary versions when using CMOS technologies.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125468609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302198
Yuki Watanabe, T. Aoki, T. Higuchi
A new computing architecture based on multiwavelength opto-electronic integrated circuits (multiwave OEICs) is proposed to overcome the communication bottleneck in highly parallel systems. In this paper, we present a possible model of multiwave OEICs to evaluate areas of multiwave computing circuits as a function of the number of available wavelength components and other key parameters. Also, the systematic multiplexing scheme of shuffle-network-based parallel processing structures is discussed to analyze the impact of multiwave computing on the design of highly parallel systems. Moreover, we discuss near-future applications of multiwave computing concept.<>
{"title":"Design of multiwave computing circuits based on a model of integrated opto-electronic devices","authors":"Yuki Watanabe, T. Aoki, T. Higuchi","doi":"10.1109/ISMVL.1994.302198","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302198","url":null,"abstract":"A new computing architecture based on multiwavelength opto-electronic integrated circuits (multiwave OEICs) is proposed to overcome the communication bottleneck in highly parallel systems. In this paper, we present a possible model of multiwave OEICs to evaluate areas of multiwave computing circuits as a function of the number of available wavelength components and other key parameters. Also, the systematic multiplexing scheme of shuffle-network-based parallel processing structures is discussed to analyze the impact of multiwave computing on the design of highly parallel systems. Moreover, we discuss near-future applications of multiwave computing concept.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124801356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302192
H. Thiele
We show how the "classical" theory of T-norms and S-norms of fuzzy logic can be generalized to a theory of T-quantifiers and S-quantifiers, respectively. The key idea leading to this generalization is the fact that the (infinite) iteration of the two-valued conjunction and disjunction gives the two-valued all-quantifier and ex-quantifier, respectively. In the framework of fuzzy logic the same holds for min with respect to Inf and for max with respect to Sup. As a T-norm (S-norm) is commutative and associative, we can construct an all-/spl tau/-quantifier (an ex-/spl sigma/-quantifier) from a given T-norm /spl tau/ (S-norm /spl sigma/). These quantifiers are characterized by axioms (T-quantifiers and S-quantifiers). Furthermore we show that the generating procedure is "complete" with respect to arbitrary T-quantifiers (S-quantifiers) and uniquely reversible.<>
{"title":"On T-quantifiers and S-quantifiers","authors":"H. Thiele","doi":"10.1109/ISMVL.1994.302192","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302192","url":null,"abstract":"We show how the \"classical\" theory of T-norms and S-norms of fuzzy logic can be generalized to a theory of T-quantifiers and S-quantifiers, respectively. The key idea leading to this generalization is the fact that the (infinite) iteration of the two-valued conjunction and disjunction gives the two-valued all-quantifier and ex-quantifier, respectively. In the framework of fuzzy logic the same holds for min with respect to Inf and for max with respect to Sup. As a T-norm (S-norm) is commutative and associative, we can construct an all-/spl tau/-quantifier (an ex-/spl sigma/-quantifier) from a given T-norm /spl tau/ (S-norm /spl sigma/). These quantifiers are characterized by axioms (T-quantifiers and S-quantifiers). Furthermore we show that the generating procedure is \"complete\" with respect to arbitrary T-quantifiers (S-quantifiers) and uniquely reversible.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129144144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302200
L. Micheel, H. Hartnagel, W. Anderson, S. Kirchoefer, N. Papanicolaou
Earlier MVL circuits used resonant tunneling devices based on intraband tunneling. Recently device concepts were explored in the AlSb/InAs system based on interband tunneling. Here non-resonant tunneling discharge from the 2DEG is effected into p/sup +/ doped InAs gates, whereas the 2DEG current is controlled with a Schottky gate as in the conventional HEMT. A wide range of physical and functional device features is possible. Linear properties of the proposed tunneling HEMTs are used for signal summation. The authors explore basic ternary half adders and redundant MVL full adders. The interband tunneling also leads to highly effective literal circuits with applications in MVL synthesis and pattern recognition. Vertically integrated tunnel gates are introduced. Recommendations for experiments and further theoretical work conclude this paper.<>
{"title":"Interband-tunneling III-V semiconductor structures for multiple-valued literal and arithmetic functions","authors":"L. Micheel, H. Hartnagel, W. Anderson, S. Kirchoefer, N. Papanicolaou","doi":"10.1109/ISMVL.1994.302200","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302200","url":null,"abstract":"Earlier MVL circuits used resonant tunneling devices based on intraband tunneling. Recently device concepts were explored in the AlSb/InAs system based on interband tunneling. Here non-resonant tunneling discharge from the 2DEG is effected into p/sup +/ doped InAs gates, whereas the 2DEG current is controlled with a Schottky gate as in the conventional HEMT. A wide range of physical and functional device features is possible. Linear properties of the proposed tunneling HEMTs are used for signal summation. The authors explore basic ternary half adders and redundant MVL full adders. The interband tunneling also leads to highly effective literal circuits with applications in MVL synthesis and pattern recognition. Vertically integrated tunnel gates are introduced. Recommendations for experiments and further theoretical work conclude this paper.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117177417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302213
A. Ramesh, Neil V. Murray
Prime implicant/implicate generating algorithms for multiple-valued logics are introduced. Techniques from classical logic not requiring large normal forms or truth tables are adapted to certain "regular" multiple-valued logics. This is accomplished by means of signed formulas, a meta-logic for multiple valued logics; the formulas are normalized in a way analogous to negation normal form. The logic of signed formulas is classical in nature. The presented method is based on path dissolution, a strongly complete inference rule. The generalization of dissolution that accommodates signed formulas is described.<>
{"title":"Computing prime implicants/implicates for regular logics","authors":"A. Ramesh, Neil V. Murray","doi":"10.1109/ISMVL.1994.302213","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302213","url":null,"abstract":"Prime implicant/implicate generating algorithms for multiple-valued logics are introduced. Techniques from classical logic not requiring large normal forms or truth tables are adapted to certain \"regular\" multiple-valued logics. This is accomplished by means of signed formulas, a meta-logic for multiple valued logics; the formulas are normalized in a way analogous to negation normal form. The logic of signed formulas is classical in nature. The presented method is based on path dissolution, a strongly complete inference rule. The generalization of dissolution that accommodates signed formulas is described.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127100721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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