Pub Date : 2023-11-06DOI: 10.24425/ijet.2022.141285
Romaniuk, Ryszard S
— On 2-3 May 2022 ARIES – Accelerator Research and Innovation for European Science and Society held its last annual conference in CERN summarizing 6 year long effort on the smart development of particle accelerator infrastructures in Europe. The whole series of Integrating Activities on accelerator infrastructures started in 2003 with preparations of CARE, then followed by EuCARD, TIARA, EuCARD2 and culminating with ARIES.
{"title":"ARIES Crowns Two Decades of Particle Accelerators Infrastructure Development in Europe","authors":"Romaniuk, Ryszard S","doi":"10.24425/ijet.2022.141285","DOIUrl":"https://doi.org/10.24425/ijet.2022.141285","url":null,"abstract":"— On 2-3 May 2022 ARIES – Accelerator Research and Innovation for European Science and Society held its last annual conference in CERN summarizing 6 year long effort on the smart development of particle accelerator infrastructures in Europe. The whole series of Integrating Activities on accelerator infrastructures started in 2003 with preparations of CARE, then followed by EuCARD, TIARA, EuCARD2 and culminating with ARIES.","PeriodicalId":13922,"journal":{"name":"International Journal of Electronics and Telecommunications","volume":"23 23","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135545541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-06DOI: 10.24425/ijet.2022.143880
—This paper aims to provide a high-level overview of practical approaches to machine-learning respecting the privacy and confidentiality of customer information, which is called Privacy-Preserving Machine Learning . First, the security approaches in offline-learning privacy methods are assessed. Those focused on modern cryptographic methods, such as Homomor-phic Encryption and Secure Multi-Party Computation , as well as on dedicated combined hardware and software platforms like Trusted Execution Environment - Intel ® Software Guard Extensions (Intel ® SGX) . Combining the security approaches with different machine learning architectures leads to our Proof of Concept in which the accuracy and speed of the security solutions will be examined. The next step was exploring and comparing the Open-Source Python -based solutions for PPML . Four solutions were selected from almost 40 separate, state-of-the-art systems: SyMPC , TF-Encrypted , TenSEAL , and Gramine . Three different Neural Network architectures were designed to show different libraries’ capabilities. The POC solves the image classification problem based on the MNIST dataset. As the computational results show, the accuracy of all considered secure approaches is similar. The maximum difference between non-secure and secure flow does not exceed 1.2%. In terms of secure computations, the most effective Privacy-Preserving Machine Learning library is based on Trusted Execution Environment , followed by Secure Multi-Party Computation and Homomorphic Encryption . However, most of those are at least 1000 times slower than the non-secure evaluation. Unfortunately, it is not acceptable for a real-world scenario. Future work could combine different security approaches, explore other new and existing state-of-the-art libraries or implement support for hardware-accelerated secure computation.
{"title":"The High-Level Practical Overview of Open-Source Privacy-Preserving Machine Learning Solutions","authors":"","doi":"10.24425/ijet.2022.143880","DOIUrl":"https://doi.org/10.24425/ijet.2022.143880","url":null,"abstract":"—This paper aims to provide a high-level overview of practical approaches to machine-learning respecting the privacy and confidentiality of customer information, which is called Privacy-Preserving Machine Learning . First, the security approaches in offline-learning privacy methods are assessed. Those focused on modern cryptographic methods, such as Homomor-phic Encryption and Secure Multi-Party Computation , as well as on dedicated combined hardware and software platforms like Trusted Execution Environment - Intel ® Software Guard Extensions (Intel ® SGX) . Combining the security approaches with different machine learning architectures leads to our Proof of Concept in which the accuracy and speed of the security solutions will be examined. The next step was exploring and comparing the Open-Source Python -based solutions for PPML . Four solutions were selected from almost 40 separate, state-of-the-art systems: SyMPC , TF-Encrypted , TenSEAL , and Gramine . Three different Neural Network architectures were designed to show different libraries’ capabilities. The POC solves the image classification problem based on the MNIST dataset. As the computational results show, the accuracy of all considered secure approaches is similar. The maximum difference between non-secure and secure flow does not exceed 1.2%. In terms of secure computations, the most effective Privacy-Preserving Machine Learning library is based on Trusted Execution Environment , followed by Secure Multi-Party Computation and Homomorphic Encryption . However, most of those are at least 1000 times slower than the non-secure evaluation. Unfortunately, it is not acceptable for a real-world scenario. Future work could combine different security approaches, explore other new and existing state-of-the-art libraries or implement support for hardware-accelerated secure computation.","PeriodicalId":13922,"journal":{"name":"International Journal of Electronics and Telecommunications","volume":"294 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135678896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-06DOI: 10.24425/ijet.2022.141263
{"title":"Program for Simulation and Testing of Apply Cryptography of Advance Encryption Standard (AES) Algorithm with Rivest-Shamir-Adleman (RSA) Algorithm for Good Performance","authors":"","doi":"10.24425/ijet.2022.141263","DOIUrl":"https://doi.org/10.24425/ijet.2022.141263","url":null,"abstract":"","PeriodicalId":13922,"journal":{"name":"International Journal of Electronics and Telecommunications","volume":"325 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135679057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-06DOI: 10.24425/ijet.2022.143883
— The Sinara hardware platform is a modular, open-source measurement and control system dedicated to quantum applications that require hard real-time performance. The hardware is controlled and managed by the ARTIQ, open-source software that provides nanosecond timing resolution and sub-microsecond latency. The Sampler is a general-purpose precision ADC sampling unit with programmable gain and configurable interface. It is used in numerous applications like laser frequency and intensity servo. This paper presents the Sampler module construction and obtained characteristics.
{"title":"Sampler – Open-Source Data Acquisition Module for Quantum Physics","authors":"","doi":"10.24425/ijet.2022.143883","DOIUrl":"https://doi.org/10.24425/ijet.2022.143883","url":null,"abstract":"— The Sinara hardware platform is a modular, open-source measurement and control system dedicated to quantum applications that require hard real-time performance. The hardware is controlled and managed by the ARTIQ, open-source software that provides nanosecond timing resolution and sub-microsecond latency. The Sampler is a general-purpose precision ADC sampling unit with programmable gain and configurable interface. It is used in numerous applications like laser frequency and intensity servo. This paper presents the Sampler module construction and obtained characteristics.","PeriodicalId":13922,"journal":{"name":"International Journal of Electronics and Telecommunications","volume":"159 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135679217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-06DOI: 10.24425/ijet.2022.143885
— This paper presents a broadband Switch-Mode Power Amplifier (SMPA) using a Band-Pass Filter (BPF) at the Output Matching Network (OMN). The proposed SMPA integrates a microstrip BPF as an output impedance matching network to significantly reduce the final circuit size. The microstrip lines of the filter simultaneously play the role of filtering and impedance matching. This proposed method reduces the size of the PA and reduces the power dissipation as much as possible. The BPF is placed at the output of the circuit using microstrip lines and the RT Duroid 6006 substrate. This BPF covers a wide bandwidth ranging from 𝟑.𝟎 𝑮𝑯𝒛 𝒕𝒐 𝟒.𝟒 𝑮𝑯𝒛 . Simulation results show 𝟗 – 𝟏𝟒 𝒅𝑩 gain with 𝟒𝟒 – 𝟓𝟔.𝟔 % drain efficiency (𝑫𝑬 %) , and the output power of 𝟑𝟗 – 𝟒𝟏.𝟑 𝒅𝑩𝒎 would be achieved across the frequency band from 𝟑.𝟎 𝑮𝑯𝒛 to 𝟒. 𝟒 𝑮𝑯𝒛 .
{"title":"Modeling and Design of a Highly Efficient Switch-Mode RF/Microwave Power Amplifier Based-on Microstrip Bandpass Filter","authors":"","doi":"10.24425/ijet.2022.143885","DOIUrl":"https://doi.org/10.24425/ijet.2022.143885","url":null,"abstract":"— This paper presents a broadband Switch-Mode Power Amplifier (SMPA) using a Band-Pass Filter (BPF) at the Output Matching Network (OMN). The proposed SMPA integrates a microstrip BPF as an output impedance matching network to significantly reduce the final circuit size. The microstrip lines of the filter simultaneously play the role of filtering and impedance matching. This proposed method reduces the size of the PA and reduces the power dissipation as much as possible. The BPF is placed at the output of the circuit using microstrip lines and the RT Duroid 6006 substrate. This BPF covers a wide bandwidth ranging from 𝟑.𝟎 𝑮𝑯𝒛 𝒕𝒐 𝟒.𝟒 𝑮𝑯𝒛 . Simulation results show 𝟗 – 𝟏𝟒 𝒅𝑩 gain with 𝟒𝟒 – 𝟓𝟔.𝟔 % drain efficiency (𝑫𝑬 %) , and the output power of 𝟑𝟗 – 𝟒𝟏.𝟑 𝒅𝑩𝒎 would be achieved across the frequency band from 𝟑.𝟎 𝑮𝑯𝒛 to 𝟒. 𝟒 𝑮𝑯𝒛 .","PeriodicalId":13922,"journal":{"name":"International Journal of Electronics and Telecommunications","volume":"207 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135679708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-06DOI: 10.24425/ijet.2022.141275
D. S. Shylu Sam, P. Sam Paul, Diana Jeba Jingle, P. Mano Paul, Judith Samuel, J. Reshma, P. Sarah Sudeepa, G. Evangeline
— This work describes a 4-bit Flash ADC with low power consumption. The performance metrics of a Flash ADC depend on the kind of comparator and encoder used. Hence open-loop comparator and mux-based encoder are used to obtain improved performance. Simulation results show that the simulated design consumes 0.265mW of power in 90nm CMOS technology using cadence-virtuoso software. The circuit operates with an operating frequency of 100MHz and a supply voltage of 1V.
{"title":"Design of Low–power 4-bit Flash ADC Using Multiplexer Based Encoder in 90nm CMOS Process","authors":"D. S. Shylu Sam, P. Sam Paul, Diana Jeba Jingle, P. Mano Paul, Judith Samuel, J. Reshma, P. Sarah Sudeepa, G. Evangeline","doi":"10.24425/ijet.2022.141275","DOIUrl":"https://doi.org/10.24425/ijet.2022.141275","url":null,"abstract":"— This work describes a 4-bit Flash ADC with low power consumption. The performance metrics of a Flash ADC depend on the kind of comparator and encoder used. Hence open-loop comparator and mux-based encoder are used to obtain improved performance. Simulation results show that the simulated design consumes 0.265mW of power in 90nm CMOS technology using cadence-virtuoso software. The circuit operates with an operating frequency of 100MHz and a supply voltage of 1V.","PeriodicalId":13922,"journal":{"name":"International Journal of Electronics and Telecommunications","volume":"9 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135584623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-06DOI: 10.24425/ijet.2022.141278
— Outage and Success performances of an amplify-and-forward relay-assisted D2D communication system over a κ - μ shadowed fading wireless link are presented here. Co-channel interference (CCI) is assumed to affect the D2D signals at relay and destination nodes. The system is analyzed with two scenarios, namely, with diversity combining and without diversity combining. Selection combining (SC) based diversity scheme is incorporated at the D2D receiver to combat fading conditions. The expressions for success and outage probabilities are presented by using the characteristic function approach. The expressions are functions of path-loss exponents, wireless link length between relay and D2D source node, wireless link length between the receiver node and relay, distances between interferers and the relay node, CCI distances from various devices of the system, fading channel. The numerical analysis for various scenarios is presented and analyzed.
{"title":"Performance Analysis of Relay-Assisted Device-to-Device Communication","authors":"","doi":"10.24425/ijet.2022.141278","DOIUrl":"https://doi.org/10.24425/ijet.2022.141278","url":null,"abstract":"— Outage and Success performances of an amplify-and-forward relay-assisted D2D communication system over a κ - μ shadowed fading wireless link are presented here. Co-channel interference (CCI) is assumed to affect the D2D signals at relay and destination nodes. The system is analyzed with two scenarios, namely, with diversity combining and without diversity combining. Selection combining (SC) based diversity scheme is incorporated at the D2D receiver to combat fading conditions. The expressions for success and outage probabilities are presented by using the characteristic function approach. The expressions are functions of path-loss exponents, wireless link length between relay and D2D source node, wireless link length between the receiver node and relay, distances between interferers and the relay node, CCI distances from various devices of the system, fading channel. The numerical analysis for various scenarios is presented and analyzed.","PeriodicalId":13922,"journal":{"name":"International Journal of Electronics and Telecommunications","volume":"329 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135679048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-06DOI: 10.24425/ijet.2022.141264
— This paper presents how to design and simulate two different topologies of a bandpass (BP) rectangular waveguide filter using a direct coupled resonator technique operating at 12 GHz. The filters are characterized by a cross coupling (CM) which produces a single attenuation pole at finite frequency used to realize the bandpass response. The filter resonators provide3rd and 4 th order designs with a pseudo-elliptic response using High Frequency Structure Simulator (HFSS) simulator. Transmission zeros are obtained through coupling between the fundamental mode and high mode. The filter structures are validated leading to obtain transmission zeros close to the bandpass. The simulated waveguide filters with a central frequency exhibit an insertion loss of 0.4/0.3dB and a return loss of 20/23dB for the whole bandwidth ranging from 11.85GHz to 12.15GHz that show good electromagnetic responses for the simulated rectangular waveguide filters.
{"title":"Design of a Bandpass Rectangular Waveguide Filter Based on Direct Coupled Technique","authors":"","doi":"10.24425/ijet.2022.141264","DOIUrl":"https://doi.org/10.24425/ijet.2022.141264","url":null,"abstract":"— This paper presents how to design and simulate two different topologies of a bandpass (BP) rectangular waveguide filter using a direct coupled resonator technique operating at 12 GHz. The filters are characterized by a cross coupling (CM) which produces a single attenuation pole at finite frequency used to realize the bandpass response. The filter resonators provide3rd and 4 th order designs with a pseudo-elliptic response using High Frequency Structure Simulator (HFSS) simulator. Transmission zeros are obtained through coupling between the fundamental mode and high mode. The filter structures are validated leading to obtain transmission zeros close to the bandpass. The simulated waveguide filters with a central frequency exhibit an insertion loss of 0.4/0.3dB and a return loss of 20/23dB for the whole bandwidth ranging from 11.85GHz to 12.15GHz that show good electromagnetic responses for the simulated rectangular waveguide filters.","PeriodicalId":13922,"journal":{"name":"International Journal of Electronics and Telecommunications","volume":"154 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135679229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-06DOI: 10.24425/ijet.2022.143887
—This paper proposes a deep neural network (DNN) based method for the purpose of power-ground plane impedance modeling. A composite DNN model, which is a combination of two DNNs is used to predict the Z-parameters of power ground planes from their design parameters. The first DNN predicts the normalized Z-parameters whereas the second DNN predicts the original maximum and minimum values of the non-normalized Z-parameters. This allows the method to retain a high accuracy when predicting responses that have large variations across designs, as is the case with the Z-parameters of the power-ground planes. We use the adaptive sampling algorithm to generate the training and validation samples for the DNNs. The adaptive sampling algorithm starts with only a few samples, then slowly generates more samples in the non-linear regions within the design parameters space. The level of non-linearity of the regions is determined by a surrogate model which is also trained using the generated samples as well. If the surrogate model has poor prediction accuracy in a region, then the adaptive sampling algorithm will generate more samples in that region. A shallow neural network is used as the surrogate model for non-linearity determination of the regions since it is faster to train and update. Once all the samples have been generated, they will be used to train and validate the composite DNN models. Finally, we present two examples, a square-shaped power ground plane and a square-shaped power ground plane with a hollow square at the center to demonstrate the robustness of the DNN composite models.
{"title":"Power-Ground Plane Impedance Modeling Using Deep Neural Networks and an Adaptive Sampling Process","authors":"","doi":"10.24425/ijet.2022.143887","DOIUrl":"https://doi.org/10.24425/ijet.2022.143887","url":null,"abstract":"—This paper proposes a deep neural network (DNN) based method for the purpose of power-ground plane impedance modeling. A composite DNN model, which is a combination of two DNNs is used to predict the Z-parameters of power ground planes from their design parameters. The first DNN predicts the normalized Z-parameters whereas the second DNN predicts the original maximum and minimum values of the non-normalized Z-parameters. This allows the method to retain a high accuracy when predicting responses that have large variations across designs, as is the case with the Z-parameters of the power-ground planes. We use the adaptive sampling algorithm to generate the training and validation samples for the DNNs. The adaptive sampling algorithm starts with only a few samples, then slowly generates more samples in the non-linear regions within the design parameters space. The level of non-linearity of the regions is determined by a surrogate model which is also trained using the generated samples as well. If the surrogate model has poor prediction accuracy in a region, then the adaptive sampling algorithm will generate more samples in that region. A shallow neural network is used as the surrogate model for non-linearity determination of the regions since it is faster to train and update. Once all the samples have been generated, they will be used to train and validate the composite DNN models. Finally, we present two examples, a square-shaped power ground plane and a square-shaped power ground plane with a hollow square at the center to demonstrate the robustness of the DNN composite models.","PeriodicalId":13922,"journal":{"name":"International Journal of Electronics and Telecommunications","volume":"207 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135679707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：