Pub Date : 2020-06-01DOI: 10.23919/MIXDES49814.2020.9155993
M. Kopeć, B. Więcek
A novel methodology of thermal impedance measurement by temperature monitoring out of the heat source in a power transistor is presented. A low-cost Infra-Red (IR) head is used to register evolution of temperature after step-function powering. A dedicated power generator has been developed to synchronize temperature recording with power dissipation in a device. Estimation of temperature in the heat source is performed by 3D FEM modelling of multilayer transistor structure. It allows fitting the measurement and simulation results to achieve the classically-defined thermal impedance in the heat source.
{"title":"Thermal Characterization of Electronic Components Using Single-detector IR Measurement and 3D Heat Transfer Modelling","authors":"M. Kopeć, B. Więcek","doi":"10.23919/MIXDES49814.2020.9155993","DOIUrl":"https://doi.org/10.23919/MIXDES49814.2020.9155993","url":null,"abstract":"A novel methodology of thermal impedance measurement by temperature monitoring out of the heat source in a power transistor is presented. A low-cost Infra-Red (IR) head is used to register evolution of temperature after step-function powering. A dedicated power generator has been developed to synchronize temperature recording with power dissipation in a device. Estimation of temperature in the heat source is performed by 3D FEM modelling of multilayer transistor structure. It allows fitting the measurement and simulation results to achieve the classically-defined thermal impedance in the heat source.","PeriodicalId":145224,"journal":{"name":"2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121516872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.23919/mixdes49814.2020.9155966
{"title":"Analysis and Modelling of ICs and Microsystems","authors":"","doi":"10.23919/mixdes49814.2020.9155966","DOIUrl":"https://doi.org/10.23919/mixdes49814.2020.9155966","url":null,"abstract":"","PeriodicalId":145224,"journal":{"name":"2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121667913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.23919/MIXDES49814.2020.9155569
I. Shatarah, B. Więcek
Continuously excited Raman scattering in optical fibers is proposed for temperature remote sensing in a Distributed Temperature Sensing (DTS) system. Such an approach is suitable for average temperature measurements over the entire optical fiber or in the chosen set points. The system is operating at 1550 nm to achieve long distance temperature applications. This paper proposes the use of sensitive NIR spectrometer instead on WDM splitter. It allows controlling and choosing the appropriate wavelength of the Raman Anti-Stokes and Raman Stokes backscattered radiation. Moreover, two different types of optical fibers were tested in order to verify the DTS system capabilities, and to present the different impact of temperature upon different optical fibers types. The obtained results were satisfying and promising.
{"title":"The Application of NIR Spectrometer for Average Temperature Measurement in Optical Fibers Based on Spontaneous Raman Scattering for DTS Applications","authors":"I. Shatarah, B. Więcek","doi":"10.23919/MIXDES49814.2020.9155569","DOIUrl":"https://doi.org/10.23919/MIXDES49814.2020.9155569","url":null,"abstract":"Continuously excited Raman scattering in optical fibers is proposed for temperature remote sensing in a Distributed Temperature Sensing (DTS) system. Such an approach is suitable for average temperature measurements over the entire optical fiber or in the chosen set points. The system is operating at 1550 nm to achieve long distance temperature applications. This paper proposes the use of sensitive NIR spectrometer instead on WDM splitter. It allows controlling and choosing the appropriate wavelength of the Raman Anti-Stokes and Raman Stokes backscattered radiation. Moreover, two different types of optical fibers were tested in order to verify the DTS system capabilities, and to present the different impact of temperature upon different optical fibers types. The obtained results were satisfying and promising.","PeriodicalId":145224,"journal":{"name":"2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"44 19","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120816788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.23919/MIXDES49814.2020.9155724
A. Romanova, V. Barzdenas
The work presents the design of an area-efficient low-noise high-performance CMOS transimpedance amplifier for optical time-domain reflectometers. The proposed solution is based on a low-noise capacitive feedback structure and shows a gain of 83/80 dBΩ with the bandwidth reaching 1.1 GHz and average input-referred noise current density below $1.8 mathrm{pA}/sqrt{mathrm{Hz}}$ in the presence of a 0.7 pF total input capacitance. The noise-efficient feedback structure allows addressing noise problem of conventional feed-forward or resistive feedback devices with the total power consumption around 21 mW while running at 1.8 V power supply. A more accurate design methodology is proposed based on explicit modeling of the biasing circuits and decoupling capacitor and modifications to the reference design are suggested including circuits for PMOS-based biasing and DC current elimination.
{"title":"A Capacitive Feedback 80 dBΩ 1.1 GHz CMOS Transimpedance Amplifier with Improved Biasing","authors":"A. Romanova, V. Barzdenas","doi":"10.23919/MIXDES49814.2020.9155724","DOIUrl":"https://doi.org/10.23919/MIXDES49814.2020.9155724","url":null,"abstract":"The work presents the design of an area-efficient low-noise high-performance CMOS transimpedance amplifier for optical time-domain reflectometers. The proposed solution is based on a low-noise capacitive feedback structure and shows a gain of 83/80 dBΩ with the bandwidth reaching 1.1 GHz and average input-referred noise current density below $1.8 mathrm{pA}/sqrt{mathrm{Hz}}$ in the presence of a 0.7 pF total input capacitance. The noise-efficient feedback structure allows addressing noise problem of conventional feed-forward or resistive feedback devices with the total power consumption around 21 mW while running at 1.8 V power supply. A more accurate design methodology is proposed based on explicit modeling of the biasing circuits and decoupling capacitor and modifications to the reference design are suggested including circuits for PMOS-based biasing and DC current elimination.","PeriodicalId":145224,"journal":{"name":"2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127642473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/CCGRID.2005.1558522
T. Krishnamurti
For realistic image synthesis, simulating complex environments in all detail can lead to prohibitive rendering costs. In visual analytics, large-scale datasets pose significant challenges for analysis
{"title":"International programme committee","authors":"T. Krishnamurti","doi":"10.1109/CCGRID.2005.1558522","DOIUrl":"https://doi.org/10.1109/CCGRID.2005.1558522","url":null,"abstract":"For realistic image synthesis, simulating complex environments in all detail can lead to prohibitive rendering costs. In visual analytics, large-scale datasets pose significant challenges for analysis","PeriodicalId":145224,"journal":{"name":"2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130429069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.23919/MIXDES49814.2020.9155752
A. Malinowski, S. Mishra
Speed or clock rate of the first microprocessor released to the market in 1971 was 740 kHz. This microprocessor was intended for calculator application. Continuing increase of microprocessor speed and computing power led to explosion of numerous applications. Five decades later microprocessors speed reached 5 GHz and they have enough computing power leading to such wonders as an artificial intelligence, virtual reality and self-driving autonomous cars which were before only in a science fiction domain. However, an increase of a chip speed is very challenging and it comes with high price. The most straightforward chip speed improvement based on transistor physical dimensions scaling eventually ran out of steam. This led to stress (1990s) followed by strain (2000s) techniques development. When this became insufficient new device structure, FinFET, has been introduced into main stream manufacturing in 2011. However, similarly to the previous approaches, increasing computing power of microprocessors based on FinFET is running now out of steam due to difficult technological barriers and integration challenges. Difficulties and challenges outlined in this paper may end era of microprocessor computing power improvement based on classical silicon technology.
{"title":"Challenges in Performance Improvement of Silicon Systems on Chip in Advanced Nanoelectronics Technology Nodes","authors":"A. Malinowski, S. Mishra","doi":"10.23919/MIXDES49814.2020.9155752","DOIUrl":"https://doi.org/10.23919/MIXDES49814.2020.9155752","url":null,"abstract":"Speed or clock rate of the first microprocessor released to the market in 1971 was 740 kHz. This microprocessor was intended for calculator application. Continuing increase of microprocessor speed and computing power led to explosion of numerous applications. Five decades later microprocessors speed reached 5 GHz and they have enough computing power leading to such wonders as an artificial intelligence, virtual reality and self-driving autonomous cars which were before only in a science fiction domain. However, an increase of a chip speed is very challenging and it comes with high price. The most straightforward chip speed improvement based on transistor physical dimensions scaling eventually ran out of steam. This led to stress (1990s) followed by strain (2000s) techniques development. When this became insufficient new device structure, FinFET, has been introduced into main stream manufacturing in 2011. However, similarly to the previous approaches, increasing computing power of microprocessors based on FinFET is running now out of steam due to difficult technological barriers and integration challenges. Difficulties and challenges outlined in this paper may end era of microprocessor computing power improvement based on classical silicon technology.","PeriodicalId":145224,"journal":{"name":"2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132579073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.23919/MIXDES49814.2020.9155632
I. Brzozowski
This paper presents results and conclusions derived from simulations of tens structures of Parallel Prefix Adders considering over a dozen activity scenarios of input vector changes. Based on extended power model of static CMOS gates accurate analysis is done, thanks to the fact, that the model take into consideration changes of input vectors, not only switching activity of signals. Various structures of PG tree have been examined: regular, non-regular, with grey cells only, with both grey and black and with higher valency cells. Obtained results shows that some structures are better for some kind of summed data, but general remarks for adders design can be derived.
{"title":"Comparative Analysis of Power Consumption of Parallel Prefix Adders","authors":"I. Brzozowski","doi":"10.23919/MIXDES49814.2020.9155632","DOIUrl":"https://doi.org/10.23919/MIXDES49814.2020.9155632","url":null,"abstract":"This paper presents results and conclusions derived from simulations of tens structures of Parallel Prefix Adders considering over a dozen activity scenarios of input vector changes. Based on extended power model of static CMOS gates accurate analysis is done, thanks to the fact, that the model take into consideration changes of input vectors, not only switching activity of signals. Various structures of PG tree have been examined: regular, non-regular, with grey cells only, with both grey and black and with higher valency cells. Obtained results shows that some structures are better for some kind of summed data, but general remarks for adders design can be derived.","PeriodicalId":145224,"journal":{"name":"2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131651429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.23919/MIXDES49814.2020.9155841
Sergio Salas Arriarán, C. Valdez, Kalun Lau, M. Amini, M. Kropidłowski, P. Sniatala
The paper describes an implementation of a Brooks-Iyengar algorithm on the Microchip PIC18F4550 platform. The circuit is considered as a testing platform to check the algorithm concept simulated in MATLAB before the final implementation as ASIC IP core. The results confirm the correctness of the proposed approach, which will be used in the final IP Core design.
{"title":"Sensor Fusion Algorithm Implementation on Microchip PIC Microcontroller","authors":"Sergio Salas Arriarán, C. Valdez, Kalun Lau, M. Amini, M. Kropidłowski, P. Sniatala","doi":"10.23919/MIXDES49814.2020.9155841","DOIUrl":"https://doi.org/10.23919/MIXDES49814.2020.9155841","url":null,"abstract":"The paper describes an implementation of a Brooks-Iyengar algorithm on the Microchip PIC18F4550 platform. The circuit is considered as a testing platform to check the algorithm concept simulated in MATLAB before the final implementation as ASIC IP core. The results confirm the correctness of the proposed approach, which will be used in the final IP Core design.","PeriodicalId":145224,"journal":{"name":"2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123808485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.23919/MIXDES49814.2020.9155813
G. Wegrzyn, R. Kleczek, P. Kmon
In this paper we present a comparative analysis of active feedback circuits dedicated to charge sensitive amplifiers (CSA) used in X-ray imaging systems. This work is motivated by the fact there are many papers discussing advantages and disadvantages of using particular CSA feedback but non of them are done in the same process which is very crucial. The presented design, prototype recording channels fabrication employing two the most competing solutions, and their further measurement results may therefore help one in choosing the most suitable feedback for a particular application. The presented circuits are designed in CMOS 40 nm process and are compared in terms of noise contribution, power consumption, area occupation, ability to minimize detectors leakage current, and also CSA stability.
{"title":"Active Feedbacks Comparative Analysis for Charge Sensitive Amplifiers Designed in CMOS 40 nm","authors":"G. Wegrzyn, R. Kleczek, P. Kmon","doi":"10.23919/MIXDES49814.2020.9155813","DOIUrl":"https://doi.org/10.23919/MIXDES49814.2020.9155813","url":null,"abstract":"In this paper we present a comparative analysis of active feedback circuits dedicated to charge sensitive amplifiers (CSA) used in X-ray imaging systems. This work is motivated by the fact there are many papers discussing advantages and disadvantages of using particular CSA feedback but non of them are done in the same process which is very crucial. The presented design, prototype recording channels fabrication employing two the most competing solutions, and their further measurement results may therefore help one in choosing the most suitable feedback for a particular application. The presented circuits are designed in CMOS 40 nm process and are compared in terms of noise contribution, power consumption, area occupation, ability to minimize detectors leakage current, and also CSA stability.","PeriodicalId":145224,"journal":{"name":"2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125461945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.23919/MIXDES49814.2020.9155790
Zbigniew Mudza
Intermediate virtual architecture overlays atop physical FPGA chips provide convenient abstraction level, which can increase productivity in FPGA-targeted application development. Individual reconfigurable modules of the overlay can be reprogrammed independently using partial reconfiguration. Homogeneous reconfigurable modules can be programmed using common configuration data, on condition that appropriate implementation constraints and proper floorplanning of the virtual architecture are provided. This paper presents methodology that can be used to generate relocatable bitstreams for Xilinx 7 series FPGA devices. The methodology is based on using constraints to force Xilinx Vivado Design Suite tools to implement multiple reconfigurable partition in the same way. Partial Reconfiguration Flow is used to implement multiple variants of individually reconfigurable partitions and Isolation Design Flow is used for feed-through prevention.
{"title":"Relocatable Partial Bitstreams For Virtual Overlay Architectures atop Field-Programmable Gate Arrays","authors":"Zbigniew Mudza","doi":"10.23919/MIXDES49814.2020.9155790","DOIUrl":"https://doi.org/10.23919/MIXDES49814.2020.9155790","url":null,"abstract":"Intermediate virtual architecture overlays atop physical FPGA chips provide convenient abstraction level, which can increase productivity in FPGA-targeted application development. Individual reconfigurable modules of the overlay can be reprogrammed independently using partial reconfiguration. Homogeneous reconfigurable modules can be programmed using common configuration data, on condition that appropriate implementation constraints and proper floorplanning of the virtual architecture are provided. This paper presents methodology that can be used to generate relocatable bitstreams for Xilinx 7 series FPGA devices. The methodology is based on using constraints to force Xilinx Vivado Design Suite tools to implement multiple reconfigurable partition in the same way. Partial Reconfiguration Flow is used to implement multiple variants of individually reconfigurable partitions and Isolation Design Flow is used for feed-through prevention.","PeriodicalId":145224,"journal":{"name":"2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130107129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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