Pub Date : 2020-06-01DOI: 10.23919/MIXDES49814.2020.9156070
L. Kohútka, V. Stopjaková
This paper presents a new ASIC design of a coprocessor that performs process scheduling for embedded mixed-criticality real-time systems consisting of processes of various criticality and various real-time attributes. The proposed solution is implementing Robust Earliest Deadline (RED) algorithm and previously developed hardware architectures used for scheduling of real-time processes. Thanks to the on-chip implementation of the scheduler in a form of a coprocessor, the scheduler operations can be completed in two clock cycles regardless of the process amount within the system contains. The proposed scheduler was verified by simulations that applied millions of random inputs. Chip area costs are evaluated by synthesis into an ASIC using 28 nm process by TSMC. Two versions of real-time process schedulers were compared: EDF scheduler designed for hard real-time processes only and the proposed RED scheduler. The RED algorithm handles variations of process execution times better, achieves higher CPU utilization and can be used for scheduling of hard real-time, soft real-time and non-real-time processes combined within one system that is not possible using the other scheduling algorithms.
{"title":"ASIC Architecture and Implementation of RED Scheduler for Mixed-Criticality Real-Time Systems","authors":"L. Kohútka, V. Stopjaková","doi":"10.23919/MIXDES49814.2020.9156070","DOIUrl":"https://doi.org/10.23919/MIXDES49814.2020.9156070","url":null,"abstract":"This paper presents a new ASIC design of a coprocessor that performs process scheduling for embedded mixed-criticality real-time systems consisting of processes of various criticality and various real-time attributes. The proposed solution is implementing Robust Earliest Deadline (RED) algorithm and previously developed hardware architectures used for scheduling of real-time processes. Thanks to the on-chip implementation of the scheduler in a form of a coprocessor, the scheduler operations can be completed in two clock cycles regardless of the process amount within the system contains. The proposed scheduler was verified by simulations that applied millions of random inputs. Chip area costs are evaluated by synthesis into an ASIC using 28 nm process by TSMC. Two versions of real-time process schedulers were compared: EDF scheduler designed for hard real-time processes only and the proposed RED scheduler. The RED algorithm handles variations of process execution times better, achieves higher CPU utilization and can be used for scheduling of hard real-time, soft real-time and non-real-time processes combined within one system that is not possible using the other scheduling algorithms.","PeriodicalId":145224,"journal":{"name":"2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126425868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.23919/MIXDES49814.2020.9155906
Mohammad Keyhanazar, A. Kalami, A. Amini
This paper introduces a new structure of the thermometer to binary decoder utilizing combination of two conventional approach and modify them in a low-power 6-bit flash analog to digital converter (ADC). Considering advantages of each method to form the presented decoder can lead to minimum possible power consumption which is a critical parameter in all converters especially in flash ADCs. Moreover, in the high-resolution flash ADCs, the decoder structure will be simpler compared to conventional ones and decreases the amount of power dissipation as well. Simulation results through HSPICE software level 49 parameters in 0.18μm standard CMOS technology parameters, prove the precise operation and the great improvements. The 6-bit converter achieves sampling rate of 1.5 GS/s, and precision of 5.10 effective number of bits (ENOB). The proposed ADC works with 1.8V power supply and it has the power consumption of 4.57mW and the figure of merit (FOM) is 0.047 pJ/conversion-step. Hence, this architecture would be dedicated to communication transceivers and data acquisition systems where area and energy efficiency are paramount.
{"title":"A New Architecture of Thermometer to Binary Decoder in a Low-Power 6-bit 1.5GS/s Flash ADC","authors":"Mohammad Keyhanazar, A. Kalami, A. Amini","doi":"10.23919/MIXDES49814.2020.9155906","DOIUrl":"https://doi.org/10.23919/MIXDES49814.2020.9155906","url":null,"abstract":"This paper introduces a new structure of the thermometer to binary decoder utilizing combination of two conventional approach and modify them in a low-power 6-bit flash analog to digital converter (ADC). Considering advantages of each method to form the presented decoder can lead to minimum possible power consumption which is a critical parameter in all converters especially in flash ADCs. Moreover, in the high-resolution flash ADCs, the decoder structure will be simpler compared to conventional ones and decreases the amount of power dissipation as well. Simulation results through HSPICE software level 49 parameters in 0.18μm standard CMOS technology parameters, prove the precise operation and the great improvements. The 6-bit converter achieves sampling rate of 1.5 GS/s, and precision of 5.10 effective number of bits (ENOB). The proposed ADC works with 1.8V power supply and it has the power consumption of 4.57mW and the figure of merit (FOM) is 0.047 pJ/conversion-step. Hence, this architecture would be dedicated to communication transceivers and data acquisition systems where area and energy efficiency are paramount.","PeriodicalId":145224,"journal":{"name":"2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"9 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129072277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.23919/MIXDES49814.2020.9155824
K. Górecki, P. Górecki
In this paper usefulness of electric and optical measurement methods to determine reliably values of thermal parameters of the IGBT is analysed. Factors influencing a measuring error of the considered methods are discussed. The results of measurements of the considered parameters obtained with the use of the considered methods for different cooling conditions of the tested transistor are presented and discussed. It is shown, in what operating conditions each measuring method makes it possible to obtain reliable results.
{"title":"Investigations Properties of Selected Methods of Measurements of Thermal Parameters of the IGBT","authors":"K. Górecki, P. Górecki","doi":"10.23919/MIXDES49814.2020.9155824","DOIUrl":"https://doi.org/10.23919/MIXDES49814.2020.9155824","url":null,"abstract":"In this paper usefulness of electric and optical measurement methods to determine reliably values of thermal parameters of the IGBT is analysed. Factors influencing a measuring error of the considered methods are discussed. The results of measurements of the considered parameters obtained with the use of the considered methods for different cooling conditions of the tested transistor are presented and discussed. It is shown, in what operating conditions each measuring method makes it possible to obtain reliable results.","PeriodicalId":145224,"journal":{"name":"2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126818000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.23919/MIXDES49814.2020.9156069
M. Jezewski, R. Czabański, J. Leski, A. Matonia, R. Martínek
CardioTocoGraphic (CTG) monitoring is the primary method of fetal condition assessment. Due to the inter- and intra-observer disagreement between experts when evaluating signals visually, a well established solution supporting the diagnostic decision is automated classification of CTG signals. The goal of this paper is to propose a method of simplifying the fuzzy classifier rule base by combining ε-similar rules, to achieve high quality of CTG signals classification, but with fewer conditional rules. The results of experiments performed using the benchmark CTG database confirm the efficiency of the introduced method.
{"title":"Combining ε-similar Fuzzy Rules for Efficient Classification of Cardiotocographic Signals","authors":"M. Jezewski, R. Czabański, J. Leski, A. Matonia, R. Martínek","doi":"10.23919/MIXDES49814.2020.9156069","DOIUrl":"https://doi.org/10.23919/MIXDES49814.2020.9156069","url":null,"abstract":"CardioTocoGraphic (CTG) monitoring is the primary method of fetal condition assessment. Due to the inter- and intra-observer disagreement between experts when evaluating signals visually, a well established solution supporting the diagnostic decision is automated classification of CTG signals. The goal of this paper is to propose a method of simplifying the fuzzy classifier rule base by combining ε-similar rules, to achieve high quality of CTG signals classification, but with fewer conditional rules. The results of experiments performed using the benchmark CTG database confirm the efficiency of the introduced method.","PeriodicalId":145224,"journal":{"name":"2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"157 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113992278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.23919/mixdes.2017.8004583
{"title":"General Invited Papers","authors":"","doi":"10.23919/mixdes.2017.8004583","DOIUrl":"https://doi.org/10.23919/mixdes.2017.8004583","url":null,"abstract":"","PeriodicalId":145224,"journal":{"name":"2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114831865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/mixdes.2015.7208573
{"title":"Microelectronics Technology and Packaging","authors":"","doi":"10.1109/mixdes.2015.7208573","DOIUrl":"https://doi.org/10.1109/mixdes.2015.7208573","url":null,"abstract":"","PeriodicalId":145224,"journal":{"name":"2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132649064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.23919/mixdes.2018.8436933
{"title":"Thermal Issues in Microelectronics","authors":"","doi":"10.23919/mixdes.2018.8436933","DOIUrl":"https://doi.org/10.23919/mixdes.2018.8436933","url":null,"abstract":"","PeriodicalId":145224,"journal":{"name":"2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127918196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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