Pub Date : 2020-06-01DOI: 10.23919/MIXDES49814.2020.9155992
M. Kucharski, M. Widlok, R. Piesiewicz
This paper presents an 86-97 GHz transmitter (TX) using a wideband voltage-controlled oscillator (VCO) operating in 21.5-26 GHz range and frequency quadrupler (FQ) fabricated in SiGe BiCMOS technology. The VCO implements a self-buffered common-collector Colpitts topology with binary-weighted varactor ladder for low VCO gain ($K_{VCO}$) and wide tuning range. Use of high-Q passive components and low-noise heterojunction bipolar transistors (HBT) results in worst-case phase noise of -92.8 dBc/Hz at 1MHz offset from the carrier. The VCO is loaded by a low-loss transformer that splitts the signal between frequency prescaling and multiplying blocks. The prescaler comprise three divide-by-two circuits (DTC) based on D flip-flops (D-FF) providing adequate feedback signal for an external phase-locked loop (PLL). The multiplying section consists of two cascaded Gilbert-cell frequency doublers driving a W-band power amplifier (PA). The TX achieves 0.2dBm output power at 92GHz and more than -2.8dBm in 86-97 GHz range consuming 60mA from 3.3V supply. The chip occupies 0.755 mm2 silicon area.
{"title":"A W-band SiGe BiCMOS Transmitter Based on K-band Wideband VCO for Radar Applications","authors":"M. Kucharski, M. Widlok, R. Piesiewicz","doi":"10.23919/MIXDES49814.2020.9155992","DOIUrl":"https://doi.org/10.23919/MIXDES49814.2020.9155992","url":null,"abstract":"This paper presents an 86-97 GHz transmitter (TX) using a wideband voltage-controlled oscillator (VCO) operating in 21.5-26 GHz range and frequency quadrupler (FQ) fabricated in SiGe BiCMOS technology. The VCO implements a self-buffered common-collector Colpitts topology with binary-weighted varactor ladder for low VCO gain ($K_{VCO}$) and wide tuning range. Use of high-Q passive components and low-noise heterojunction bipolar transistors (HBT) results in worst-case phase noise of -92.8 dBc/Hz at 1MHz offset from the carrier. The VCO is loaded by a low-loss transformer that splitts the signal between frequency prescaling and multiplying blocks. The prescaler comprise three divide-by-two circuits (DTC) based on D flip-flops (D-FF) providing adequate feedback signal for an external phase-locked loop (PLL). The multiplying section consists of two cascaded Gilbert-cell frequency doublers driving a W-band power amplifier (PA). The TX achieves 0.2dBm output power at 92GHz and more than -2.8dBm in 86-97 GHz range consuming 60mA from 3.3V supply. The chip occupies 0.755 mm2 silicon area.","PeriodicalId":145224,"journal":{"name":"2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128824510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.23919/MIXDES49814.2020.9155739
M. Jankowski, P. Zając, Piotr Amrozik, M. Szermer
In many applications it is crucial to design reliable and efficient analog readout circuits for micro-electromechanical (MEMS) capacitive sensors. In this paper, we describe the switched-capacitor, open-loop, capacitive-sensing readout circuit, which was designed and manufactured in 0.18 μm technology. Non-standard application of a fully differential amplifier structure is also presented. The post-layout simulation results are described to show the proper operation of the circuit. They show that with the proper symmetrical design of the differential signal path the output offset voltage can be kept at acceptable level.
{"title":"CMOS Interface for Capacitive Sensors with Custom Fully-Differential Amplifiers","authors":"M. Jankowski, P. Zając, Piotr Amrozik, M. Szermer","doi":"10.23919/MIXDES49814.2020.9155739","DOIUrl":"https://doi.org/10.23919/MIXDES49814.2020.9155739","url":null,"abstract":"In many applications it is crucial to design reliable and efficient analog readout circuits for micro-electromechanical (MEMS) capacitive sensors. In this paper, we describe the switched-capacitor, open-loop, capacitive-sensing readout circuit, which was designed and manufactured in 0.18 μm technology. Non-standard application of a fully differential amplifier structure is also presented. The post-layout simulation results are described to show the proper operation of the circuit. They show that with the proper symmetrical design of the differential signal path the output offset voltage can be kept at acceptable level.","PeriodicalId":145224,"journal":{"name":"2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132513182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.23919/MIXDES49814.2020.9156023
Lucas Sales de Oliveira Almeida, Alexandre Baratella Lugli, T. Pimenta, Matheus Vinícius Cirino e Silva, João Paulo Carvalho Henriques, Renzo Paranaíba Mesquita
In the context of the 4.0 industry, new technologies have been aggregated to the industries, which has been pushing production levels and through the use of Big Data keeping great control over its products. Connectivity has been the main focus of this new revolution highlighting the Internet of Things and Systems Integration. One pillar of this massive change industries is Augmented and Virtual reality, which shows itself as a promising area for training purposes and error diagnoses. The focus of this paper is to develop a virtual reality system capable of showing a can production company operators the procedure for components exchange in a machine responsible for the extrusion of aluminum cups. For this end an HTC Vive device was employed for the immersion of the operator, the full modeling of the machine was also needed. The methods used to fulfill the project goals are presented as well as the tools used to develop the proposed system.
{"title":"Virtualization of an Aluminum Cans Production Line Using Virtual Reality","authors":"Lucas Sales de Oliveira Almeida, Alexandre Baratella Lugli, T. Pimenta, Matheus Vinícius Cirino e Silva, João Paulo Carvalho Henriques, Renzo Paranaíba Mesquita","doi":"10.23919/MIXDES49814.2020.9156023","DOIUrl":"https://doi.org/10.23919/MIXDES49814.2020.9156023","url":null,"abstract":"In the context of the 4.0 industry, new technologies have been aggregated to the industries, which has been pushing production levels and through the use of Big Data keeping great control over its products. Connectivity has been the main focus of this new revolution highlighting the Internet of Things and Systems Integration. One pillar of this massive change industries is Augmented and Virtual reality, which shows itself as a promising area for training purposes and error diagnoses. The focus of this paper is to develop a virtual reality system capable of showing a can production company operators the procedure for components exchange in a machine responsible for the extrusion of aluminum cups. For this end an HTC Vive device was employed for the immersion of the operator, the full modeling of the machine was also needed. The methods used to fulfill the project goals are presented as well as the tools used to develop the proposed system.","PeriodicalId":145224,"journal":{"name":"2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132458497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.23919/MIXDES49814.2020.9155782
T. Szmuc, W. Szmuc
A rigorous approach to development of embedded systems is proposed in the paper. The concept is based on introduction of formal modeling branch in parallel to the classical V-development method. SysML is used for description of the developed components, and then these artifacts are translated into Colored Petri Nets (CPN) blocks. The correctness of the CPN models is described using temporal logic and finally verified using model checking tools. The proposed concept enables detection of structural errors in early development stages. The paper describes the next steps of research in this area. Translations of remaining SysML diagrams are included, and the modeling-verification chain is described.
{"title":"Rigorous Development of Embedded Systems Supported by Formal Tools","authors":"T. Szmuc, W. Szmuc","doi":"10.23919/MIXDES49814.2020.9155782","DOIUrl":"https://doi.org/10.23919/MIXDES49814.2020.9155782","url":null,"abstract":"A rigorous approach to development of embedded systems is proposed in the paper. The concept is based on introduction of formal modeling branch in parallel to the classical V-development method. SysML is used for description of the developed components, and then these artifacts are translated into Colored Petri Nets (CPN) blocks. The correctness of the CPN models is described using temporal logic and finally verified using model checking tools. The proposed concept enables detection of structural errors in early development stages. The paper describes the next steps of research in this area. Translations of remaining SysML diagrams are included, and the modeling-verification chain is described.","PeriodicalId":145224,"journal":{"name":"2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130041283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.23919/mixdes49814.2020.9155849
{"title":"Testing and Reliability [breaker page]","authors":"","doi":"10.23919/mixdes49814.2020.9155849","DOIUrl":"https://doi.org/10.23919/mixdes49814.2020.9155849","url":null,"abstract":"","PeriodicalId":145224,"journal":{"name":"2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130772878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.23919/mixdes49814.2020.9155723
N. Kakanakov
Test-bed experimental analysis of the client/server applications in embedded systems is presented. The experiments are executed on different embedded platforms and with different packet sizes. The evaluation of client/server application includes measuring the speed of network hardware and protocol stack processing and the OS speed in creating a socket and reading/writing to it. The experiments include UDP and TCP client/server applications. They are made using a software tool for test-bed experiments in experimental network [5]. The paper includes a comparison of the embedded systems based on the received results. It examines the dependency of the communication latency on packet sizes for small packets (1-500 bytes). Using two modes of TCP communication ( single transport stream for multiple transfers and new transport stream for every packet) enables distinguishing the socket creation time from socket access time.
{"title":"Embedded Systems","authors":"N. Kakanakov","doi":"10.23919/mixdes49814.2020.9155723","DOIUrl":"https://doi.org/10.23919/mixdes49814.2020.9155723","url":null,"abstract":"Test-bed experimental analysis of the client/server applications in embedded systems is presented. The experiments are executed on different embedded platforms and with different packet sizes. The evaluation of client/server application includes measuring the speed of network hardware and protocol stack processing and the OS speed in creating a socket and reading/writing to it. The experiments include UDP and TCP client/server applications. They are made using a software tool for test-bed experiments in experimental network [5]. The paper includes a comparison of the embedded systems based on the received results. It examines the dependency of the communication latency on packet sizes for small packets (1-500 bytes). Using two modes of TCP communication ( single transport stream for multiple transfers and new transport stream for every packet) enables distinguishing the socket creation time from socket access time.","PeriodicalId":145224,"journal":{"name":"2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130091991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.23919/MIXDES49814.2020.9155922
R. D. Lorenzo, A. Baschirotto, Albino Pidutti, P. D. Croce
The demand for low-cost integrated circuits for automotive applications is increasing, while their cost must remain low to maintain product competitiveness. In this scenario, to guarantee DC-DC Buck converters high-efficiency and low cost (in terms of external components) increasing switching frequency is mandatory. The main problems are inherent the parasitic inductances and the parasitic capacitance of power MOSFET. This paper deals with the main critical aspects of increasing such switching frequency and show how to replace the external Schottky diode with an integrated structure. The case of a highspeed monolithic integrated circuit to control a load current is here proposed. Proper design allows to achieve switching frequency up to 1MHz with 94.4% efficiency.
{"title":"1MHz Gate Driver in Power Technology for Fast Switching Applications","authors":"R. D. Lorenzo, A. Baschirotto, Albino Pidutti, P. D. Croce","doi":"10.23919/MIXDES49814.2020.9155922","DOIUrl":"https://doi.org/10.23919/MIXDES49814.2020.9155922","url":null,"abstract":"The demand for low-cost integrated circuits for automotive applications is increasing, while their cost must remain low to maintain product competitiveness. In this scenario, to guarantee DC-DC Buck converters high-efficiency and low cost (in terms of external components) increasing switching frequency is mandatory. The main problems are inherent the parasitic inductances and the parasitic capacitance of power MOSFET. This paper deals with the main critical aspects of increasing such switching frequency and show how to replace the external Schottky diode with an integrated structure. The case of a highspeed monolithic integrated circuit to control a load current is here proposed. Proper design allows to achieve switching frequency up to 1MHz with 94.4% efficiency.","PeriodicalId":145224,"journal":{"name":"2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115792506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.23919/MIXDES49814.2020.9155884
E. Karagianni, C. Lessi, C. Vazouras, A. Panagopoulos, G. Deligeorgis, G. Stavrinidis, A. Kostopoulos
Gallium Nitride technology is entering dynamically in the area of manufacturing integrated circuits. In this paper the design of a Low Noise Amplifier is presented. The transistor that is used is a bilateral, conditionally stable transistor and it has been built at the Foundation for Research and Technology Hellas. It is measured in order to get the Scattering parameters and the Noise Figure. The Noise Figure is additionally calculated, together with the noise resistance and the error between the calculated and the measured values is estimated for a single stage amplifier.
{"title":"Noise Resistance Estimation for a GaN JFET Using Small Signal Measurements for an X-band LNA","authors":"E. Karagianni, C. Lessi, C. Vazouras, A. Panagopoulos, G. Deligeorgis, G. Stavrinidis, A. Kostopoulos","doi":"10.23919/MIXDES49814.2020.9155884","DOIUrl":"https://doi.org/10.23919/MIXDES49814.2020.9155884","url":null,"abstract":"Gallium Nitride technology is entering dynamically in the area of manufacturing integrated circuits. In this paper the design of a Low Noise Amplifier is presented. The transistor that is used is a bilateral, conditionally stable transistor and it has been built at the Foundation for Research and Technology Hellas. It is measured in order to get the Scattering parameters and the Noise Figure. The Noise Figure is additionally calculated, together with the noise resistance and the error between the calculated and the measured values is estimated for a single stage amplifier.","PeriodicalId":145224,"journal":{"name":"2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121951724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.23919/MIXDES49814.2020.9155806
T. Szmuc, W. Szmuc
Architecture Analysis and Design Language (AADL) supports consistence modeling and several analyses in designing of real-time systems. Additional features supporting modeling and analysis is proposed in the paper. The concept is based on automatic translation of AADL components into Colored Petri Net (CPN) models. The translated model may be verified using CPN tools, and also checking satisfability of requirements (described using temporal logic) in the model. The proposed extension supports detection of structural errors in early development stages.
{"title":"Consistency Preserving Development of Embedded Systems Using AADL","authors":"T. Szmuc, W. Szmuc","doi":"10.23919/MIXDES49814.2020.9155806","DOIUrl":"https://doi.org/10.23919/MIXDES49814.2020.9155806","url":null,"abstract":"Architecture Analysis and Design Language (AADL) supports consistence modeling and several analyses in designing of real-time systems. Additional features supporting modeling and analysis is proposed in the paper. The concept is based on automatic translation of AADL components into Colored Petri Net (CPN) models. The translated model may be verified using CPN tools, and also checking satisfability of requirements (described using temporal logic) in the model. The proposed extension supports detection of structural errors in early development stages.","PeriodicalId":145224,"journal":{"name":"2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131716640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.23919/MIXDES49814.2020.9155828
Z. Dlugosz, M. Rajewski, M. Banach, T. Talaśka, R. Dlugosz
The paper presents a method of transistor level implementation of a reconfigurable filter for the application in the algorithm responsible for processing air pollution data. The assumption of the proposed solutions is the realization of the algorithm that uses such filters directly in the wireless sensor, along with other components of such devices. Thanks to this, the amount of data exchanged between the sensors and the base station can be reduced. In the proposed filter structure, a special emphasis was placed on reducing the hardware complexity of the filter. The objective is to reduce the chip area of the overall device. The filter features a modular reconfigurable structure, which allows to achieve different filter orders, with almost linear increase in the hardware complexity. Target application of the proposed solution is in wireless sensors networks (WSN) that consist of large numbers of devices distributed, e.g. in dense urban areas in cities.
{"title":"Low Hardware Complexity Filters for On-Chip Algorithm Used in Air Pollution Sensors for Dense Urban Areas in Smart Cities","authors":"Z. Dlugosz, M. Rajewski, M. Banach, T. Talaśka, R. Dlugosz","doi":"10.23919/MIXDES49814.2020.9155828","DOIUrl":"https://doi.org/10.23919/MIXDES49814.2020.9155828","url":null,"abstract":"The paper presents a method of transistor level implementation of a reconfigurable filter for the application in the algorithm responsible for processing air pollution data. The assumption of the proposed solutions is the realization of the algorithm that uses such filters directly in the wireless sensor, along with other components of such devices. Thanks to this, the amount of data exchanged between the sensors and the base station can be reduced. In the proposed filter structure, a special emphasis was placed on reducing the hardware complexity of the filter. The objective is to reduce the chip area of the overall device. The filter features a modular reconfigurable structure, which allows to achieve different filter orders, with almost linear increase in the hardware complexity. Target application of the proposed solution is in wireless sensors networks (WSN) that consist of large numbers of devices distributed, e.g. in dense urban areas in cities.","PeriodicalId":145224,"journal":{"name":"2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130582254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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