Pub Date : 1989-11-01DOI: 10.1109/ARFTG.1989.323962
J. Rautio
A common practice when calibrating an Automated Network Analyzer (ANA) for use with a wafer prober involves measurement of standards (e.g., short, open, load) placed directly under the coplanar waveguide probe tips. In this paper, we show that this placement changes the nature of the probe. Thus,, the " error" two-port, which separates the device under test from the ANA, depends on the particular standard being measured. This inserts an unremovable error into the calibration. An electromagnetic analyses of several coplanar waveguide standards is provided to support this hypothesis. A means of testing when the error is significant, compared to other measurement errors, and a solution to the problem are presented.
{"title":"A Possible Source of Error in On-Wafer Calibration","authors":"J. Rautio","doi":"10.1109/ARFTG.1989.323962","DOIUrl":"https://doi.org/10.1109/ARFTG.1989.323962","url":null,"abstract":"A common practice when calibrating an Automated Network Analyzer (ANA) for use with a wafer prober involves measurement of standards (e.g., short, open, load) placed directly under the coplanar waveguide probe tips. In this paper, we show that this placement changes the nature of the probe. Thus,, the \" error\" two-port, which separates the device under test from the ANA, depends on the particular standard being measured. This inserts an unremovable error into the calibration. An electromagnetic analyses of several coplanar waveguide standards is provided to support this hypothesis. A means of testing when the error is significant, compared to other measurement errors, and a solution to the problem are presented.","PeriodicalId":153615,"journal":{"name":"34th ARFTG Conference Digest","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126951275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-11-01DOI: 10.1109/ARFTG.1989.323959
D. Dawson, M. Salib
map of Figure 1, 41 d i e ou t of a poss ib l e 122 d i e had g r e a t e r than 32 dBm o f output power. and the d i e s i t e s with "zeros" are d i e t h a t were DC bad. The d e f i n i t i o n of DC bad was any d i e t h a t d id not p inchoff . For example, a d i e wi th a shor t ed ga te has high d r a i n cu r ren t t h a t remains "s tuck" h igh as V,, i s ramped from zero t o a lower l i m i t such a s -5V. A device with a ga t e vo id (open ga te ) has a d r a i n cu r ren t t h a t a l s o remains h igh as V,, is ramped more.negat ive. with "zeros" then a r e d i e t h a t are DC bad, and t i m e w a s n o t spent on RF t e s t i n g . A wafer with 35% y i e l d the re fo re only has RF t e s t t i m e spent on 35% of the d i e , and the f a s t e r DC "screening" i s spent on 65% of the d i e . Figure 2 shows the average y i e l d of devices measured over the l a s t two yea r s . I f wafers t h a t made i t t o t es t a r e the b a s i s of y i e l d , t he average y i e l d was 23%; i f the wafers t h a t s t a r t e d processing a r e the b a s i s of y i e l d , the average y i e l d was 16%. The da ta of Figure 2 is from 700 devices t h a t w e r e power t e s t e d , and the l a r g e amount o f da t a shows t h a t power measurements a t wafer level a r e poss ib l e . Wafer maps of output power have been obtained ( see Figure 1). On the wafer
地图的图1中,41 d i e ou t的彼得·ib l e 122 d e比32 g r e t e r o f dBm的输出功率。而带“0”的“d”是“d”，带“0”的“d”是“d”，带“0”的“d”是“DC”。如果它的值是0，它的值是0，它的值是0，它的值是0，它的值是0。例如，一个具有短电压的电压，其高电压为1v，当电压为1v时，它保持“10v”的高电压，它从零上升到低电压1v，即-5V。设备的ga t e vo id(开放ga te) d r任我n铜r t t h t l s o仍然本,V,,是增加更多。negat ive。加上“0”，然后是“0”，然后是“0”，然后是“0”，然后是“0”，然后是“0”，然后是“0”，然后是“0”，然后是“0”。一个晶圆有35%的电流，而另一个晶圆只有35%的电流，而另一个晶圆只有35%的电流，而另一个晶圆只有35%的电流，而另一个晶圆则有65%的电流用于直流“筛选”。图2显示了在过去两年中测量到的设备的平均功耗。如果有一半的人成功了，一半的人成功了，一半的人成功了，一半的人成功了，一半的人成功了，一半的人成功了，23%的人成功了;如果晶圆片在加工过程中所占的比例比在加工过程中所占的比例要高，那么在加工过程中所占的比例平均为16%。图2的数据来自于700个器件到该器件的功率测量值，图2的数据来自于该器件到该器件的功率测量值，图2的数据来自于该器件到该器件的功率测量值，图2的数据来自于该器件到该器件的功率测量值。已获得输出功率的晶圆图(见图1)
{"title":"On-Wafer Power Measurements","authors":"D. Dawson, M. Salib","doi":"10.1109/ARFTG.1989.323959","DOIUrl":"https://doi.org/10.1109/ARFTG.1989.323959","url":null,"abstract":"map of Figure 1, 41 d i e ou t of a poss ib l e 122 d i e had g r e a t e r than 32 dBm o f output power. and the d i e s i t e s with \"zeros\" are d i e t h a t were DC bad. The d e f i n i t i o n of DC bad was any d i e t h a t d id not p inchoff . For example, a d i e wi th a shor t ed ga te has high d r a i n cu r ren t t h a t remains \"s tuck\" h igh as V,, i s ramped from zero t o a lower l i m i t such a s -5V. A device with a ga t e vo id (open ga te ) has a d r a i n cu r ren t t h a t a l s o remains h igh as V,, is ramped more.negat ive. with \"zeros\" then a r e d i e t h a t are DC bad, and t i m e w a s n o t spent on RF t e s t i n g . A wafer with 35% y i e l d the re fo re only has RF t e s t t i m e spent on 35% of the d i e , and the f a s t e r DC \"screening\" i s spent on 65% of the d i e . Figure 2 shows the average y i e l d of devices measured over the l a s t two yea r s . I f wafers t h a t made i t t o t es t a r e the b a s i s of y i e l d , t he average y i e l d was 23%; i f the wafers t h a t s t a r t e d processing a r e the b a s i s of y i e l d , the average y i e l d was 16%. The da ta of Figure 2 is from 700 devices t h a t w e r e power t e s t e d , and the l a r g e amount o f da t a shows t h a t power measurements a t wafer level a r e poss ib l e . Wafer maps of output power have been obtained ( see Figure 1). On the wafer","PeriodicalId":153615,"journal":{"name":"34th ARFTG Conference Digest","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129416657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-11-01DOI: 10.1109/ARFTG.1989.323957
A. Davidson, E. Strid, Keith Jones
Since the Introduction of microwave wafer probing In 1983 the dominant vector network analyzer calibration technique has been the short-open-load-thru (SOLT). The thru-reflect-line (TRL) technique has also been used In certain applications, and both approaches have enabled valuable measurements to be made with relative ease and a high degree of accuracy. Each technique, however, has drawbacks which may hinder accuracy or prevent certain applications. A new method,' line-reflect-match (LRM), circumvents many of these drawbacks, thereby allowing a more accurate and more versatile on-wafer calibration. In addition, LRM is simpler to perform because it requires fewer standards.
{"title":"Achieving greater on-wafer S-parameter accuracy with the LRM calibration technique","authors":"A. Davidson, E. Strid, Keith Jones","doi":"10.1109/ARFTG.1989.323957","DOIUrl":"https://doi.org/10.1109/ARFTG.1989.323957","url":null,"abstract":"Since the Introduction of microwave wafer probing In 1983 the dominant vector network analyzer calibration technique has been the short-open-load-thru (SOLT). The thru-reflect-line (TRL) technique has also been used In certain applications, and both approaches have enabled valuable measurements to be made with relative ease and a high degree of accuracy. Each technique, however, has drawbacks which may hinder accuracy or prevent certain applications. A new method,' line-reflect-match (LRM), circumvents many of these drawbacks, thereby allowing a more accurate and more versatile on-wafer calibration. In addition, LRM is simpler to perform because it requires fewer standards.","PeriodicalId":153615,"journal":{"name":"34th ARFTG Conference Digest","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127080737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-11-01DOI: 10.1109/ARFTG.1989.323964
Eric S. Copeland, Matthew M. Borg, K. Kerwin
This paper describes a cost-effective DC and microwave test system for production screening of discrete and process-monitor GaAs FETs. Topics covered include system hardware, test software and data storage, DC error-correction, RF GaAs FET modeling, RF probe card technology, error-correction for common-mode inductance, and on-wafer calibration.
{"title":"A Cost-Effective Production DC/RF On-Wafer GaAs FET Measurement System","authors":"Eric S. Copeland, Matthew M. Borg, K. Kerwin","doi":"10.1109/ARFTG.1989.323964","DOIUrl":"https://doi.org/10.1109/ARFTG.1989.323964","url":null,"abstract":"This paper describes a cost-effective DC and microwave test system for production screening of discrete and process-monitor GaAs FETs. Topics covered include system hardware, test software and data storage, DC error-correction, RF GaAs FET modeling, RF probe card technology, error-correction for common-mode inductance, and on-wafer calibration.","PeriodicalId":153615,"journal":{"name":"34th ARFTG Conference Digest","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130199066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-11-01DOI: 10.1109/ARFTG.1989.323954
V. Adamian
A new 2-26.5 GHz on wafer noise parameter measurement is presented. A solid state impedance tuner based test set in conjunction with a vector network analyzer (NWA) and a noise figure system (NFS) can determine the noise and S-parameters of the devices.
{"title":"2-26.5 GHZ On-Wafer Noise and S-Parameter Measurements Using a Solid State Tuner","authors":"V. Adamian","doi":"10.1109/ARFTG.1989.323954","DOIUrl":"https://doi.org/10.1109/ARFTG.1989.323954","url":null,"abstract":"A new 2-26.5 GHz on wafer noise parameter measurement is presented. A solid state impedance tuner based test set in conjunction with a vector network analyzer (NWA) and a noise figure system (NFS) can determine the noise and S-parameters of the devices.","PeriodicalId":153615,"journal":{"name":"34th ARFTG Conference Digest","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128686724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-11-01DOI: 10.1109/ARFTG.1989.323958
H. Sequeira, M. Trippe
Besides calculating the usual coefficients of a 3-term (one-port) or 12-term (two-port) error model, the MMAVERIC technique provides 1) a corruption factor, 2) the phase and loss of the transmission line in which the calibration is performed, and 3) the reflection coefficient of one of the terminations used in the procedure. Each of these outputs is a valuable tool for analyzing and minimizing residual calibration errors. The corruption factor is a sensitive measure of the aggregate contributions of all departures from the ideal situation. For example, if one of the calibration standards is a short, we can determine how closely it approaches the ideal magnitude, |Γ|= 1, and phase, argΓ = 180/°. Our experimental evidence has shown that, at 40 GHz, |Γ| for a coplanar short directly contacted by the probe is about 0.7 dB smaller than that for a short seen through a length of coplanar line on the substrate. Thus, lower corruption and residual calibration errors are obtained if the reference plane is defined on the substrate at some distance away from the probe tips. We have corroborated the work of others(4) by modeling the short as a small reactance and shown how further improvements are achieved by separating the substrate from the wafer chuck by a low-dielectric spacer.
{"title":"Improved Accuracy of On-Wafer Measurements Using the MMAVERIC Calibration Technique","authors":"H. Sequeira, M. Trippe","doi":"10.1109/ARFTG.1989.323958","DOIUrl":"https://doi.org/10.1109/ARFTG.1989.323958","url":null,"abstract":"Besides calculating the usual coefficients of a 3-term (one-port) or 12-term (two-port) error model, the MMAVERIC technique provides 1) a corruption factor, 2) the phase and loss of the transmission line in which the calibration is performed, and 3) the reflection coefficient of one of the terminations used in the procedure. Each of these outputs is a valuable tool for analyzing and minimizing residual calibration errors. The corruption factor is a sensitive measure of the aggregate contributions of all departures from the ideal situation. For example, if one of the calibration standards is a short, we can determine how closely it approaches the ideal magnitude, |Γ|= 1, and phase, argΓ = 180/°. Our experimental evidence has shown that, at 40 GHz, |Γ| for a coplanar short directly contacted by the probe is about 0.7 dB smaller than that for a short seen through a length of coplanar line on the substrate. Thus, lower corruption and residual calibration errors are obtained if the reference plane is defined on the substrate at some distance away from the probe tips. We have corroborated the work of others(4) by modeling the short as a small reactance and shown how further improvements are achieved by separating the substrate from the wafer chuck by a low-dielectric spacer.","PeriodicalId":153615,"journal":{"name":"34th ARFTG Conference Digest","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133817037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-11-01DOI: 10.1109/ARFTG.1989.323956
John T. Barr, Michael J. Pervere
This paper discuss the theory and implementation of a generalized set of Vector Network Analyzer (VNA) calibration techniques. In particular, the Thru-Reflect-Match (TRM) (& Line-Reflect-Match - LRM) technique will be developed. This technique uses a throughline, a reflective device and a matched Z0 load. The TRM/LRM technique is closely related to the TRL method popularized by Hewlett-Packard in the HP 8510B but overcomes certain application limitations of TRL. The described theory generalizes calibration methods for a broad range of coaxial, waveguide and other non-coaxial media. Calibrated measurement results from Open-Short-Load-Thru (OSLT), TRL and TRM/LRM will be presented.
{"title":"A Generalized Vector Network Analyzer Calibration Technique","authors":"John T. Barr, Michael J. Pervere","doi":"10.1109/ARFTG.1989.323956","DOIUrl":"https://doi.org/10.1109/ARFTG.1989.323956","url":null,"abstract":"This paper discuss the theory and implementation of a generalized set of Vector Network Analyzer (VNA) calibration techniques. In particular, the Thru-Reflect-Match (TRM) (& Line-Reflect-Match - LRM) technique will be developed. This technique uses a throughline, a reflective device and a matched Z0 load. The TRM/LRM technique is closely related to the TRL method popularized by Hewlett-Packard in the HP 8510B but overcomes certain application limitations of TRL. The described theory generalizes calibration methods for a broad range of coaxial, waveguide and other non-coaxial media. Calibrated measurement results from Open-Short-Load-Thru (OSLT), TRL and TRM/LRM will be presented.","PeriodicalId":153615,"journal":{"name":"34th ARFTG Conference Digest","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124727213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-11-01DOI: 10.1109/ARFTG.1989.323965
D. Glajchen
By integrating GPIB ATE control, database management, production control and personal computer functions into a distributed network of PCs, required resources can be widely shared, at the same time as the nodes are controlling the ATE systems - while databasing and statistical functions are still centralized. Further, computer-aided design and drawing as well as Production Control functions can be integrated into the same system - permitting immediate data sharing between these functions. ATE and software techniques used to achieve run rates in excess of 100 5W power modules per week, in building over 2400 modules to date - for application in a T/R phased array, are described; as is the distributed ATE system architecture used for MMIC-based Ku-Band 1W peak and X-Band 10W peak power module pilot production.
{"title":"An Integrated Approach to High-Volume Production and Automated Testing of Microwave Power Modules, Using Distributed PCS","authors":"D. Glajchen","doi":"10.1109/ARFTG.1989.323965","DOIUrl":"https://doi.org/10.1109/ARFTG.1989.323965","url":null,"abstract":"By integrating GPIB ATE control, database management, production control and personal computer functions into a distributed network of PCs, required resources can be widely shared, at the same time as the nodes are controlling the ATE systems - while databasing and statistical functions are still centralized. Further, computer-aided design and drawing as well as Production Control functions can be integrated into the same system - permitting immediate data sharing between these functions. ATE and software techniques used to achieve run rates in excess of 100 5W power modules per week, in building over 2400 modules to date - for application in a T/R phased array, are described; as is the distributed ATE system architecture used for MMIC-based Ku-Band 1W peak and X-Band 10W peak power module pilot production.","PeriodicalId":153615,"journal":{"name":"34th ARFTG Conference Digest","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121828375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-11-01DOI: 10.1109/ARFTG.1989.323963
L. Dunleavy
A Ka-band on-wafer S-parameter and noise figure measurement system is described. The system includes an automatic network analyzer for S-parameter measurements and a waveguide noise source and receiver for noise figure measurements. A key difficulty in the system calibration is obtaining the excess noise ratio (ENR) provided by the noise source at the MMIC wafer probe interface. This problem is overcome by performing error corrected vector S-parameter measurements of the input transition network, which consists of a waveguide terminal on one end and a probe tip on the other. These S-parameters are then used to obtain noise calibration reference planes at the probe tips. To demonstrate the system, noise figure and gain measurements for three MMIC amplifiers are presented.
{"title":"A Ka-Band On-Wafer S-Parameter and Noise Figure Measurement System","authors":"L. Dunleavy","doi":"10.1109/ARFTG.1989.323963","DOIUrl":"https://doi.org/10.1109/ARFTG.1989.323963","url":null,"abstract":"A Ka-band on-wafer S-parameter and noise figure measurement system is described. The system includes an automatic network analyzer for S-parameter measurements and a waveguide noise source and receiver for noise figure measurements. A key difficulty in the system calibration is obtaining the excess noise ratio (ENR) provided by the noise source at the MMIC wafer probe interface. This problem is overcome by performing error corrected vector S-parameter measurements of the input transition network, which consists of a waveguide terminal on one end and a probe tip on the other. These S-parameters are then used to obtain noise calibration reference planes at the probe tips. To demonstrate the system, noise figure and gain measurements for three MMIC amplifiers are presented.","PeriodicalId":153615,"journal":{"name":"34th ARFTG Conference Digest","volume":"159 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133112517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-11-01DOI: 10.1109/ARFTG.1989.323961
H. Stinehelfer
The TSO calibration of the Automatic Network Analyzer uses shorts, thru and delay lines. This calibration is then used to extract or de-embed the parameters of a measured circuit.
自动网络分析仪的TSO校准使用短线、直通线和延迟线。然后使用该校准提取或去嵌入被测电路的参数。
{"title":"Analysis of Circuit Parameters Using TSD Method","authors":"H. Stinehelfer","doi":"10.1109/ARFTG.1989.323961","DOIUrl":"https://doi.org/10.1109/ARFTG.1989.323961","url":null,"abstract":"The TSO calibration of the Automatic Network Analyzer uses shorts, thru and delay lines. This calibration is then used to extract or de-embed the parameters of a measured circuit.","PeriodicalId":153615,"journal":{"name":"34th ARFTG Conference Digest","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132335923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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