Pub Date : 2006-04-18DOI: 10.1109/DDECS.2006.1649631
L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, M. Bastian
In this paper, we first present an exhaustive study on the influence of resistive-open defects in the pre-charge circuit of SRAMs. We show that these defects may disturb the pre-charge circuit, thus disturbing the read operation. This faulty behavior can be modeled by two types of dynamic faults called un-restored write faults (URWFs) and un-restored read faults (URRFs). For this type of faults, we next propose a new test algorithm called March Pre. The main advantage of March Pre is its complexity, which is twice lower (2.5N) than that of the reference MATS+ algorithm (5N). On the other side, an obvious shortcoming is that it targets only faults in pre-charge circuits. However, with its properties, March Pre makes the test but also the diagnosis easier in SRAM memories sensitive to pre-charge defects
{"title":"March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit","authors":"L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, M. Bastian","doi":"10.1109/DDECS.2006.1649631","DOIUrl":"https://doi.org/10.1109/DDECS.2006.1649631","url":null,"abstract":"In this paper, we first present an exhaustive study on the influence of resistive-open defects in the pre-charge circuit of SRAMs. We show that these defects may disturb the pre-charge circuit, thus disturbing the read operation. This faulty behavior can be modeled by two types of dynamic faults called un-restored write faults (URWFs) and un-restored read faults (URRFs). For this type of faults, we next propose a new test algorithm called March Pre. The main advantage of March Pre is its complexity, which is twice lower (2.5N) than that of the reference MATS+ algorithm (5N). On the other side, an obvious shortcoming is that it targets only faults in pre-charge circuits. However, with its properties, March Pre makes the test but also the diagnosis easier in SRAM memories sensitive to pre-charge defects","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127995952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-18DOI: 10.1109/DDECS.2006.1649633
P. Fiser, H. Kubátová
Extension of a BIST design algorithm is proposed in this paper. The method is based on a synthesis of a combinational block - the decoder, transforming pseudo-random code words into deterministic test patterns pre-computed by an ATPG tool. The column-matching algorithm is used to design the decoder. Using this algorithm, maximum of decoder outputs is tried to be matched with the decoder inputs, yielding the outputs be implemented as wires, thus without any logic. The newly proposed enhancement consists in a major generalization of the method. The ATPG possibility of generating more than one test vectors for one fault is exploited, yielding smaller area overhead. The complexity of the resulting BIST logic reduction is evaluated for some of the ISCAS benchmarks
{"title":"Multiple-Vector Column-Matching BIST Design Method","authors":"P. Fiser, H. Kubátová","doi":"10.1109/DDECS.2006.1649633","DOIUrl":"https://doi.org/10.1109/DDECS.2006.1649633","url":null,"abstract":"Extension of a BIST design algorithm is proposed in this paper. The method is based on a synthesis of a combinational block - the decoder, transforming pseudo-random code words into deterministic test patterns pre-computed by an ATPG tool. The column-matching algorithm is used to design the decoder. Using this algorithm, maximum of decoder outputs is tried to be matched with the decoder inputs, yielding the outputs be implemented as wires, thus without any logic. The newly proposed enhancement consists in a major generalization of the method. The ATPG possibility of generating more than one test vectors for one fault is exploited, yielding smaller area overhead. The complexity of the resulting BIST logic reduction is evaluated for some of the ISCAS benchmarks","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121528769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-18DOI: 10.1109/DDECS.2006.1649572
E. Aho, Jarno Vanne, T. Hämäläinen
Parallel memory modules can be used to increase memory bandwidth and feed a processor with only necessary data. Arbitrary stride access capability with interleaved memories is described in previous research where the skewing scheme is changed at run time according to the currently used stride. This paper presents the improved schemes which are adapted to parallel memories. The proposed novel parallel memory architecture allows conflict free accesses with all the constant strides which has not been possible in prior application specific parallel memories. Moreover, the possible access locations are unrestricted and the data patterns have equal amount of accessed data elements as the number of memory modules. The complexity is evaluated with resource counts
{"title":"Parallel Memory Architecture for Arbitrary Stride Accesses","authors":"E. Aho, Jarno Vanne, T. Hämäläinen","doi":"10.1109/DDECS.2006.1649572","DOIUrl":"https://doi.org/10.1109/DDECS.2006.1649572","url":null,"abstract":"Parallel memory modules can be used to increase memory bandwidth and feed a processor with only necessary data. Arbitrary stride access capability with interleaved memories is described in previous research where the skewing scheme is changed at run time according to the currently used stride. This paper presents the improved schemes which are adapted to parallel memories. The proposed novel parallel memory architecture allows conflict free accesses with all the constant strides which has not been possible in prior application specific parallel memories. Moreover, the possible access locations are unrestricted and the data patterns have equal amount of accessed data elements as the number of memory modules. The complexity is evaluated with resource counts","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117346415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-18DOI: 10.1109/DDECS.2006.1649607
A. Fidalgo, G. Alves, J. Ferreira
Fault injection is frequently used for the verification and validation of the fault tolerant features of microprocessors. This paper proposes the modification of a common on-chip debugging (OCD) infrastructure to add fault injection capabilities and improve performance. The proposed solution imposes a very low logic overhead and provides a flexible and efficient mechanism for the execution of fault injection campaigns, being applicable to different target system architectures
{"title":"A Modified Debugging Infrastructure to Assist Real Time Fault Injection Campaigns","authors":"A. Fidalgo, G. Alves, J. Ferreira","doi":"10.1109/DDECS.2006.1649607","DOIUrl":"https://doi.org/10.1109/DDECS.2006.1649607","url":null,"abstract":"Fault injection is frequently used for the verification and validation of the fault tolerant features of microprocessors. This paper proposes the modification of a common on-chip debugging (OCD) infrastructure to add fault injection capabilities and improve performance. The proposed solution imposes a very low logic overhead and provides a flexible and efficient mechanism for the execution of fault injection campaigns, being applicable to different target system architectures","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115852612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-18DOI: 10.1109/DDECS.2006.1649593
Stefan R. Vock, Ulrich Flogaus, Hans Martin von Staudt
Typical nowadays mixed-signal ICs are approaching 1000 or even more parametric tests. These tests are usually coded in a procedural or a semi-object oriented language. The huge code base of the programs is a significant challenge for maintaining code quality which inherently translates into outgoing quality. The paper presents software metrics of typical mixed-signal power management and audio devices with regard to the number of tests conducted. It is shown that classical ways to handle test programs are error prone and tend to systematically repeat known mistakes. The adoption of selected software engineering methods can avoid such mistakes and improves the productivity of the mixed-signal test generation. Results of a pilot project show significant productivity improvement. Open-source based software is employed to provide the necessary tool support. They establish a potential roadmap to get away from proprietary tester specific tool sets
{"title":"Productivity and code quality improvement of mixed-signal test software by applying software engineering methods","authors":"Stefan R. Vock, Ulrich Flogaus, Hans Martin von Staudt","doi":"10.1109/DDECS.2006.1649593","DOIUrl":"https://doi.org/10.1109/DDECS.2006.1649593","url":null,"abstract":"Typical nowadays mixed-signal ICs are approaching 1000 or even more parametric tests. These tests are usually coded in a procedural or a semi-object oriented language. The huge code base of the programs is a significant challenge for maintaining code quality which inherently translates into outgoing quality. The paper presents software metrics of typical mixed-signal power management and audio devices with regard to the number of tests conducted. It is shown that classical ways to handle test programs are error prone and tend to systematically repeat known mistakes. The adoption of selected software engineering methods can avoid such mistakes and improves the productivity of the mixed-signal test generation. Results of a pilot project show significant productivity improvement. Open-source based software is employed to provide the necessary tool support. They establish a potential roadmap to get away from proprietary tester specific tool sets","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132676482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-18DOI: 10.1109/DDECS.2006.1649628
J. Lomsdalen, R. Jensen, Y. Berg
This paper introduces a multiple valued counter, based on recharged semi floating gate structures. The counter starts at a sampled voltage, and counts from there, using an input clock signal as an input. Depending on the sampled value and the phase of the input clock signal - the counter can count both up and down. The counting steps can be varied adjusting the input clock amplitude, which in combination with different output resetting values allows a set of different counting radixes. Recharged semi floating structures may suffer from an offset at the output due to mismatch in the inverter structures. This counter minimizes this problem with a build in offset cancellation, which is an advantage for non capacitive readouts
{"title":"Multiple Valued Counter","authors":"J. Lomsdalen, R. Jensen, Y. Berg","doi":"10.1109/DDECS.2006.1649628","DOIUrl":"https://doi.org/10.1109/DDECS.2006.1649628","url":null,"abstract":"This paper introduces a multiple valued counter, based on recharged semi floating gate structures. The counter starts at a sampled voltage, and counts from there, using an input clock signal as an input. Depending on the sampled value and the phase of the input clock signal - the counter can count both up and down. The counting steps can be varied adjusting the input clock amplitude, which in combination with different output resetting values allows a set of different counting radixes. Recharged semi floating structures may suffer from an offset at the output due to mismatch in the inverter structures. This counter minimizes this problem with a build in offset cancellation, which is an advantage for non capacitive readouts","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123892993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-18DOI: 10.1109/DDECS.2006.1649601
E. Armengaud
Correct system operation, especially in a safety-critical environment, is all the more important since the consequences in case of failure might be catastrophic. This is particularly true for automotive electronics, which are building complex distributed systems comprising more than 70 electronic control units. In such a context, systematic test operation urgently requires the capability to repeat a given scenario in order (a) to track down the root of a failure (cyclic debugging) or (b) to apply a given - standardized -test pattern for validation or benchmarking. However, deterministic re-execution of a given scenario is difficult to achieve due to the large number of inputs and the concurrent process execution. The focus of our ExTraCT project is set to the communication network due to its central role in distributed systems. More especially, it is the aim of this paper to present a novel approach for the deterministic replay of network bus traffic in case of time-triggered communication protocols such as FlexRay (Mores et al., 2001). This low level replay aims at emulating parts of the system, thus decreasing the test complexity with respect to reproducibility
{"title":"Low Level Bus Traffic Replay for the Test of Time-Triggered Communication Systems","authors":"E. Armengaud","doi":"10.1109/DDECS.2006.1649601","DOIUrl":"https://doi.org/10.1109/DDECS.2006.1649601","url":null,"abstract":"Correct system operation, especially in a safety-critical environment, is all the more important since the consequences in case of failure might be catastrophic. This is particularly true for automotive electronics, which are building complex distributed systems comprising more than 70 electronic control units. In such a context, systematic test operation urgently requires the capability to repeat a given scenario in order (a) to track down the root of a failure (cyclic debugging) or (b) to apply a given - standardized -test pattern for validation or benchmarking. However, deterministic re-execution of a given scenario is difficult to achieve due to the large number of inputs and the concurrent process execution. The focus of our ExTraCT project is set to the communication network due to its central role in distributed systems. More especially, it is the aim of this paper to present a novel approach for the deterministic replay of network bus traffic in case of time-triggered communication protocols such as FlexRay (Mores et al., 2001). This low level replay aims at emulating parts of the system, thus decreasing the test complexity with respect to reproducibility","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128795106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-18DOI: 10.1109/DDECS.2006.1649578
G. Bognár, Gyula Horváth, Z. Szűcs, V. Székely
The paper presents a novel, fully contact-less method for detecting die attach problems of semiconductor devices by measuring the dilatation resulting from thermal expansion. Laser interferometer measuring system was used to measure the thermal dilatation caused by infrared radiation directed onto the measured structure. By using the contact based stylus measurement method the previously got results have been cross-verified
{"title":"Die attach quality testing by fully contact-less measurement method","authors":"G. Bognár, Gyula Horváth, Z. Szűcs, V. Székely","doi":"10.1109/DDECS.2006.1649578","DOIUrl":"https://doi.org/10.1109/DDECS.2006.1649578","url":null,"abstract":"The paper presents a novel, fully contact-less method for detecting die attach problems of semiconductor devices by measuring the dilatation resulting from thermal expansion. Laser interferometer measuring system was used to measure the thermal dilatation caused by infrared radiation directed onto the measured structure. By using the contact based stylus measurement method the previously got results have been cross-verified","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124562436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-18DOI: 10.1109/DDECS.2006.1649580
L. Sekanina, Lukás Starecek, Z. Kotásek
Polymorphic gates exhibit one or more additional functions in addition to the "main" function of the gate. The additional functions can be activated under certain conditions by changing control parameters (such as temperature, Vdd, light etc.) of the circuit. This paper shows a non-trivial polymorphic combinational circuit (5 bit majority/Boolean symmetry) which was designed at the gate level and then simulated using polymorphic NAND/NOR gates controlled by Vdd and some conventional gates at the transistor level. PSpice simulations have shown correct behavior of this circuit
{"title":"Novel Logic Circuits Controlled by Vdd","authors":"L. Sekanina, Lukás Starecek, Z. Kotásek","doi":"10.1109/DDECS.2006.1649580","DOIUrl":"https://doi.org/10.1109/DDECS.2006.1649580","url":null,"abstract":"Polymorphic gates exhibit one or more additional functions in addition to the \"main\" function of the gate. The additional functions can be activated under certain conditions by changing control parameters (such as temperature, Vdd, light etc.) of the circuit. This paper shows a non-trivial polymorphic combinational circuit (5 bit majority/Boolean symmetry) which was designed at the gate level and then simulated using polymorphic NAND/NOR gates controlled by Vdd and some conventional gates at the transistor level. PSpice simulations have shown correct behavior of this circuit","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125938431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-18DOI: 10.1109/DDECS.2006.1649609
H. Kariniemi, J. Nurmi
Large system-on-chip (SoC) circuits contain increasing number of embedded processor cores while their communication infrastructures are implemented with networks-on-chip (NOC). Due to the increasing transistor and wire densities these circuits are more difficult to test, which requires that different self-diagnosis and self-test methods must be mobilized. Self-diagnosis and self-repair methods usable for invalidating at least minor manufacturing defects of the NOCs may also be needed for improving the chip yield. This paper presents a new fault-tolerant NOC with two-dimensional mesh topology for future multi-processor SoCs (MPSoC). The improved fault-tolerance is implemented with fault-diagnosis-and-repair (FDAR) system, which makes the NOC more testable and diagnosable. The FDAR can detect static, dynamic, and transient faults and repairs the faulty switches. Furthermore, it makes it possible also for the local processors to reconfigure their switch nodes to work correctly. After the reconfigurations a novel adaptive routing algorithm named fault-tolerant dimension-order-routing (FTDOR) is able to route packets adaptively in seriously faulty networks. The usage of the FTDOR makes it also possible to use all of the ports of the edge switch nodes for connecting processors to the NOC, which improves the utilization of the NOC's resources
{"title":"Fault-tolerant 2-D Mesh Network-On-Chip for MultiProcessor Systems-on-Chip","authors":"H. Kariniemi, J. Nurmi","doi":"10.1109/DDECS.2006.1649609","DOIUrl":"https://doi.org/10.1109/DDECS.2006.1649609","url":null,"abstract":"Large system-on-chip (SoC) circuits contain increasing number of embedded processor cores while their communication infrastructures are implemented with networks-on-chip (NOC). Due to the increasing transistor and wire densities these circuits are more difficult to test, which requires that different self-diagnosis and self-test methods must be mobilized. Self-diagnosis and self-repair methods usable for invalidating at least minor manufacturing defects of the NOCs may also be needed for improving the chip yield. This paper presents a new fault-tolerant NOC with two-dimensional mesh topology for future multi-processor SoCs (MPSoC). The improved fault-tolerance is implemented with fault-diagnosis-and-repair (FDAR) system, which makes the NOC more testable and diagnosable. The FDAR can detect static, dynamic, and transient faults and repairs the faulty switches. Furthermore, it makes it possible also for the local processors to reconfigure their switch nodes to work correctly. After the reconfigurations a novel adaptive routing algorithm named fault-tolerant dimension-order-routing (FTDOR) is able to route packets adaptively in seriously faulty networks. The usage of the FTDOR makes it also possible to use all of the ports of the edge switch nodes for connecting processors to the NOC, which improves the utilization of the NOC's resources","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130945574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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