Pub Date : 2006-04-18DOI: 10.1109/DDECS.2006.1649582
Guoyan Zhang, R. Farrell
An embedded rectifier-based built-in-test (BIT) detection circuit for the RF integrated circuits is proposed, and is adopted to transform the RF output signal into DC signal. In this BIT circuit, low threshold voltage MOS transistor with positive substrate bias is used to act as diode to further improve the detecting sensitivity. With this BIT circuit, the minimum input testing sensitivity can be improved to -50dBm. Also, this circuit doesn't consume current and has very high operating frequency scalability. As an example 2.4GHz low noise amplifier has been verified by using this BIT detection circuit, and gain and linearity are extracted
{"title":"Embedded Built-In-Test Detection Circuit for Radio Frequency Systems and Circuits","authors":"Guoyan Zhang, R. Farrell","doi":"10.1109/DDECS.2006.1649582","DOIUrl":"https://doi.org/10.1109/DDECS.2006.1649582","url":null,"abstract":"An embedded rectifier-based built-in-test (BIT) detection circuit for the RF integrated circuits is proposed, and is adopted to transform the RF output signal into DC signal. In this BIT circuit, low threshold voltage MOS transistor with positive substrate bias is used to act as diode to further improve the detecting sensitivity. With this BIT circuit, the minimum input testing sensitivity can be improved to -50dBm. Also, this circuit doesn't consume current and has very high operating frequency scalability. As an example 2.4GHz low noise amplifier has been verified by using this BIT detection circuit, and gain and linearity are extracted","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126083728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-18DOI: 10.1109/DDECS.2006.1649621
T. Garbolino, M. Kopec, K. Gucwa, A. Hlawiczka
The paper introduces a novel idea of interconnect fault detection, localization and identification based on test response compaction using a MISR. The above-mentioned operations are made at-speed. The localization is done by means of three long, full diagnostic resolution sequences: Walking 1 (W1), Walking 0 (W0) and a part of Johnson sequence (J). The final fault identification phase exploits information stored in two or three signatures
{"title":"Detection, Localisation and Identification of Interconnection Faults Using MISR Compactor","authors":"T. Garbolino, M. Kopec, K. Gucwa, A. Hlawiczka","doi":"10.1109/DDECS.2006.1649621","DOIUrl":"https://doi.org/10.1109/DDECS.2006.1649621","url":null,"abstract":"The paper introduces a novel idea of interconnect fault detection, localization and identification based on test response compaction using a MISR. The above-mentioned operations are made at-speed. The localization is done by means of three long, full diagnostic resolution sequences: Walking 1 (W1), Walking 0 (W0) and a part of Johnson sequence (J). The final fault identification phase exploits information stored in two or three signatures","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116727196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-18DOI: 10.1109/DDECS.2006.1649565
K. Granhaug, S. Aunet
This paper presents a performance analysis and evaluation of six different 1-bit full adder topologies in deep subthreshold operation. The cells are characterized with respect to delay, power consumption, driving capability, power-delay product (PDP), energy-delay product (EDP) and maximum operating frequency. Both traditional CMOS, a specialized low power cell and minority-3 based full adders are simulated and characterized. PDPs of less than 200 aJ are reported, for FA cells operating at frequencies around 2 MHz, for Vdd=200 mV, dissipating less than 100 nW of average power
{"title":"Six subthreshold full adder cells characterized in 90 nm CMOS technology","authors":"K. Granhaug, S. Aunet","doi":"10.1109/DDECS.2006.1649565","DOIUrl":"https://doi.org/10.1109/DDECS.2006.1649565","url":null,"abstract":"This paper presents a performance analysis and evaluation of six different 1-bit full adder topologies in deep subthreshold operation. The cells are characterized with respect to delay, power consumption, driving capability, power-delay product (PDP), energy-delay product (EDP) and maximum operating frequency. Both traditional CMOS, a specialized low power cell and minority-3 based full adders are simulated and characterized. PDPs of less than 200 aJ are reported, for FA cells operating at frequencies around 2 MHz, for Vdd=200 mV, dissipating less than 100 nW of average power","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117269865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-18DOI: 10.1109/DDECS.2006.1649627
Y. You, Yong-Dae Kim, J. Choi
This paper presents a carry look ahead (CLA) circuitry design based on dynamic circuit aiming at delay reduction in addition of BCD coded decimal numbers. The performance of the proposed dynamic decimal adder is analyzed demonstrating its speed improvement. Timing simulation on the proposed decimal addition circuit employing 0.25 mum CMOS technology yields the worst case delay of 622 ns
本文提出了一种基于动态电路的超前进位(CLA)电路设计，以减少BCD编码十进制数的延迟为目标。对所提出的动态十进制加法器的性能进行了分析，证明了其速度的提高。采用0.25 μ m CMOS技术对所提出的十进制加法电路进行时序仿真，其最坏情况延迟为622 ns
{"title":"Dynamic Decimal Adder Circuit Design by using the Carry Lookahead","authors":"Y. You, Yong-Dae Kim, J. Choi","doi":"10.1109/DDECS.2006.1649627","DOIUrl":"https://doi.org/10.1109/DDECS.2006.1649627","url":null,"abstract":"This paper presents a carry look ahead (CLA) circuitry design based on dynamic circuit aiming at delay reduction in addition of BCD coded decimal numbers. The performance of the proposed dynamic decimal adder is analyzed demonstrating its speed improvement. Timing simulation on the proposed decimal addition circuit employing 0.25 mum CMOS technology yields the worst case delay of 622 ns","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128259566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-18DOI: 10.1109/DDECS.2006.1649595
R. Elbaz, L. Torres, G. Sassatelli, P. Guillemin, M. Bardouillet
This paper describes a novel engine, called PE-ICE (parallelized encryption and integrity checking engine), enabling to guarantee the confidentiality and the integrity of data exchanged between a SoC (system on chip) and its external memory by adding the integrity checking capability to a block encryption algorithm
本文介绍了一种新的并行加密和完整性检查引擎PE-ICE (parallelized encryption and integrity checking engine)，通过在块加密算法中增加完整性检查功能，保证了片上系统(system on chip, SoC)与其外部存储器之间交换数据的保密性和完整性
{"title":"PE-ICE: Parallelized Encryption and Integrity Checking Engine","authors":"R. Elbaz, L. Torres, G. Sassatelli, P. Guillemin, M. Bardouillet","doi":"10.1109/DDECS.2006.1649595","DOIUrl":"https://doi.org/10.1109/DDECS.2006.1649595","url":null,"abstract":"This paper describes a novel engine, called PE-ICE (parallelized encryption and integrity checking engine), enabling to guarantee the confidentiality and the integrity of data exchanged between a SoC (system on chip) and its external memory by adding the integrity checking capability to a block encryption algorithm","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134466294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-18DOI: 10.1109/DDECS.2006.1649630
G. Perlaky, G. Mezösi, I. Zolomy
Distributed sensor networks are a fast developing scenario. Ambient assisted living (AAL) is among those scenarios, with ever-growing importance among developed countries with aging population. The smallest components of these systems are the chip size sensors that have embedded sensing, data processing and transmitting capabilities. A strong need is arising to develop integrated means of powering these sensors. Our paper investigates requirements against chips and powering issues and proposes a sample MOS technology compatible array of solar cells integrated on the same wafer as the integrated circuit. The aim of this design is to help to the development of "pin free" autonomous sensor packages
{"title":"Sensor powering with integrated MOS compatible solar cell array","authors":"G. Perlaky, G. Mezösi, I. Zolomy","doi":"10.1109/DDECS.2006.1649630","DOIUrl":"https://doi.org/10.1109/DDECS.2006.1649630","url":null,"abstract":"Distributed sensor networks are a fast developing scenario. Ambient assisted living (AAL) is among those scenarios, with ever-growing importance among developed countries with aging population. The smallest components of these systems are the chip size sensors that have embedded sensing, data processing and transmitting capabilities. A strong need is arising to develop integrated means of powering these sensors. Our paper investigates requirements against chips and powering issues and proposes a sample MOS technology compatible array of solar cells integrated on the same wafer as the integrated circuit. The aim of this design is to help to the development of \"pin free\" autonomous sensor packages","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114226846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-18DOI: 10.1109/DDECS.2006.1649600
P. Dziurzański, W. Bielecki, Konrad Trifunovic, M. Kleszczonek
In this paper, we describe a system for transforming a code given in ANSI C into an equivalent SystemC description. In order to synthesize parallel C codes into hardware, we applied the directives of OpenMP, a de-facto standard that specifies portable implementations of shared memory parallel programs. The proposed design flow utilizing this system is outlined and some implementation details are provided
{"title":"A system for transforming an ANSI C code with OpenMP directives into a SystemC description","authors":"P. Dziurzański, W. Bielecki, Konrad Trifunovic, M. Kleszczonek","doi":"10.1109/DDECS.2006.1649600","DOIUrl":"https://doi.org/10.1109/DDECS.2006.1649600","url":null,"abstract":"In this paper, we describe a system for transforming a code given in ANSI C into an equivalent SystemC description. In order to synthesize parallel C codes into hardware, we applied the directives of OpenMP, a de-facto standard that specifies portable implementations of shared memory parallel programs. The proposed design flow utilizing this system is outlined and some implementation details are provided","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122094838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-18DOI: 10.1109/DDECS.2006.1649622
P. Bernardi, M. Grosso
We present a survey on the academic and industrial structured ASIC practices, especially focusing on the test strategies currently in use. Then, we compare two possible test generation flows, underlining the most critical aspects introduced by the adoption of the structured ASIC methodology
{"title":"Test Considerations about the Structured ASIC Paradigm","authors":"P. Bernardi, M. Grosso","doi":"10.1109/DDECS.2006.1649622","DOIUrl":"https://doi.org/10.1109/DDECS.2006.1649622","url":null,"abstract":"We present a survey on the academic and industrial structured ASIC practices, especially focusing on the test strategies currently in use. Then, we compare two possible test generation flows, underlining the most critical aspects introduced by the adoption of the structured ASIC methodology","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126335523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-18DOI: 10.1109/DDECS.2006.1649573
G. Pastuszak
Hardware accelerators for H.264/AVC using arithmetic coding require special approaches to achieve high throughputs. This paper proposes an efficient architecture for the context formatter that is a part of the H.264/AVC binary encoder. Five versions of the architecture are developed to match different throughputs. The implementation results show that the proposed versions of the context formatter match the performance of corresponding arithmetic coders
{"title":"Architecture Design for the Context Formatter in the H.264/AVC Encoder","authors":"G. Pastuszak","doi":"10.1109/DDECS.2006.1649573","DOIUrl":"https://doi.org/10.1109/DDECS.2006.1649573","url":null,"abstract":"Hardware accelerators for H.264/AVC using arithmetic coding require special approaches to achieve high throughputs. This paper proposes an efficient architecture for the context formatter that is a part of the H.264/AVC binary encoder. Five versions of the architecture are developed to match different throughputs. The implementation results show that the proposed versions of the context formatter match the performance of corresponding arithmetic coders","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131748908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-18DOI: 10.1109/DDECS.2006.1649575
V. V. Belkin, S. Sharshunov
This paper presents a method for functional test generation, which aims self-test of RISC processors and processor cores. The method allows developing compact and quite effective software based tests if only the instruction set architecture (ISA) or ISA together with some micro architecture features are known. We have successfully applied this methodology to test a RISC processor core
{"title":"ISA Based Functional Test Generation with Application to Self-Test of RISC Processors","authors":"V. V. Belkin, S. Sharshunov","doi":"10.1109/DDECS.2006.1649575","DOIUrl":"https://doi.org/10.1109/DDECS.2006.1649575","url":null,"abstract":"This paper presents a method for functional test generation, which aims self-test of RISC processors and processor cores. The method allows developing compact and quite effective software based tests if only the instruction set architecture (ISA) or ISA together with some micro architecture features are known. We have successfully applied this methodology to test a RISC processor core","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132129203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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