Pub Date : 1991-06-12DOI: 10.1109/UGIM.1991.148143
M. Saleh, M. El-Nokali
A DC model for AlGaAs-GaAs high electron mobility transistor (HEMT) is proposed. The model considers the parasitic parallel conduction in AlGaAs, which becomes important for large gate voltages, together with other important effects, such as field-dependent mobility, channel length modulation, maximum concentration of the two-dimensional electron gas, and series resistances. The theoretical predictions of the model are compared with the experimental data and are found to be in good agreement over a wide range of bias conditions.<>
{"title":"A DC model for the HEMT including the effect of parasitic conduction","authors":"M. Saleh, M. El-Nokali","doi":"10.1109/UGIM.1991.148143","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148143","url":null,"abstract":"A DC model for AlGaAs-GaAs high electron mobility transistor (HEMT) is proposed. The model considers the parasitic parallel conduction in AlGaAs, which becomes important for large gate voltages, together with other important effects, such as field-dependent mobility, channel length modulation, maximum concentration of the two-dimensional electron gas, and series resistances. The theoretical predictions of the model are compared with the experimental data and are found to be in good agreement over a wide range of bias conditions.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114488803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-06-12DOI: 10.1109/UGIM.1991.148140
W.R. Einsenstadt, S. Potluri, K.J. Rambo, R. Fox
A small-scale CMOS-based radiographic X-ray image sensor array has been developed for nondestructive test and medical imaging. The authors present an analysis of tradeoffs between yield and area of a scaled up large-area X-ray sensor design. The X-ray sensor array can tolerate a low level of faults in the individual pixel cells and these faults can be corrected by imaging software. However, global signal line faults cause X-ray sensor failures. This work models X-ray sensor yield in a 12-layer analog CMOS process for three possible overall defect densities, 1.5 defects/cm, 1.0 defects/cm, and 0.75 defects/cm. It is shown that the X-ray sensor is more manufacturable than a charge coupled device (CCD) array of the same area.<>
{"title":"Yield analysis for a large-area analog X-ray sensor array","authors":"W.R. Einsenstadt, S. Potluri, K.J. Rambo, R. Fox","doi":"10.1109/UGIM.1991.148140","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148140","url":null,"abstract":"A small-scale CMOS-based radiographic X-ray image sensor array has been developed for nondestructive test and medical imaging. The authors present an analysis of tradeoffs between yield and area of a scaled up large-area X-ray sensor design. The X-ray sensor array can tolerate a low level of faults in the individual pixel cells and these faults can be corrected by imaging software. However, global signal line faults cause X-ray sensor failures. This work models X-ray sensor yield in a 12-layer analog CMOS process for three possible overall defect densities, 1.5 defects/cm, 1.0 defects/cm, and 0.75 defects/cm. It is shown that the X-ray sensor is more manufacturable than a charge coupled device (CCD) array of the same area.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127013932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-06-12DOI: 10.1109/UGIM.1991.148135
F. Rotella, T. Sanders
The authors address the methodology developed for the Florida SEMATECH Center of Excellence (FSCOE) for performing statistical simulations of integrated circuit processes. This methodology involves doing a series of statistical simulations at the process, device, and circuit design levels. Various techniques to improve the amount of time it takes to obtain results from statistical simulations of processes using Suprem-IV are described. Methods the design engineer can use, rather than means of improving the models in the simulator are considered. The key to this methodology is that multiple simulations are performed in order to obtained the statistical results to adequately model the effect of the variation in the fab. Five possible techniques are outlined that reduce the simulation time and eliminate the need to buy expensive computer equipment or use less accurate simulation models.<>
{"title":"Techniques for optimizing statistical simulations (IC processes)","authors":"F. Rotella, T. Sanders","doi":"10.1109/UGIM.1991.148135","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148135","url":null,"abstract":"The authors address the methodology developed for the Florida SEMATECH Center of Excellence (FSCOE) for performing statistical simulations of integrated circuit processes. This methodology involves doing a series of statistical simulations at the process, device, and circuit design levels. Various techniques to improve the amount of time it takes to obtain results from statistical simulations of processes using Suprem-IV are described. Methods the design engineer can use, rather than means of improving the models in the simulator are considered. The key to this methodology is that multiple simulations are performed in order to obtained the statistical results to adequately model the effect of the variation in the fab. Five possible techniques are outlined that reduce the simulation time and eliminate the need to buy expensive computer equipment or use less accurate simulation models.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123098894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-06-12DOI: 10.1109/UGIM.1991.148147
J. Simone, M. Cases
The authors describe a custom logic-circuit design methodology for CMOS circuit technologies where design time and cost are drastically reduced by efficiently using computer-aided design tools. Also described is a hierarchical chip-design methodology where the design is logically partitioned into self-contained timetable design units.<>
{"title":"A structured custom logic-design methodology","authors":"J. Simone, M. Cases","doi":"10.1109/UGIM.1991.148147","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148147","url":null,"abstract":"The authors describe a custom logic-circuit design methodology for CMOS circuit technologies where design time and cost are drastically reduced by efficiently using computer-aided design tools. Also described is a hierarchical chip-design methodology where the design is logically partitioned into self-contained timetable design units.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123759443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-06-12DOI: 10.1109/UGIM.1991.148146
S. Vemuru, E. Smith
A variable taper (VT) approach is proposed for the design of CMOS buffers. The minimum propagation delay obtained by using a VT buffer is approximately 12% higher than the minimum propagation delays obtained by using a conventional fixed taper (FT) approach. A modification to the initial stages of a VT buffer reduces this difference to within 2% of a FT buffer. For buffer designs with similar propagation delays, a VT buffer design usually takes significantly less silicon area and dissipates less power.<>
{"title":"Variable taper CMOS buffer design","authors":"S. Vemuru, E. Smith","doi":"10.1109/UGIM.1991.148146","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148146","url":null,"abstract":"A variable taper (VT) approach is proposed for the design of CMOS buffers. The minimum propagation delay obtained by using a VT buffer is approximately 12% higher than the minimum propagation delays obtained by using a conventional fixed taper (FT) approach. A modification to the initial stages of a VT buffer reduces this difference to within 2% of a FT buffer. For buffer designs with similar propagation delays, a VT buffer design usually takes significantly less silicon area and dissipates less power.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132387242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-06-12DOI: 10.1109/UGIM.1991.148124
J. E. Varrientos, A. Rys
An outline for the instruction of VLSI microprocessor design is given. Considerable preplanning and complexity reduction by use of hierarchy is proposed to simplify the design procedure and reduce or eliminate design iterations late in the design. The microprocessor designed is a modified version of a simple-instruction accumulator machine designed for teaching software and hardware concepts. The design beings with the construction of standard cell libraries using the CAD tools VIVID and MAGIC. A design in VIVID is supported to verify circuit functionality, and a design in MAGIC is supported for final layout. The design continues with considerations for arithmetic-logic-unit (ALU) design, clocking schemes, bus-pre-charging, floorplanning, system timing, and interfacing to memory.<>
{"title":"VLSI microprocessor design for classroom instruction","authors":"J. E. Varrientos, A. Rys","doi":"10.1109/UGIM.1991.148124","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148124","url":null,"abstract":"An outline for the instruction of VLSI microprocessor design is given. Considerable preplanning and complexity reduction by use of hierarchy is proposed to simplify the design procedure and reduce or eliminate design iterations late in the design. The microprocessor designed is a modified version of a simple-instruction accumulator machine designed for teaching software and hardware concepts. The design beings with the construction of standard cell libraries using the CAD tools VIVID and MAGIC. A design in VIVID is supported to verify circuit functionality, and a design in MAGIC is supported for final layout. The design continues with considerations for arithmetic-logic-unit (ALU) design, clocking schemes, bus-pre-charging, floorplanning, system timing, and interfacing to memory.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128793009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-06-12DOI: 10.1109/UGIM.1991.148132
F. Evans, J. Wall, B. Hancock, P. Brusius, M. Mitchell
An experiment was performed on 1.25 mu m radiation-hard, very high-speed integrated circuit (VHSIC)-level 2 K*8 static random access memory (SRAM) devices with the objective of investigating the relationship between the SRAM reliability and the die yield at wafer probe. The SRAMs were product-level devices that were included as part of a test chip, the yield/circuit/reliability analysis tool (YCRAT). There were 54 YCRAT sites on each four-inch wafer. After all wafer-level tests, 423 SRAMs were packaged in 24-pin flatpacks and subjected to a 1000 h, 125 degrees C life test. 183 of the parts were from wafers judged to be bad, i.e. for some reason the SRAM dice or test structures did not pass wafer-level screening, and 240 parts were from wafers judged to be good, i.e. they passed wafer-level screening. The results of the test showed that wafers exhibiting metal/dielectric problems had poor yields through screening and somewhat worse reliability.<>
{"title":"Reliability in VHSIC-level 1.25 mu m radiation-hard CMOS IC devices","authors":"F. Evans, J. Wall, B. Hancock, P. Brusius, M. Mitchell","doi":"10.1109/UGIM.1991.148132","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148132","url":null,"abstract":"An experiment was performed on 1.25 mu m radiation-hard, very high-speed integrated circuit (VHSIC)-level 2 K*8 static random access memory (SRAM) devices with the objective of investigating the relationship between the SRAM reliability and the die yield at wafer probe. The SRAMs were product-level devices that were included as part of a test chip, the yield/circuit/reliability analysis tool (YCRAT). There were 54 YCRAT sites on each four-inch wafer. After all wafer-level tests, 423 SRAMs were packaged in 24-pin flatpacks and subjected to a 1000 h, 125 degrees C life test. 183 of the parts were from wafers judged to be bad, i.e. for some reason the SRAM dice or test structures did not pass wafer-level screening, and 240 parts were from wafers judged to be good, i.e. they passed wafer-level screening. The results of the test showed that wafers exhibiting metal/dielectric problems had poor yields through screening and somewhat worse reliability.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132336700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-06-12DOI: 10.1109/UGIM.1991.148142
M. Guvench, S. Irving, M. Robinson, D. Desbiens
Use of two-dimensional process and device simulators in predicting the latch-up immunity of a BiCMOS process is described. Recent advances have resulted in the availability of a number of simulation tools such as PISCES in the device simulation area and others such as SUPRA and SUPREM-2, -3, and -4 in the process simulation area. SUPRA was used for process modeling, and PISCES-2B for device simulations. It is shown that despite SUPRA's limitations and restrictions in the sequential choice of process steps, with tricks and some help from one-dimensional SUPREM-3 results, satisfactory 2-D profiles can be obtained. Therefore, PISCES-2B receives a two-dimensional device structure with no manual interference. It is shown that the models developed yield not only the MOSFET characteristics but also the parasitic transistors gains. Results obtained from the simulation of the device under latch-up test conditions help the engineer to design latch-up-free CMOS and BiCMOS processes.<>
{"title":"Concurrent use of two-dimensional process and device simulators in the development of a latch-up free BiCMOS process","authors":"M. Guvench, S. Irving, M. Robinson, D. Desbiens","doi":"10.1109/UGIM.1991.148142","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148142","url":null,"abstract":"Use of two-dimensional process and device simulators in predicting the latch-up immunity of a BiCMOS process is described. Recent advances have resulted in the availability of a number of simulation tools such as PISCES in the device simulation area and others such as SUPRA and SUPREM-2, -3, and -4 in the process simulation area. SUPRA was used for process modeling, and PISCES-2B for device simulations. It is shown that despite SUPRA's limitations and restrictions in the sequential choice of process steps, with tricks and some help from one-dimensional SUPREM-3 results, satisfactory 2-D profiles can be obtained. Therefore, PISCES-2B receives a two-dimensional device structure with no manual interference. It is shown that the models developed yield not only the MOSFET characteristics but also the parasitic transistors gains. Results obtained from the simulation of the device under latch-up test conditions help the engineer to design latch-up-free CMOS and BiCMOS processes.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134251447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-06-12DOI: 10.1109/UGIM.1991.148156
R. Bracken, M. Salatino, C. Adkins, B. Kraemer
Harris Corporation has undertaken a multichip module (MCM) project that will develop a four-channel digital RF receiver as a very dense, lightweight system. A single-channel system has been implemented with its supporting logic chips in a 6"*7" PCB (printed circuit board). The four-channel module was fabricated on a 2.5"*2.5" substrate that will be assembled in a 2.75"*2.75" metal package with 200 leads. The module contains a total of 41 chips, twelve being VLSI. To test currently available substrate technologies, the substrate was fabricated in two different varieties: a low-temperature cofired ceramic, the DuPont Green Tape, and a high-density copper/polyimide. Bonding to the top level of the system was done by both TAB (tape automated bonding) and gold wire bonding. An important feature of this MCM is that it exploits design-for-testability concepts which allow defective die or interconnects to be easily identified, thus facilitating module rework. This approach does not require boundary scan to be incorporated into chip design, or test registers to be added to the module.<>
{"title":"Multi-chip modules: a comparative study-phase I: system design and substrate selection","authors":"R. Bracken, M. Salatino, C. Adkins, B. Kraemer","doi":"10.1109/UGIM.1991.148156","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148156","url":null,"abstract":"Harris Corporation has undertaken a multichip module (MCM) project that will develop a four-channel digital RF receiver as a very dense, lightweight system. A single-channel system has been implemented with its supporting logic chips in a 6\"*7\" PCB (printed circuit board). The four-channel module was fabricated on a 2.5\"*2.5\" substrate that will be assembled in a 2.75\"*2.75\" metal package with 200 leads. The module contains a total of 41 chips, twelve being VLSI. To test currently available substrate technologies, the substrate was fabricated in two different varieties: a low-temperature cofired ceramic, the DuPont Green Tape, and a high-density copper/polyimide. Bonding to the top level of the system was done by both TAB (tape automated bonding) and gold wire bonding. An important feature of this MCM is that it exploits design-for-testability concepts which allow defective die or interconnects to be easily identified, thus facilitating module rework. This approach does not require boundary scan to be incorporated into chip design, or test registers to be added to the module.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134346460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-06-12DOI: 10.1109/UGIM.1991.148111
R. Lucic
The Semiconductor Research Corporation (SRC) is a cooperative effort of US and Canadian companies to strengthen and maintain the vitality and competitive ability of the semiconductor industry. In 1990, the SRC funded over 81 research contracts ranging in size from $30 thousand to $1.5 million per year. These contracts define 290 separate research tasks and involve 69 different research organizations, most of which are universities. The researchers themselves are the most important element of the program. At present there are 337 faculty members and over 600 students participating.<>
{"title":"Cooperative research and technology transfer","authors":"R. Lucic","doi":"10.1109/UGIM.1991.148111","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148111","url":null,"abstract":"The Semiconductor Research Corporation (SRC) is a cooperative effort of US and Canadian companies to strengthen and maintain the vitality and competitive ability of the semiconductor industry. In 1990, the SRC funded over 81 research contracts ranging in size from $30 thousand to $1.5 million per year. These contracts define 290 separate research tasks and involve 69 different research organizations, most of which are universities. The researchers themselves are the most important element of the program. At present there are 337 faculty members and over 600 students participating.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"43 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114114008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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