Pub Date : 2000-02-27DOI: 10.1109/SSMSD.2000.836456
Hee-Tae Ahn, D. Allstot
A fully-differential four-stage distributed amplifier (DA) with 5.5 dB gain and 8.5 GHz bandwidth has been integrated in 1.3 mm/spl times/2.2 mm in a 0.6 /spl mu/m digital CMOS process. The DA dissipates 216 mW from a single 3 V supply. A custom CAD tool was used to optimize the DA design including device and package parasitics.
{"title":"A 0.5-8.5 GHz fully-differential CMOS RF distributed amplifier","authors":"Hee-Tae Ahn, D. Allstot","doi":"10.1109/SSMSD.2000.836456","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836456","url":null,"abstract":"A fully-differential four-stage distributed amplifier (DA) with 5.5 dB gain and 8.5 GHz bandwidth has been integrated in 1.3 mm/spl times/2.2 mm in a 0.6 /spl mu/m digital CMOS process. The DA dissipates 216 mW from a single 3 V supply. A custom CAD tool was used to optimize the DA design including device and package parasitics.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127092542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-02-27DOI: 10.1109/SSMSD.2000.836435
F.E. Kaimilev, J. Ekman, P. Chandramani, A. Krishnamoorthy, R. Rozier
The use of inter-chip optical interconnects can lead to a dramatic increase in chip-level and system-level performance of high-performance computing and signal processing systems. In this paper, we describe our efforts to build chipsets for these applications using optoelectronic VLSI. The performance advantages of using optical interconnects are compared with the conventional approach.
{"title":"CMOS DSP and microprocessor cores using optoelectronic VLSI","authors":"F.E. Kaimilev, J. Ekman, P. Chandramani, A. Krishnamoorthy, R. Rozier","doi":"10.1109/SSMSD.2000.836435","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836435","url":null,"abstract":"The use of inter-chip optical interconnects can lead to a dramatic increase in chip-level and system-level performance of high-performance computing and signal processing systems. In this paper, we describe our efforts to build chipsets for these applications using optoelectronic VLSI. The performance advantages of using optical interconnects are compared with the conventional approach.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131153201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-02-27DOI: 10.1109/SSMSD.2000.836442
Seoung-Jae Yoo, H. Ahn, M. Hella, M. Ismail
This paper reports the design and simulation results of a 433 MHz Power Amplifier (PA) which is designed in a 0.5 /spl mu/m CMOS technology and can provide variable gain modes. The PA consists of a driver and an output stage, and the gain is adjustable using digital codes. In this paper, 16.5 dB and 3.5 dB gain modes are chosen. This amplifier matches a 50 ohm load and provides 20 mW of output power at 432-434 MHz from a 3 V supply. The overall power efficiency is 30%.
{"title":"The design of 433 MHz class AB CMOS power amplifier","authors":"Seoung-Jae Yoo, H. Ahn, M. Hella, M. Ismail","doi":"10.1109/SSMSD.2000.836442","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836442","url":null,"abstract":"This paper reports the design and simulation results of a 433 MHz Power Amplifier (PA) which is designed in a 0.5 /spl mu/m CMOS technology and can provide variable gain modes. The PA consists of a driver and an output stage, and the gain is adjustable using digital codes. In this paper, 16.5 dB and 3.5 dB gain modes are chosen. This amplifier matches a 50 ohm load and provides 20 mW of output power at 432-434 MHz from a 3 V supply. The overall power efficiency is 30%.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128596081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-02-27DOI: 10.1109/SSMSD.2000.836440
Esteban Tlelo-Cuautle, L. A. Sarmiento-Reyes
In an attempt to provide an efficient biasing scheme for analog circuits, this paper addresses the problem of designing the correct bias-circuitry using the nullor concept. First, the rules for biasing nullators and norators are introduced. Second, a technique for efficiently biasing analog circuits is proposed. Finally, the proposed biasing technique is demonstrated by implementing it in practical circuits.
{"title":"Biasing analog circuits using the nullor concept","authors":"Esteban Tlelo-Cuautle, L. A. Sarmiento-Reyes","doi":"10.1109/SSMSD.2000.836440","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836440","url":null,"abstract":"In an attempt to provide an efficient biasing scheme for analog circuits, this paper addresses the problem of designing the correct bias-circuitry using the nullor concept. First, the rules for biasing nullators and norators are introduced. Second, a technique for efficiently biasing analog circuits is proposed. Finally, the proposed biasing technique is demonstrated by implementing it in practical circuits.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116388739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-02-27DOI: 10.1109/SSMSD.2000.836469
A. Walker, P. Lala
A new mixed-signal Built-in Self-Test (BIST) approach that is based upon voltage transitions at the primary output of the analog block under test (CUT) is presented in this paper. This CUT output is the pulse response of the CUT for a rail-to-rail pulse stream. The technique can effectively detect both soft and hard faults and does not require an analog-to-digital converter (ADC) or/and digital-to-analog converter (DAC). This approach also does not require any additional analog circuits to realize the test signal generator and sample circuits. The paper is concluded with an example of the application of the proposed approach for a passive second order notch filter.
{"title":"A dual edge transition based BIST approach for passive analog circuits","authors":"A. Walker, P. Lala","doi":"10.1109/SSMSD.2000.836469","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836469","url":null,"abstract":"A new mixed-signal Built-in Self-Test (BIST) approach that is based upon voltage transitions at the primary output of the analog block under test (CUT) is presented in this paper. This CUT output is the pulse response of the CUT for a rail-to-rail pulse stream. The technique can effectively detect both soft and hard faults and does not require an analog-to-digital converter (ADC) or/and digital-to-analog converter (DAC). This approach also does not require any additional analog circuits to realize the test signal generator and sample circuits. The paper is concluded with an example of the application of the proposed approach for a passive second order notch filter.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117090636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-02-27DOI: 10.1109/SSMSD.2000.836470
R. Urbieta Parrazales, M. Ramírez, S. Osvaldo Espinosa, J. Elena Aguilar, A. De Luca
This regular paper describes three important aspects: design, simulation and implementation of neuro-fuzzy control applied to the temperature variable of a thermal system with a range of 25/spl deg/C to 75/spl deg/C and resolution of 0.01%. In the design were found the membership functions and the fuzzy rules base already optimized of the fuzzy controller by means of a backpropagation neural network trained to 120 learning cycles. The simulation presents basic tables of the fuzzy controller obtained by the neural network. The implementation of the program of the fuzzy controller was effected using a 486 PC with conversion card A/D and of 8-bit port output.
{"title":"Learning of a backpropagation neural network to tune a fuzzy control of a thermal system","authors":"R. Urbieta Parrazales, M. Ramírez, S. Osvaldo Espinosa, J. Elena Aguilar, A. De Luca","doi":"10.1109/SSMSD.2000.836470","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836470","url":null,"abstract":"This regular paper describes three important aspects: design, simulation and implementation of neuro-fuzzy control applied to the temperature variable of a thermal system with a range of 25/spl deg/C to 75/spl deg/C and resolution of 0.01%. In the design were found the membership functions and the fuzzy rules base already optimized of the fuzzy controller by means of a backpropagation neural network trained to 120 learning cycles. The simulation presents basic tables of the fuzzy controller obtained by the neural network. The implementation of the program of the fuzzy controller was effected using a 486 PC with conversion card A/D and of 8-bit port output.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123689677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-02-27DOI: 10.1109/SSMSD.2000.836451
S. Jackson, B. Blalock, M. Mojarradi, H.W. Li
High-voltage transistors in SOI that coexist with traditional low-voltage transistors enable the development of mixed-voltage (high-voltage and low-voltage) systems-on-a-chip. The parasitic back-channel transistor, however, is a critical issue in these mixed-voltage single-chip systems. The presence of high-voltage can create a situation in which the parasitic back-channel device turns on and "shorts-out" the top device inducing functional failure of the system. An active substrate driver has been designed that automatically adjusts the substrate bias voltage to a level ensuring the back-channel devices remain off. The active substrate driver should also help compensate for shifts in back-channel transistor threshold voltages induced by temperature, aging, and irradiation effects.
{"title":"An active substrate driver for mixed-voltage SOI systems on a chip","authors":"S. Jackson, B. Blalock, M. Mojarradi, H.W. Li","doi":"10.1109/SSMSD.2000.836451","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836451","url":null,"abstract":"High-voltage transistors in SOI that coexist with traditional low-voltage transistors enable the development of mixed-voltage (high-voltage and low-voltage) systems-on-a-chip. The parasitic back-channel transistor, however, is a critical issue in these mixed-voltage single-chip systems. The presence of high-voltage can create a situation in which the parasitic back-channel device turns on and \"shorts-out\" the top device inducing functional failure of the system. An active substrate driver has been designed that automatically adjusts the substrate bias voltage to a level ensuring the back-channel devices remain off. The active substrate driver should also help compensate for shifts in back-channel transistor threshold voltages induced by temperature, aging, and irradiation effects.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123141067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-02-27DOI: 10.1109/SSMSD.2000.836457
B. Blalock, H.W. Li, P. Allen, S. Jackson
This paper presents an overview of circuit topologies for achieving low-voltage analog designs using body-driving techniques. A new and novel low-voltage Class AB output stage is presented along with topologies for amplifiers and a four quadrant multiplier. A discussion of the application of body-driving in a silicon-on-insulator (SOI) technology is also included.
{"title":"Body-driving as a low-voltage analog design technique for CMOS technology","authors":"B. Blalock, H.W. Li, P. Allen, S. Jackson","doi":"10.1109/SSMSD.2000.836457","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836457","url":null,"abstract":"This paper presents an overview of circuit topologies for achieving low-voltage analog designs using body-driving techniques. A new and novel low-voltage Class AB output stage is presented along with topologies for amplifiers and a four quadrant multiplier. A discussion of the application of body-driving in a silicon-on-insulator (SOI) technology is also included.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132442876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-02-27DOI: 10.1109/SSMSD.2000.836461
J. Compiet, P. D. Jong, P. Wambacq, G. Vandersteen, S. Donnay, D. M. Engels, I. Bolsens
A hierarchical high-level model of a high-speed flash ADC is presented. The input parameter list is extracted from a 400 MHz, 4-bit, flash ADC designed in HSPICE in a 0.35 /spl mu/m CMOS technology. A speedup in simulation time of 5000 is reported compared to the 3-bit flash ADC HSPICE simulations. The accuracy of the model is verified with HSPICE simulations and shows a good agreement.
{"title":"High-level modeling of a high-speed flash A/D converter for mixed-signal simulations of digital telecommunication front-ends","authors":"J. Compiet, P. D. Jong, P. Wambacq, G. Vandersteen, S. Donnay, D. M. Engels, I. Bolsens","doi":"10.1109/SSMSD.2000.836461","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836461","url":null,"abstract":"A hierarchical high-level model of a high-speed flash ADC is presented. The input parameter list is extracted from a 400 MHz, 4-bit, flash ADC designed in HSPICE in a 0.35 /spl mu/m CMOS technology. A speedup in simulation time of 5000 is reported compared to the 3-bit flash ADC HSPICE simulations. The accuracy of the model is verified with HSPICE simulations and shows a good agreement.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129414879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-02-27DOI: 10.1109/SSMSD.2000.836434
P. Marchand, S. Esener
The 3D-OESP consortium is a government-industry-university collaboration dedicated to the development of the technologies required to integrate stacked silicon chips with optoelectronic devices for high-performance computing and switching applications. By utilizing the combined strengths of 3D chip packaging and optoelectronic array interconnect technologies, it is possible to bring a low-power ultra-compact hardware solution to systems requiring fast processing and handling of large data arrays. We believe that, providing optoelectronic I/O to 3D chip stacks using VCSEL arrays with associated drivers, specially designed optical receivers, and micro-optics to direct the optical signals provide the most efficient way to communicate between the stacks. By integrating these components with a set of packaging techniques ranging from silicon micro-bench to plastic molded lenses, we are presently engaged in demonstrating the practical superiority of this approach in terms of system speed, power and volume metrics. We address various aspects of this approach that are being explored within the 3D-OESP consortium.
{"title":"Free-space optics for 3D multi-chip environment","authors":"P. Marchand, S. Esener","doi":"10.1109/SSMSD.2000.836434","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836434","url":null,"abstract":"The 3D-OESP consortium is a government-industry-university collaboration dedicated to the development of the technologies required to integrate stacked silicon chips with optoelectronic devices for high-performance computing and switching applications. By utilizing the combined strengths of 3D chip packaging and optoelectronic array interconnect technologies, it is possible to bring a low-power ultra-compact hardware solution to systems requiring fast processing and handling of large data arrays. We believe that, providing optoelectronic I/O to 3D chip stacks using VCSEL arrays with associated drivers, specially designed optical receivers, and micro-optics to direct the optical signals provide the most efficient way to communicate between the stacks. By integrating these components with a set of packaging techniques ranging from silicon micro-bench to plastic molded lenses, we are presently engaged in demonstrating the practical superiority of this approach in terms of system speed, power and volume metrics. We address various aspects of this approach that are being explored within the 3D-OESP consortium.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129783259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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