Pub Date : 2000-02-27DOI: 10.1109/SSMSD.2000.836441
JungBum Choi, S. Bampi, M. Ismail
This paper presents Operational Transconductance Amplifiers (OTA) designed on a pre-diffused array of digital Sea-Of-Transistors (SOT) using trapezoidal association of transistors (TAT) to emulate a single equivalent full-custom transistor. The TAT transistor is a composite of minimum channel length transistors, that achieves a DC and AC performance comparable to its equivalent single transistor. OTA amplifiers in both full-custom and SOT array methodology were implemented to allow better performance comparisons. The experimental results obtained for 1.0 /spl mu/m digital technology are presented.
{"title":"OTA amplifiers using the principle of trapezoidal association of transistors on a sea-of-transistors digital array","authors":"JungBum Choi, S. Bampi, M. Ismail","doi":"10.1109/SSMSD.2000.836441","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836441","url":null,"abstract":"This paper presents Operational Transconductance Amplifiers (OTA) designed on a pre-diffused array of digital Sea-Of-Transistors (SOT) using trapezoidal association of transistors (TAT) to emulate a single equivalent full-custom transistor. The TAT transistor is a composite of minimum channel length transistors, that achieves a DC and AC performance comparable to its equivalent single transistor. OTA amplifiers in both full-custom and SOT array methodology were implemented to allow better performance comparisons. The experimental results obtained for 1.0 /spl mu/m digital technology are presented.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129126285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-02-27DOI: 10.1109/SSMSD.2000.836453
U. Gatti, F. Maloberti
We present a new design approach for high resolution analog-to-digital converters operating at very high speeds. We show that using CMOS switches and the switched current technique are not convenient for advanced specifications. The switched buffer method proposed here offers new perspectives since it allows the designer to preserve accuracy even at high speeds of operation. The switched buffer consists of a bipolar high-speed unity gain amplifier controlled by a clock phase which allows the buffered output node to be turned into high impedance. We demonstrate the usability of switched buffers in a pipeline architecture and in a sigma delta modulator. Simulation results show that the circuits can operate at 200 MHz and 500 MHz respectively with an expected resolution better than 13-14 bit.
{"title":"Use of switched buffers in very high-speed data converters","authors":"U. Gatti, F. Maloberti","doi":"10.1109/SSMSD.2000.836453","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836453","url":null,"abstract":"We present a new design approach for high resolution analog-to-digital converters operating at very high speeds. We show that using CMOS switches and the switched current technique are not convenient for advanced specifications. The switched buffer method proposed here offers new perspectives since it allows the designer to preserve accuracy even at high speeds of operation. The switched buffer consists of a bipolar high-speed unity gain amplifier controlled by a clock phase which allows the buffered output node to be turned into high impedance. We demonstrate the usability of switched buffers in a pipeline architecture and in a sigma delta modulator. Simulation results show that the circuits can operate at 200 MHz and 500 MHz respectively with an expected resolution better than 13-14 bit.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129001751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-02-27DOI: 10.1109/SSMSD.2000.836467
K. Pun, J. Franca, C. Azeredo-Leme
Complex sub-sampling mixers are used in various kinds of image rejection receiver. The image rejection performance of these receivers is mainly limited by I/Q phase error. A digital calibration technique is proposed in this paper to correct this error. The phase error is measured by a statistical method with a local test signal, and is corrected in the baseband digital domain. With this method, the image rejection performance can be improved as much as 20 dB as indicated by high level simulation results.
{"title":"A digital method for the correction of I/Q phase errors in complex sub-sampling mixers","authors":"K. Pun, J. Franca, C. Azeredo-Leme","doi":"10.1109/SSMSD.2000.836467","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836467","url":null,"abstract":"Complex sub-sampling mixers are used in various kinds of image rejection receiver. The image rejection performance of these receivers is mainly limited by I/Q phase error. A digital calibration technique is proposed in this paper to correct this error. The phase error is measured by a statistical method with a local test signal, and is corrected in the baseband digital domain. With this method, the image rejection performance can be improved as much as 20 dB as indicated by high level simulation results.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"220 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115526582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-02-27DOI: 10.1109/SSMSD.2000.836464
S. Ozev, A. Orailoglu
We outline a methodology for system level test composition out of module level tests in the context of system-on-a-chip (SOC). The method can be utilized as soon as high level specifications are available providing avenues for testability insertion. The digital/analog interface is handled by a conversion from digital bits to analog signals. Experimental results show that high fault and yield coverages for most tests can be attained with no hardware alterations.
{"title":"Path-based test composition for mixed-signal SOC's","authors":"S. Ozev, A. Orailoglu","doi":"10.1109/SSMSD.2000.836464","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836464","url":null,"abstract":"We outline a methodology for system level test composition out of module level tests in the context of system-on-a-chip (SOC). The method can be utilized as soon as high level specifications are available providing avenues for testability insertion. The digital/analog interface is handled by a conversion from digital bits to analog signals. Experimental results show that high fault and yield coverages for most tests can be attained with no hardware alterations.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125859717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-02-27DOI: 10.1109/SSMSD.2000.836458
Robert C. Fpre, Bell Luboratories, Lucent Technohgies
We use a stochastic model of the switching current to describe the power spectral density of current noise waveforms induced by digital switching events. We discuss common impedance paths, particularly arising from non-ideal properties of electronic packages, that couple this noise into the substrate of an integrated circuit. We derive estimates of the noise spectrum for modest digital power and typical package characteristics and evaluate the noise in the context of RF mixed-signal designs. Common TQFP packages show significantly worse noise performance than BGA packages with low inductance substrate ground, and are less suitable for demanding applications. The adoption of differential design methods can eliminate this source of common-mode noise, at the expense of added power or higher noise figure.
{"title":"Switching-induced substrate noise and mixed-signal receiver design","authors":"Robert C. Fpre, Bell Luboratories, Lucent Technohgies","doi":"10.1109/SSMSD.2000.836458","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836458","url":null,"abstract":"We use a stochastic model of the switching current to describe the power spectral density of current noise waveforms induced by digital switching events. We discuss common impedance paths, particularly arising from non-ideal properties of electronic packages, that couple this noise into the substrate of an integrated circuit. We derive estimates of the noise spectrum for modest digital power and typical package characteristics and evaluate the noise in the context of RF mixed-signal designs. Common TQFP packages show significantly worse noise performance than BGA packages with low inductance substrate ground, and are less suitable for demanding applications. The adoption of differential design methods can eliminate this source of common-mode noise, at the expense of added power or higher noise figure.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126521449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-02-27DOI: 10.1109/SSMSD.2000.836448
J. Wikner, M. Vesterbacka
We evaluate the performance of flash D/A converters designed with a new approach based on linear coding of the weights. The evaluation is performed by estimating the relative performance of the new, linear-coded converter compared with thermometer coded, binary-scaled, and segmented converters. As a measure of performance we use glitch noise, which is of importance in high-speed D/A converter operation. We also consider linearity measures such as the differential and integral nonlinearities to illustrate the typical impact of matching errors in the different converter types. A bound is given on the converter size at which the glitch performance becomes better for the linear-coded than for the segmented D/A converter.
{"title":"Characteristics of linear-coded D/A converters","authors":"J. Wikner, M. Vesterbacka","doi":"10.1109/SSMSD.2000.836448","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836448","url":null,"abstract":"We evaluate the performance of flash D/A converters designed with a new approach based on linear coding of the weights. The evaluation is performed by estimating the relative performance of the new, linear-coded converter compared with thermometer coded, binary-scaled, and segmented converters. As a measure of performance we use glitch noise, which is of importance in high-speed D/A converter operation. We also consider linearity measures such as the differential and integral nonlinearities to illustrate the typical impact of matching errors in the different converter types. A bound is given on the converter size at which the glitch performance becomes better for the linear-coded than for the segmented D/A converter.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116746655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Mumbru, Gan Zhou, Suat U. Ay, X. An, G. Panotopoulos, F. Mok, D. Psaltis
Reconfigurable processors, like the field programmable gate arrays (FPGAs), open new computational paradigms where the processor is able to tailor its internal structure to better implement a given application. A typical FPGA consists of an array of configurable logic blocks and a mesh of interconnections fully programmable by the user to perform a given application. By just changing its internal connectivity, the FPGA can implement a totally different new function. However in most of the applications, the FPGA is configured only once and used as coprocessor to carry out some highly complex or time-consuming computation. The reason for such limitation is the small communication bandwidth between the FPGA chip and the external memory, usually ROM, where the configuration data is stored. The Optically Programmable Gate Array (OPGA), an enhanced version of a conventional FPGA, can overcome this problem. The OPGA utilizes a holographic memory accessed by an array of VCSELs to program its logic. The on-chip logic has been complemented with an array of photodetectors to detect the configuration template recorded in the memory. Combining spatial and shift multiplexing to store the configuration pages in the memory, the OPGA module is very compact and has extremely short configuration time allowing for dynamic reconfiguration. The reconfiguration capability of the OPGA can be applied to solve more efficiently problems in pattern recognition and digit classification.
{"title":"Optically reconfigurable processors","authors":"J. Mumbru, Gan Zhou, Suat U. Ay, X. An, G. Panotopoulos, F. Mok, D. Psaltis","doi":"10.1117/12.365910","DOIUrl":"https://doi.org/10.1117/12.365910","url":null,"abstract":"Reconfigurable processors, like the field programmable gate arrays (FPGAs), open new computational paradigms where the processor is able to tailor its internal structure to better implement a given application. A typical FPGA consists of an array of configurable logic blocks and a mesh of interconnections fully programmable by the user to perform a given application. By just changing its internal connectivity, the FPGA can implement a totally different new function. However in most of the applications, the FPGA is configured only once and used as coprocessor to carry out some highly complex or time-consuming computation. The reason for such limitation is the small communication bandwidth between the FPGA chip and the external memory, usually ROM, where the configuration data is stored. The Optically Programmable Gate Array (OPGA), an enhanced version of a conventional FPGA, can overcome this problem. The OPGA utilizes a holographic memory accessed by an array of VCSELs to program its logic. The on-chip logic has been complemented with an array of photodetectors to detect the configuration template recorded in the memory. Combining spatial and shift multiplexing to store the configuration pages in the memory, the OPGA module is very compact and has extremely short configuration time allowing for dynamic reconfiguration. The reconfiguration capability of the OPGA can be applied to solve more efficiently problems in pattern recognition and digit classification.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134628562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SSMSD.2000.836468
Tso-Bing Juang, Shen-Fu Hsiao
In this paper the application of CORDIC (COordinate Rotation DIgital Computer) processor using leading zeros detector (LZD) is discussed. In previous research, LZD was used in the normalization of the floating point number computation, also we find that it can be used in the CORDIC processor for reducing the number of iterations, deciding the sign of redundant number and speeding the computation of the exponent.
{"title":"Discussions on the CORDIC processor using leading zeros detector","authors":"Tso-Bing Juang, Shen-Fu Hsiao","doi":"10.1109/SSMSD.2000.836468","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836468","url":null,"abstract":"In this paper the application of CORDIC (COordinate Rotation DIgital Computer) processor using leading zeros detector (LZD) is discussed. In previous research, LZD was used in the normalization of the floating point number computation, also we find that it can be used in the CORDIC processor for reducing the number of iterations, deciding the sign of redundant number and speeding the computation of the exponent.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123090238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SSMSD.2000.836472
H. Chiueh, L. Luh, J. Draper, J. Choma
A low-cost, high-efficiency, compact architecture of a PWM (pulse-width-modulation) drive fan controller is designed for use in an embedded multicomputer system with an integrated hierarchical thermal management scheme. This pure digital design yields lower cost and higher conventional linear drive fan providing the functionality and advantages of PWM drive fan controllers. The implementation and system integration of this circuit is also described in this paper.
{"title":"A novel fully integrated fan controller for advanced computer systems","authors":"H. Chiueh, L. Luh, J. Draper, J. Choma","doi":"10.1109/SSMSD.2000.836472","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836472","url":null,"abstract":"A low-cost, high-efficiency, compact architecture of a PWM (pulse-width-modulation) drive fan controller is designed for use in an embedded multicomputer system with an integrated hierarchical thermal management scheme. This pure digital design yields lower cost and higher conventional linear drive fan providing the functionality and advantages of PWM drive fan controllers. The implementation and system integration of this circuit is also described in this paper.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121232012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SSMSD.2000.836460
Y. Zinzius, E. Lauwers, G. Gielen, Willy Sansen
This paper describes an approach used to simulate the bulk in such a way that we can evaluate the substrate noise effect on analog designs. For these simulations a simple model is used in order to reduce the time needed for the simulations. In this model we take into account the effect of the bonding wire and the bulk resistance. This simulation technique was applied to a sample and hold circuit.
{"title":"Evaluation of the substrate noise effect on analog circuits in mixed-signal designs","authors":"Y. Zinzius, E. Lauwers, G. Gielen, Willy Sansen","doi":"10.1109/SSMSD.2000.836460","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836460","url":null,"abstract":"This paper describes an approach used to simulate the bulk in such a way that we can evaluate the substrate noise effect on analog designs. For these simulations a simple model is used in order to reduce the time needed for the simulations. In this model we take into account the effect of the bonding wire and the bulk resistance. This simulation technique was applied to a sample and hold circuit.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"5005 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122138225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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