Pub Date : 2000-02-27DOI: 10.1109/SSMSD.2000.836466
T. Haniotakis, E. Kalligeros, D. Nikolos, G. Sidiropulos, Y. Tsiatouhas, H. T. Vergos
The number of physical paths in a carry save or modified Booth multiplier, as well as in a non-restoring cellular array divider is prohibitively large for testing all paths for delay faults. Besides, neither all paths are robustly testable nor a basis consisting of SPP-HFRT paths exists. In this paper we present sufficient modifications of the above mentioned circuits so that a basis consisting of SPP-HFRT paths exists. The cardinality of the derived basis is very small. Also, hardware and delay overheads due to the modifications are respectively small and negligible.
{"title":"A class of easily path delay fault testable circuits","authors":"T. Haniotakis, E. Kalligeros, D. Nikolos, G. Sidiropulos, Y. Tsiatouhas, H. T. Vergos","doi":"10.1109/SSMSD.2000.836466","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836466","url":null,"abstract":"The number of physical paths in a carry save or modified Booth multiplier, as well as in a non-restoring cellular array divider is prohibitively large for testing all paths for delay faults. Besides, neither all paths are robustly testable nor a basis consisting of SPP-HFRT paths exists. In this paper we present sufficient modifications of the above mentioned circuits so that a basis consisting of SPP-HFRT paths exists. The cardinality of the derived basis is very small. Also, hardware and delay overheads due to the modifications are respectively small and negligible.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116500192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-02-27DOI: 10.1109/SSMSD.2000.836433
R. Tumbar, D. Brady
Digital imaging systems are fundamentally different from analog ones because they differentiate the measurement space and the reconstruction space. Multiplex systems use this separation to optimize source reconstruction. We consider the requirements imposed on sensor plane processors by multiplex imaging systems. We consider system flexibility, analog/digital split, A/D dynamic range, bandwidth, and sensitivity.
{"title":"Sensor plane processing for multiplex imaging","authors":"R. Tumbar, D. Brady","doi":"10.1109/SSMSD.2000.836433","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836433","url":null,"abstract":"Digital imaging systems are fundamentally different from analog ones because they differentiate the measurement space and the reconstruction space. Multiplex systems use this separation to optimize source reconstruction. We consider the requirements imposed on sensor plane processors by multiplex imaging systems. We consider system flexibility, analog/digital split, A/D dynamic range, bandwidth, and sensitivity.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134004276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-02-27DOI: 10.1109/SSMSD.2000.836462
W. Zhang, M. Hassoun
This paper describes a small signal model and analysis results for a general configuration of a gain-boosting amplifier. The simulation results generated by MATLAB matched well to HSPICE results. According to the model, the DC gain and the dominant pole approximation formulae are derived. The pole-zero movement behavior related to the model parameters are also investigated. All of above leads to a very useful model to guide the design and understanding of the gain-boosting amplifier.
{"title":"A small signal analysis of a gain-boosting amplifier","authors":"W. Zhang, M. Hassoun","doi":"10.1109/SSMSD.2000.836462","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836462","url":null,"abstract":"This paper describes a small signal model and analysis results for a general configuration of a gain-boosting amplifier. The simulation results generated by MATLAB matched well to HSPICE results. According to the model, the DC gain and the dominant pole approximation formulae are derived. The pole-zero movement behavior related to the model parameters are also investigated. All of above leads to a very useful model to guide the design and understanding of the gain-boosting amplifier.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123489678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-02-27DOI: 10.1109/SSMSD.2000.836446
C. Binan Wang, J. Todsen, T. Kalthoff
A dual channel 20 bit current-input A/D converter is implemented in a 0.6 /spl mu/m CMOS process with a single 5 V supply for use in direct photo-sensor digitization. Continuous charge integration is achieved through the use of a double switched capacitor integrator at each channel input. The front end provides a programmable full-scale input charge range from 50 pC to 1000 pC while also converting the input current to a voltage output. The voltage output of the switched integrator is then digitized by a high dynamic range delta-sigma converter that multiplexes between the two input channels. This current-input A/D converter achieves 3 ppm RMS noise and 1 ppm linearity with low level inputs.
{"title":"A dual channel 20 bit current-input A/D converter for photo-sensor applications","authors":"C. Binan Wang, J. Todsen, T. Kalthoff","doi":"10.1109/SSMSD.2000.836446","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836446","url":null,"abstract":"A dual channel 20 bit current-input A/D converter is implemented in a 0.6 /spl mu/m CMOS process with a single 5 V supply for use in direct photo-sensor digitization. Continuous charge integration is achieved through the use of a double switched capacitor integrator at each channel input. The front end provides a programmable full-scale input charge range from 50 pC to 1000 pC while also converting the input current to a voltage output. The voltage output of the switched integrator is then digitized by a high dynamic range delta-sigma converter that multiplexes between the two input channels. This current-input A/D converter achieves 3 ppm RMS noise and 1 ppm linearity with low level inputs.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125104654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-02-27DOI: 10.1109/SSMSD.2000.836463
Jiun-Lang Huang, K. Cheng
We present the architecture and analysis of a built-in self-test (BIST) scheme that targets mixed-signal system-on-chip (SOC) designs. The basic idea is to employ simple yet high-tolerant digital-to-analog (DA) and analog-to-digital (AD) conversion techniques for on-chip stimulus generation and response acquisition, and to utilize on-chip programmable cores for digital signal processing required for signal synthesis and response analysis. Numerical simulations are conducted to validate the idea and the results demonstrate the effectiveness of this BIST scheme.
{"title":"A delta-sigma modulation based BIST scheme for mixed-signal systems","authors":"Jiun-Lang Huang, K. Cheng","doi":"10.1109/SSMSD.2000.836463","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836463","url":null,"abstract":"We present the architecture and analysis of a built-in self-test (BIST) scheme that targets mixed-signal system-on-chip (SOC) designs. The basic idea is to employ simple yet high-tolerant digital-to-analog (DA) and analog-to-digital (AD) conversion techniques for on-chip stimulus generation and response acquisition, and to utilize on-chip programmable cores for digital signal processing required for signal synthesis and response analysis. Numerical simulations are conducted to validate the idea and the results demonstrate the effectiveness of this BIST scheme.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134201372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-02-27DOI: 10.1109/SSMSD.2000.836443
Yuyu Chang, J. Choma
A CMOS inductorless image-reject filter based on active RLC circuitry is discussed and designed with the emphasis on low-noise, low-power, and gigahertz-range circuits. Two Q-enhancement techniques are utilized to circumvent the low Q characteristics inherent in the simple feedback circuit. The frequency tuning is almost independent of Q tuning, facilitating the design of the automatic tuning circuitry. The stability of the filter is also discussed. Simulations using 0.6 /spl mu/m CMOS technology demonstrate the feasibility of the tunable image-reject filter for GSM wireless applications. Simulation results show 4.75 dB voltage gain, 7.2 dB noise figure, and -20 dBm IIP3 at a passband centered at 947 MHz. The image signal suppression is 60 dB at 1089 MHz and the power consumption is 27 mW.
{"title":"A monolithic RF image-reject filter","authors":"Yuyu Chang, J. Choma","doi":"10.1109/SSMSD.2000.836443","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836443","url":null,"abstract":"A CMOS inductorless image-reject filter based on active RLC circuitry is discussed and designed with the emphasis on low-noise, low-power, and gigahertz-range circuits. Two Q-enhancement techniques are utilized to circumvent the low Q characteristics inherent in the simple feedback circuit. The frequency tuning is almost independent of Q tuning, facilitating the design of the automatic tuning circuitry. The stability of the filter is also discussed. Simulations using 0.6 /spl mu/m CMOS technology demonstrate the feasibility of the tunable image-reject filter for GSM wireless applications. Simulation results show 4.75 dB voltage gain, 7.2 dB noise figure, and -20 dBm IIP3 at a passband centered at 947 MHz. The image signal suppression is 60 dB at 1089 MHz and the power consumption is 27 mW.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116053709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-02-27DOI: 10.1109/SSMSD.2000.836459
A. Gothenberg, E. Soenen, H. Tenhunen
This paper presents methods to model and analyze substrate coupled noise in pipelined data converters. The substrate noise models covers substrate types, such as lightly and highly doped substrates, and the analyzes includes the effects on the pipelined data converter performance from a variety of noise shielding techniques, such as guarding and wells. Classical approaches to prevent noise are investigated. It is found that in some cases these traditional design rules are no longer suitable and have to be redefined.
{"title":"Modeling and analysis of substrate coupled noise in pipelined data converters","authors":"A. Gothenberg, E. Soenen, H. Tenhunen","doi":"10.1109/SSMSD.2000.836459","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836459","url":null,"abstract":"This paper presents methods to model and analyze substrate coupled noise in pipelined data converters. The substrate noise models covers substrate types, such as lightly and highly doped substrates, and the analyzes includes the effects on the pipelined data converter performance from a variety of noise shielding techniques, such as guarding and wells. Classical approaches to prevent noise are investigated. It is found that in some cases these traditional design rules are no longer suitable and have to be redefined.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122108340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-02-27DOI: 10.1109/SSMSD.2000.836449
S. Abdennadher
In order to reduce the number of design iteration for complex mixed signal telecommunication IC's, verification through full chip simulation is a must. The objective is to verify connectivity and functionality for the whole chip including the interface between analog and digital blocks. Efficient top level simulation required the use of a mixed mode (Analog and Digital) simulator. In addition, in order to accomplish this task, behavioral models of all the system building blocks of the design were developed and used to replace the transistor level sub-circuit description. The design sub-blocks were modeled in HDLA.
{"title":"Behavioral modeling of a SONET/SDH transceiver using HDLA","authors":"S. Abdennadher","doi":"10.1109/SSMSD.2000.836449","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836449","url":null,"abstract":"In order to reduce the number of design iteration for complex mixed signal telecommunication IC's, verification through full chip simulation is a must. The objective is to verify connectivity and functionality for the whole chip including the interface between analog and digital blocks. Efficient top level simulation required the use of a mixed mode (Analog and Digital) simulator. In addition, in order to accomplish this task, behavioral models of all the system building blocks of the design were developed and used to replace the transistor level sub-circuit description. The design sub-blocks were modeled in HDLA.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130456047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-02-27DOI: 10.1109/SSMSD.2000.836471
C. Tsai, S. Kang
A multiport RC network reduction technique based on congruence transformation was developed specifically for improving the efficiency of temperature calculation in electrothermal simulations. This technique helps reduce the size of the three-dimensional lumped RC network, which is commonly used to model substrate heat conduction, while still preserving the input/output characteristics at the port nodes. A smaller thermal network leads to more efficient substrate temperature calculation. Furthermore, the reduced network can be combined with the device netlist to perform tightly-coupled electrothermal simulation for some cases when the large data size dictates the employment of the more time-consuming relaxation-based temperature calculation method. Our method is applicable to both static and dynamic electrothermal simulations for either localized or large-scale analyses. Runtime improvements in the range of 2/spl times//spl sim/3/spl times/ have been achieved in simulations.
{"title":"Substrate thermal model reduction for efficient transient electrothermal simulation","authors":"C. Tsai, S. Kang","doi":"10.1109/SSMSD.2000.836471","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836471","url":null,"abstract":"A multiport RC network reduction technique based on congruence transformation was developed specifically for improving the efficiency of temperature calculation in electrothermal simulations. This technique helps reduce the size of the three-dimensional lumped RC network, which is commonly used to model substrate heat conduction, while still preserving the input/output characteristics at the port nodes. A smaller thermal network leads to more efficient substrate temperature calculation. Furthermore, the reduced network can be combined with the device netlist to perform tightly-coupled electrothermal simulation for some cases when the large data size dictates the employment of the more time-consuming relaxation-based temperature calculation method. Our method is applicable to both static and dynamic electrothermal simulations for either localized or large-scale analyses. Runtime improvements in the range of 2/spl times//spl sim/3/spl times/ have been achieved in simulations.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125194319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-02-27DOI: 10.1109/SSMSD.2000.836439
R. Stair, J. Connelly, M. Pulkin
A current mode CMOS voltage reference uses a p-channel MOSFET threshold voltage extractor circuit to create a current that is inversely proportional to temperature. This current is summed with a current that is proportional to temperature into a resistor to create a voltage that is, to the first order, temperature independent. The output voltage is scalable by adjusting the size of the summing resistor. The circuit operates over temperature from 0 to 100/spl deg/C with a power supply voltage between 3.3 and 7 V. Experimental results show that over these conditions, the output voltage varies by /spl plusmn/3%.
{"title":"A current mode CMOS voltage reference","authors":"R. Stair, J. Connelly, M. Pulkin","doi":"10.1109/SSMSD.2000.836439","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836439","url":null,"abstract":"A current mode CMOS voltage reference uses a p-channel MOSFET threshold voltage extractor circuit to create a current that is inversely proportional to temperature. This current is summed with a current that is proportional to temperature into a resistor to create a voltage that is, to the first order, temperature independent. The output voltage is scalable by adjusting the size of the summing resistor. The circuit operates over temperature from 0 to 100/spl deg/C with a power supply voltage between 3.3 and 7 V. Experimental results show that over these conditions, the output voltage varies by /spl plusmn/3%.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122151348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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