Pub Date : 2012-04-10DOI: 10.1109/LATW.2012.6261252
O. Sinanoglu, V. Agrawal
Scan design has a performance penalty that affects the critical path delay by an added fanout at the origin and a multiplexer at the destination. This problem is outlined in a recent paper [10], which also proposes a solution. The purpose of the present work is to provide a retiming solution. Retiming of a synchronous sequential circuit is a transformation that moves flip-flops through combinational logic without altering the function. We move the destination flip-flop of a critical path backward through its scan multiplexer. This splits the flip-flop into three, one on each input of the multiplexer. First of these is the “original flip-flop” in the normal data path. The second, called “shadow flip-flop”, appears only in the scan path. The third flip-flops from all critical paths are replaced by a single flip-flop that generates a delayed scan enable signal for controlling all retimed multiplexers. We further show how the fanout delay at the origin of a critical path can be eliminated by additional retiming. The use of the formally proven retiming transformations preserve both the function of the circuit and its scan operation without any change. The retimed scan, therefore, can test DC as well as delay faults. Benchmark results show further timing improvement and reduced hardware overhead compared to previously reported results [10].
{"title":"Retiming scan circuit to eliminate timing penalty","authors":"O. Sinanoglu, V. Agrawal","doi":"10.1109/LATW.2012.6261252","DOIUrl":"https://doi.org/10.1109/LATW.2012.6261252","url":null,"abstract":"Scan design has a performance penalty that affects the critical path delay by an added fanout at the origin and a multiplexer at the destination. This problem is outlined in a recent paper [10], which also proposes a solution. The purpose of the present work is to provide a retiming solution. Retiming of a synchronous sequential circuit is a transformation that moves flip-flops through combinational logic without altering the function. We move the destination flip-flop of a critical path backward through its scan multiplexer. This splits the flip-flop into three, one on each input of the multiplexer. First of these is the “original flip-flop” in the normal data path. The second, called “shadow flip-flop”, appears only in the scan path. The third flip-flops from all critical paths are replaced by a single flip-flop that generates a delayed scan enable signal for controlling all retimed multiplexers. We further show how the fanout delay at the origin of a critical path can be eliminated by additional retiming. The use of the formally proven retiming transformations preserve both the function of the circuit and its scan operation without any change. The retimed scan, therefore, can test DC as well as delay faults. Benchmark results show further timing improvement and reduced hardware overhead compared to previously reported results [10].","PeriodicalId":173735,"journal":{"name":"2012 13th Latin American Test Workshop (LATW)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114056491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-10DOI: 10.1109/LATW.2012.6261230
W. C. Bartra, F. Kastensmidt, R. Reis
In Integrated Circuits (ICs), the faults can lead to permanent, transient or intermittent errors. In the case of transient faults, they take place for a very short time. These faults can lead from small unexpected changes in the results or even in the circuit complete and permanent failure. One of transient fault is known as Single-Event Transient (SET), which occur in combinational logic and analog circuits typically. The study of the behavior of a circuit under fault is important to choose the protection techniques and measurement of susceptibility to the type of fault inserted. Nowadays, the fault simulation is an important step in any IC design. Predicting the behavioral faults is essential to ensure that the design is well implemented. During simulation various problems can be detected and corrected. We present a toolkit to simulate the effect that occurs when a SET failure source is inserted in a 250nm CMOS Voltage Controlled Oscillator (VCO) using National Instruments LabVIEW. The results of these simulations were compared with results obtained in the laboratory by W. Chen et al. in 2003.
{"title":"Simulation of SET faults in a voltage controlled oscillator","authors":"W. C. Bartra, F. Kastensmidt, R. Reis","doi":"10.1109/LATW.2012.6261230","DOIUrl":"https://doi.org/10.1109/LATW.2012.6261230","url":null,"abstract":"In Integrated Circuits (ICs), the faults can lead to permanent, transient or intermittent errors. In the case of transient faults, they take place for a very short time. These faults can lead from small unexpected changes in the results or even in the circuit complete and permanent failure. One of transient fault is known as Single-Event Transient (SET), which occur in combinational logic and analog circuits typically. The study of the behavior of a circuit under fault is important to choose the protection techniques and measurement of susceptibility to the type of fault inserted. Nowadays, the fault simulation is an important step in any IC design. Predicting the behavioral faults is essential to ensure that the design is well implemented. During simulation various problems can be detected and corrected. We present a toolkit to simulate the effect that occurs when a SET failure source is inserted in a 250nm CMOS Voltage Controlled Oscillator (VCO) using National Instruments LabVIEW. The results of these simulations were compared with results obtained in the laboratory by W. Chen et al. in 2003.","PeriodicalId":173735,"journal":{"name":"2012 13th Latin American Test Workshop (LATW)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124223476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-10DOI: 10.1109/LATW.2012.6261244
I. Beretta, F. Rincón, N. Khaled, P. Grassi, V. Rana, David Atienza Alonso, D. Sciuto
Wireless body sensor networks (WBSNs) are a rising technology that allows constant and unobtrusive monitoring of the vital signals of a patient. The configuration of a WBSN node proves to be critical in order to maximize its lifetime, while meeting the predefined performance during signal sensing, preprocessing, and wireless transmission to the base station. In this work, we propose a model-based optimization framework for WBSN nodes, which is centered on a detailed analytical characterization of the most energy-demanding components of this application domain. We also propose a multi-objective exploration algorithm to evaluate the node configurations and the corresponding performance tradeoffs. A case study is discussed to validate the proposed framework, proving that our model captures the behavior of real WBSNs and efficiently leads to the determination of the Pareto-optimal configurations.
{"title":"Model-based design for wireless body sensor network nodes","authors":"I. Beretta, F. Rincón, N. Khaled, P. Grassi, V. Rana, David Atienza Alonso, D. Sciuto","doi":"10.1109/LATW.2012.6261244","DOIUrl":"https://doi.org/10.1109/LATW.2012.6261244","url":null,"abstract":"Wireless body sensor networks (WBSNs) are a rising technology that allows constant and unobtrusive monitoring of the vital signals of a patient. The configuration of a WBSN node proves to be critical in order to maximize its lifetime, while meeting the predefined performance during signal sensing, preprocessing, and wireless transmission to the base station. In this work, we propose a model-based optimization framework for WBSN nodes, which is centered on a detailed analytical characterization of the most energy-demanding components of this application domain. We also propose a multi-objective exploration algorithm to evaluate the node configurations and the corresponding performance tradeoffs. A case study is discussed to validate the proposed framework, proving that our model captures the behavior of real WBSNs and efficiently leads to the determination of the Pareto-optimal configurations.","PeriodicalId":173735,"journal":{"name":"2012 13th Latin American Test Workshop (LATW)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116577288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-10DOI: 10.1109/LATW.2012.6261247
F. Haddad, W. Rahajandraibe, H. Aziza, K. Castellani-Coulié, J. Portal
A built-in tuning circuit of RadioFrequency (RF) Passive Polyphase Filter (PPF) for image rejection in low Intermediate Frequency (IF) receiver is presented. The resistance values of the filter are process dependent and can severely impact the circuit performances if not controlled. In order to overcome this limitation, an in-line auto-calibration of the PPF resistance values, based on Design Of Experiment (DOE) methodology, is presented. Using DOE, a model is derived from thermal and process deviations of the chip responses. This approach results in a robust and low cost solution.
{"title":"Built-in tuning of RFIC Passive Polyphase Filter by process and thermal monitoring","authors":"F. Haddad, W. Rahajandraibe, H. Aziza, K. Castellani-Coulié, J. Portal","doi":"10.1109/LATW.2012.6261247","DOIUrl":"https://doi.org/10.1109/LATW.2012.6261247","url":null,"abstract":"A built-in tuning circuit of RadioFrequency (RF) Passive Polyphase Filter (PPF) for image rejection in low Intermediate Frequency (IF) receiver is presented. The resistance values of the filter are process dependent and can severely impact the circuit performances if not controlled. In order to overcome this limitation, an in-line auto-calibration of the PPF resistance values, based on Design Of Experiment (DOE) methodology, is presented. Using DOE, a model is derived from thermal and process deviations of the chip responses. This approach results in a robust and low cost solution.","PeriodicalId":173735,"journal":{"name":"2012 13th Latin American Test Workshop (LATW)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122775597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-10DOI: 10.1109/LATW.2012.6261256
R. Chipana, F. Kastensmidt, Jorge Tonfat, R. Reis
Clock networks are composed of buffers and flip-flops that are susceptible to Single Event Transient (SET) faults. Therefore, it is important to evaluate in terms of SET vulnerability when designing radiation-hardened circuits. For that, we developed an automatic method of extraction of clock network parameters from any ASIC design layout to allow a more precise SET propagation analysis by electrical simulations. We analyzed the clock tree network from SRAM arbiter layout using the proposed methodology and we found that the most vulnerable nodes in the clock tree are the output of the smaller buffers and nodes with lowest fan-out.
{"title":"SET susceptibility estimation of clock tree networks from layout extraction","authors":"R. Chipana, F. Kastensmidt, Jorge Tonfat, R. Reis","doi":"10.1109/LATW.2012.6261256","DOIUrl":"https://doi.org/10.1109/LATW.2012.6261256","url":null,"abstract":"Clock networks are composed of buffers and flip-flops that are susceptible to Single Event Transient (SET) faults. Therefore, it is important to evaluate in terms of SET vulnerability when designing radiation-hardened circuits. For that, we developed an automatic method of extraction of clock network parameters from any ASIC design layout to allow a more precise SET propagation analysis by electrical simulations. We analyzed the clock tree network from SRAM arbiter layout using the proposed methodology and we found that the most vulnerable nodes in the clock tree are the output of the smaller buffers and nodes with lowest fan-out.","PeriodicalId":173735,"journal":{"name":"2012 13th Latin American Test Workshop (LATW)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124879915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-10DOI: 10.1109/LATW.2012.6261249
A. Timár, M. Rencz
In today's digital electronic integrated circuits device heating is one of the most critical issues. Overheating can cause failures in functionality and device malfunction. In certain circumstances overheating of ICs can cause physical destruction of the device itself. This paper introduces a solution to determine cell and gate heating curves across the standard cell ICs surface. The presented methodology and toolset is tightly integrated into standardized logic simulator engines thus providing digital circuit designers a low-level, cell-resolution temperature distribution map during logic simulations. Actual temperatures of each con- sisting cell of the design can be monitored throughout the whole logic simulation. By being able to monitor temperatures of digital cells during initial simulations, it allows us to detect hot-spots and overheating caused malfunctions far before manufacture. By using the spatial location and temperature magnitude of hot-spots acquired from the presented methodology, place and route (P&R) tools can be driven to change cell placement and routing in order to avoid heating caused failures. Additionally, cooling solutions can be developed using the simulated temperature maps of the ICs surface.
{"title":"Acquiring real-time heating of cells in standard cell designs","authors":"A. Timár, M. Rencz","doi":"10.1109/LATW.2012.6261249","DOIUrl":"https://doi.org/10.1109/LATW.2012.6261249","url":null,"abstract":"In today's digital electronic integrated circuits device heating is one of the most critical issues. Overheating can cause failures in functionality and device malfunction. In certain circumstances overheating of ICs can cause physical destruction of the device itself. This paper introduces a solution to determine cell and gate heating curves across the standard cell ICs surface. The presented methodology and toolset is tightly integrated into standardized logic simulator engines thus providing digital circuit designers a low-level, cell-resolution temperature distribution map during logic simulations. Actual temperatures of each con- sisting cell of the design can be monitored throughout the whole logic simulation. By being able to monitor temperatures of digital cells during initial simulations, it allows us to detect hot-spots and overheating caused malfunctions far before manufacture. By using the spatial location and temperature magnitude of hot-spots acquired from the presented methodology, place and route (P&R) tools can be driven to change cell placement and routing in order to avoid heating caused failures. Additionally, cooling solutions can be developed using the simulated temperature maps of the ICs surface.","PeriodicalId":173735,"journal":{"name":"2012 13th Latin American Test Workshop (LATW)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133396006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-10DOI: 10.1109/LATW.2012.6261243
R. Ubar, S. Kostin, J. Raik
We present a new idea of test groups as a general approach to generate test patterns for multiple stuck-at-faults in combinational circuits. All faults of any multiplicity are assumed present in the circuit and we do not need to enumerate them. Unlike the known approaches, we do not target faults as test objectives. The goal is to verify the correctness of a part of the circuit The final test is presented as a set of test pattern groups where each group has the goal to identify the correctness of a selected part of a circuit. The method facilitates fault diagnosis in the presence of multiple faults. The knowledge about identified correct parts of the circuit allows to extend step by step the core of the circuit proved as correct.
{"title":"About robustness of test patterns regarding multiple faults","authors":"R. Ubar, S. Kostin, J. Raik","doi":"10.1109/LATW.2012.6261243","DOIUrl":"https://doi.org/10.1109/LATW.2012.6261243","url":null,"abstract":"We present a new idea of test groups as a general approach to generate test patterns for multiple stuck-at-faults in combinational circuits. All faults of any multiplicity are assumed present in the circuit and we do not need to enumerate them. Unlike the known approaches, we do not target faults as test objectives. The goal is to verify the correctness of a part of the circuit The final test is presented as a set of test pattern groups where each group has the goal to identify the correctness of a selected part of a circuit. The method facilitates fault diagnosis in the presence of multiple faults. The knowledge about identified correct parts of the circuit allows to extend step by step the core of the circuit proved as correct.","PeriodicalId":173735,"journal":{"name":"2012 13th Latin American Test Workshop (LATW)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133711921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-10DOI: 10.1109/LATW.2012.6261255
G. Cardoso, T. Balen, M. Lubaszewski, R. G. Vaz, O. Gonçalez
This paper presents an investigation on the performance of analog building-blocks of two counterpart architectures of Operational Amplifiers (with PMOS and NMOS differential amplifier as input stage) under cumulative radiation effects. This investigation is performed through Spice simulations, by injecting typical radiation-induced shifts in the threshold voltage of the transistors for the considered technology, a 0.5 µm standard CMOS process. Transient and DC (Direct Current) analysis are performed in differential and inverter stages of a simple two-stage operational amplifier. The linearity and voltage swing of both amplifier stages are evaluated, as well as, the effects on the bias current and the output offset voltage. Simulation results show that the NMOS differential amplifier architecture may have an improved robustness in radiation environments, if compared to its PMOS counterpart, when considering the typical behavior of MOS transistors under radiation.
{"title":"Impact of TID-induced threshold deviations in analog building-blocks of operational amplifiers","authors":"G. Cardoso, T. Balen, M. Lubaszewski, R. G. Vaz, O. Gonçalez","doi":"10.1109/LATW.2012.6261255","DOIUrl":"https://doi.org/10.1109/LATW.2012.6261255","url":null,"abstract":"This paper presents an investigation on the performance of analog building-blocks of two counterpart architectures of Operational Amplifiers (with PMOS and NMOS differential amplifier as input stage) under cumulative radiation effects. This investigation is performed through Spice simulations, by injecting typical radiation-induced shifts in the threshold voltage of the transistors for the considered technology, a 0.5 µm standard CMOS process. Transient and DC (Direct Current) analysis are performed in differential and inverter stages of a simple two-stage operational amplifier. The linearity and voltage swing of both amplifier stages are evaluated, as well as, the effects on the bias current and the output offset voltage. Simulation results show that the NMOS differential amplifier architecture may have an improved robustness in radiation environments, if compared to its PMOS counterpart, when considering the typical behavior of MOS transistors under radiation.","PeriodicalId":173735,"journal":{"name":"2012 13th Latin American Test Workshop (LATW)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132571304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-10DOI: 10.1109/LATW.2012.6261248
Manuel J. Barragan Asian, G. Léger, J. Huertas
This work proposes a generic path to improve Alternate Test strategies. It demonstrates that multi-condition test increases the amount of information present in the test data and consequently decreases the prediction error of the trained models. The ambition of this paper is to be a methodological contribution to the field of AMS-RF test, and formal guidelines are provided that justify the interest of the approach. For the sake of validation, the proposed methodology has been applied to several alternate test strategies for analog, mixed signal, and RF circuits. Promising results are found for the following case studies: an analog filter, a ΣΔ A/D converter, and an RF LNA.
这项工作提出了一个改进备用测试策略的通用路径。结果表明，多条件测试增加了测试数据中的信息量，从而降低了训练模型的预测误差。本文的目标是对AMS-RF测试领域做出方法学上的贡献，并提供了正式的指导方针来证明该方法的价值。为了验证，所提出的方法已应用于模拟，混合信号和射频电路的几种替代测试策略。在以下案例研究中发现了有希望的结果:模拟滤波器，ΣΔ a /D转换器和RF LNA。
{"title":"Multi-condition alternate test of analog, mixed-signal, and RF systems","authors":"Manuel J. Barragan Asian, G. Léger, J. Huertas","doi":"10.1109/LATW.2012.6261248","DOIUrl":"https://doi.org/10.1109/LATW.2012.6261248","url":null,"abstract":"This work proposes a generic path to improve Alternate Test strategies. It demonstrates that multi-condition test increases the amount of information present in the test data and consequently decreases the prediction error of the trained models. The ambition of this paper is to be a methodological contribution to the field of AMS-RF test, and formal guidelines are provided that justify the interest of the approach. For the sake of validation, the proposed methodology has been applied to several alternate test strategies for analog, mixed signal, and RF circuits. Promising results are found for the following case studies: an analog filter, a ΣΔ A/D converter, and an RF LNA.","PeriodicalId":173735,"journal":{"name":"2012 13th Latin American Test Workshop (LATW)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131409612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-10DOI: 10.1109/LATW.2012.6261246
Lars Schor, Iuliana Bacivarov, Hoeseok Yang, L. Thiele
The reliability of multi-core systems is nowadays threatened by high chip temperatures leading to long-term reliability concerns and short-term functional errors. In real-time systems, high chip temperatures are even adherent to potential deadline violations. Therefore, correct functionality can only be guaranteed if the worst-case peak temperature is incorporated in real-time analysis. However, calculating the peak temperature of hundreds of design alternatives during design space exploration is time-consuming. In this paper, we address this challenge and present a fast analytic method to calculate a non-trivial upper bound on the maximum temperature of a multi-core real-time system with non-deterministic workload. The considered thermal model is able to address various thermal effects like heat exchange between neighboring cores and temperature-dependent leakage power. Finally, the proposed method is applied to a multi-core ARM platform to validate its efficiency and accuracy.
{"title":"Fast worst-case peak temperature evaluation for real-time applications on multi-core systems","authors":"Lars Schor, Iuliana Bacivarov, Hoeseok Yang, L. Thiele","doi":"10.1109/LATW.2012.6261246","DOIUrl":"https://doi.org/10.1109/LATW.2012.6261246","url":null,"abstract":"The reliability of multi-core systems is nowadays threatened by high chip temperatures leading to long-term reliability concerns and short-term functional errors. In real-time systems, high chip temperatures are even adherent to potential deadline violations. Therefore, correct functionality can only be guaranteed if the worst-case peak temperature is incorporated in real-time analysis. However, calculating the peak temperature of hundreds of design alternatives during design space exploration is time-consuming. In this paper, we address this challenge and present a fast analytic method to calculate a non-trivial upper bound on the maximum temperature of a multi-core real-time system with non-deterministic workload. The considered thermal model is able to address various thermal effects like heat exchange between neighboring cores and temperature-dependent leakage power. Finally, the proposed method is applied to a multi-core ARM platform to validate its efficiency and accuracy.","PeriodicalId":173735,"journal":{"name":"2012 13th Latin American Test Workshop (LATW)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125730525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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