Pub Date : 2015-04-02DOI: 10.1109/ICCSP.2015.7322719
M. J. Sataraddi, M. Kakkasageri
Wireless sensor network consists of spatially distributed autonomous devices using sensors to monitor various conditions. There are many issues concerned with wireless sensor networks, namely routing to save energy, fault tolerance, production cost, scalability, data aggregation, security and quality of service. Since the network life time depends on power consumption, energy is considered as an important issue. The proposed work aims at overcoming the energy issue by finding the faulty nodes and choosing the probability based optimal path between source and sink. Based on Bayesian rule of probability, joint probability is calculated at each node by considering the parameters like distance between nodes, bandwidth and energy. Path is selected by considering the nodes which are having more energy, large bandwidth and less distance. To test the performance effectiveness of the scheme, we have analyzed the performance parameters like node deployment, throughput and latency.
{"title":"Energy efficient path identification in wireless sensor networks","authors":"M. J. Sataraddi, M. Kakkasageri","doi":"10.1109/ICCSP.2015.7322719","DOIUrl":"https://doi.org/10.1109/ICCSP.2015.7322719","url":null,"abstract":"Wireless sensor network consists of spatially distributed autonomous devices using sensors to monitor various conditions. There are many issues concerned with wireless sensor networks, namely routing to save energy, fault tolerance, production cost, scalability, data aggregation, security and quality of service. Since the network life time depends on power consumption, energy is considered as an important issue. The proposed work aims at overcoming the energy issue by finding the faulty nodes and choosing the probability based optimal path between source and sink. Based on Bayesian rule of probability, joint probability is calculated at each node by considering the parameters like distance between nodes, bandwidth and energy. Path is selected by considering the nodes which are having more energy, large bandwidth and less distance. To test the performance effectiveness of the scheme, we have analyzed the performance parameters like node deployment, throughput and latency.","PeriodicalId":174192,"journal":{"name":"2015 International Conference on Communications and Signal Processing (ICCSP)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127145495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-02DOI: 10.1109/ICCSP.2015.7322680
Emy Mariam George, Komal Punia, K. Vinoth Babu, G. Ramachandra Reddy
Present wireless technologies demand high quality broadband services even at cell edges. Multi-hop relay (MHR) network is one of the suitable solutions for the above demands. The standards like IEEE 802.16j and Long Term Evolution (LTE) are using relay architecture which mainly focuses on capacity and coverage improvement. In recent days, multi antenna MHR networks are becoming more popular. However obtaining accurate channel state information (CSI) has become a crucial issue in MHR network performance. In this paper, we analyze the effect of delayed CSI at the transmitter (CSIT) in a system with N transmit antennas and one receive antenna, which uses antenna selection (AS). Assuming perfect CSI at the receiver (CSIR), only two out of the N transmit antennas is selected by the receiver and the indices for the same are fed back to the transmitter over a noiseless link with some finite delay. Thus this paper studied the reduced multiple input single output (MISO) systems for MHR networks which perform well even with delayed CSIT. The simulation results also validate the same.
{"title":"Performance analysis of multi-antenna multi-hop relay networks using antenna selection with delayed channel state information at the transmitter","authors":"Emy Mariam George, Komal Punia, K. Vinoth Babu, G. Ramachandra Reddy","doi":"10.1109/ICCSP.2015.7322680","DOIUrl":"https://doi.org/10.1109/ICCSP.2015.7322680","url":null,"abstract":"Present wireless technologies demand high quality broadband services even at cell edges. Multi-hop relay (MHR) network is one of the suitable solutions for the above demands. The standards like IEEE 802.16j and Long Term Evolution (LTE) are using relay architecture which mainly focuses on capacity and coverage improvement. In recent days, multi antenna MHR networks are becoming more popular. However obtaining accurate channel state information (CSI) has become a crucial issue in MHR network performance. In this paper, we analyze the effect of delayed CSI at the transmitter (CSIT) in a system with N transmit antennas and one receive antenna, which uses antenna selection (AS). Assuming perfect CSI at the receiver (CSIR), only two out of the N transmit antennas is selected by the receiver and the indices for the same are fed back to the transmitter over a noiseless link with some finite delay. Thus this paper studied the reduced multiple input single output (MISO) systems for MHR networks which perform well even with delayed CSIT. The simulation results also validate the same.","PeriodicalId":174192,"journal":{"name":"2015 International Conference on Communications and Signal Processing (ICCSP)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127164553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-02DOI: 10.1109/ICCSP.2015.7322763
R. Narmadha, S. Malarkkan
To deal with the increasing demand for heterogeneity, a new authentication protocol have been proposed to increase the efficiency of interworking wireless security; they enable mutual authentication among users in inter and intra domain networks. However, to expand inequitable distribution of heterogeneous networks, an intruder may impersonate a legitimate user's signal. Therefore, a secure legitimate user detection method that can distinguish an allowed user's gesture from an attacker's gesture is needed. To generate a trust relationship between user, base station and home network, a novel approach for authenticating protocol which kowtow heterogeneity requirements. It integrates cryptographic credentials, public/private key of base station, random number challenges to facilitate user detection in the presence of intruders. The random number serves as an association, to enable a home network to verify equivalent certificate carried by the base station per user's request. A key involvement in this paper is a new physical layer authentication technique that enables the base station authentication signals from its associated users.
{"title":"Random number based authentication for heterogeneous networks","authors":"R. Narmadha, S. Malarkkan","doi":"10.1109/ICCSP.2015.7322763","DOIUrl":"https://doi.org/10.1109/ICCSP.2015.7322763","url":null,"abstract":"To deal with the increasing demand for heterogeneity, a new authentication protocol have been proposed to increase the efficiency of interworking wireless security; they enable mutual authentication among users in inter and intra domain networks. However, to expand inequitable distribution of heterogeneous networks, an intruder may impersonate a legitimate user's signal. Therefore, a secure legitimate user detection method that can distinguish an allowed user's gesture from an attacker's gesture is needed. To generate a trust relationship between user, base station and home network, a novel approach for authenticating protocol which kowtow heterogeneity requirements. It integrates cryptographic credentials, public/private key of base station, random number challenges to facilitate user detection in the presence of intruders. The random number serves as an association, to enable a home network to verify equivalent certificate carried by the base station per user's request. A key involvement in this paper is a new physical layer authentication technique that enables the base station authentication signals from its associated users.","PeriodicalId":174192,"journal":{"name":"2015 International Conference on Communications and Signal Processing (ICCSP)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127250376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-02DOI: 10.1109/ICCSP.2015.7322898
P. A. Raju, Nishant Kumar, S. Behera
An ultra-wideband (UWB) planar microstrip antenna integrated with a narrow-band cylindrical dielectric resonator antenna (DRA) is presented for cognitive radio applications. The proposed antenna is a combination of semicircular-semi hexagon shape microstrip patch, which is fed by coplanar waveguide (CPW). The dielectric resonator antenna (DRA) is cylindrical in shape excited by a microstrip slot fed on the rear side which shows a narrow band (NB) characteristics. The microstrip antenna provides a wide bandwidth operates from 2.58 GHz to 14 GHz. The DRA provides a narrow bandwidth operates from 10.07 GHz to 11.38 GHz. The UWB antenna is used for sensing the spectrum and the narrow-band DRA used for communication operation. A very good isolation between the two antenna ports (S21 less than -15 dB) are also achieved. Compared to the existing designs the peak gain of the antenna is highly increased around 6.15 dB.
{"title":"Semi circular -semi hexagon microstrip antenna integrated with DRA for cognitive radio applications","authors":"P. A. Raju, Nishant Kumar, S. Behera","doi":"10.1109/ICCSP.2015.7322898","DOIUrl":"https://doi.org/10.1109/ICCSP.2015.7322898","url":null,"abstract":"An ultra-wideband (UWB) planar microstrip antenna integrated with a narrow-band cylindrical dielectric resonator antenna (DRA) is presented for cognitive radio applications. The proposed antenna is a combination of semicircular-semi hexagon shape microstrip patch, which is fed by coplanar waveguide (CPW). The dielectric resonator antenna (DRA) is cylindrical in shape excited by a microstrip slot fed on the rear side which shows a narrow band (NB) characteristics. The microstrip antenna provides a wide bandwidth operates from 2.58 GHz to 14 GHz. The DRA provides a narrow bandwidth operates from 10.07 GHz to 11.38 GHz. The UWB antenna is used for sensing the spectrum and the narrow-band DRA used for communication operation. A very good isolation between the two antenna ports (S21 less than -15 dB) are also achieved. Compared to the existing designs the peak gain of the antenna is highly increased around 6.15 dB.","PeriodicalId":174192,"journal":{"name":"2015 International Conference on Communications and Signal Processing (ICCSP)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129069980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-02DOI: 10.1109/ICCSP.2015.7322910
Nishant Kumar, P. A. Raju, S. Behera
This paper presents a selective frequency reconfigurable antenna, suitable for cognitive radio applications. Reconfigurability is achieved by inserting PIN diode switches in DMS(defected microstrip structure) `T' slot filter. The proposed antenna is capable of switching between a wide operating band of 3.0 GHz - 10 GHz and six different narrow band operating from 5 GHz to 10 GHz. UWB case is used for sensing the entire band and then adjusting its bandwidth to select the suitable sub-band and pre-filter out the other ones to communicate with wireless devices without interference with others. The proposed antenna patch is a combination of two semi-circular patches. For each case reflection coefficient is calculated, it maintains less than -10 dB throughout the operating frequency. Radiation Patterns for each case also reveal a very low distortion as required. Gain is more than 70% in each case.
{"title":"Frequency reconfigurable microstrip antenna for cognitive radio applications","authors":"Nishant Kumar, P. A. Raju, S. Behera","doi":"10.1109/ICCSP.2015.7322910","DOIUrl":"https://doi.org/10.1109/ICCSP.2015.7322910","url":null,"abstract":"This paper presents a selective frequency reconfigurable antenna, suitable for cognitive radio applications. Reconfigurability is achieved by inserting PIN diode switches in DMS(defected microstrip structure) `T' slot filter. The proposed antenna is capable of switching between a wide operating band of 3.0 GHz - 10 GHz and six different narrow band operating from 5 GHz to 10 GHz. UWB case is used for sensing the entire band and then adjusting its bandwidth to select the suitable sub-band and pre-filter out the other ones to communicate with wireless devices without interference with others. The proposed antenna patch is a combination of two semi-circular patches. For each case reflection coefficient is calculated, it maintains less than -10 dB throughout the operating frequency. Radiation Patterns for each case also reveal a very low distortion as required. Gain is more than 70% in each case.","PeriodicalId":174192,"journal":{"name":"2015 International Conference on Communications and Signal Processing (ICCSP)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129091096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-02DOI: 10.1109/ICCSP.2015.7322741
Prathibha Peddireddy, Usha Kiran K, Chhavi Kush
RF-MEMS filters will substitute conventional filters as they offer better performance at optimum cost. A bandpass filter is one such filter which is designed using microelectro-mechanical systems (MEMS) technology which have low insertion loss, high quality factors, good temperature stability and have various unique advantages. This paper reports on the implementation of wide bandpass filter using a silicon based integrated passive device technology. The wide bandpass filter is realized on a micromachined (MEMS) silicon substrate. The filter occupies only 1mm x 0.56mm die area and the band pass is achieved using spiral inductors and a gap capacitor. The wide band pass filter is designed using a coplanar wave guide transmission line which is placed on a silicon substrate operating over K-band to W-band. This design is implemented in High Frequency Structural Simulator (HFSS) software. The simulated results shows that the design has the return loss of -14.7dB and insertion loss of -1.02dB. A wide bandwidth of 74GHz has been achieved.
RF-MEMS滤波器将取代传统滤波器，因为它们以最佳的成本提供更好的性能。带通滤波器是一种采用微机电系统(MEMS)技术设计的滤波器，具有插入损耗低、质量因数高、温度稳定性好等诸多独特优点。本文报道了利用硅基集成无源器件技术实现宽带通滤波器。宽带通滤波器是在微机械(MEMS)硅衬底上实现的。该滤波器仅占用1mm x 0.56mm的芯片面积，带通是使用螺旋电感和间隙电容实现的。宽带通滤波器的设计使用了一根放置在硅衬底上的共面波导传输线，该传输线在k波段到w波段之间工作。本设计在高频结构模拟器(HFSS)软件中实现。仿真结果表明，该设计回波损耗为-14.7dB，插入损耗为-1.02dB。实现了74GHz的宽带带宽。
{"title":"Micromachined wide bandpass filter","authors":"Prathibha Peddireddy, Usha Kiran K, Chhavi Kush","doi":"10.1109/ICCSP.2015.7322741","DOIUrl":"https://doi.org/10.1109/ICCSP.2015.7322741","url":null,"abstract":"RF-MEMS filters will substitute conventional filters as they offer better performance at optimum cost. A bandpass filter is one such filter which is designed using microelectro-mechanical systems (MEMS) technology which have low insertion loss, high quality factors, good temperature stability and have various unique advantages. This paper reports on the implementation of wide bandpass filter using a silicon based integrated passive device technology. The wide bandpass filter is realized on a micromachined (MEMS) silicon substrate. The filter occupies only 1mm x 0.56mm die area and the band pass is achieved using spiral inductors and a gap capacitor. The wide band pass filter is designed using a coplanar wave guide transmission line which is placed on a silicon substrate operating over K-band to W-band. This design is implemented in High Frequency Structural Simulator (HFSS) software. The simulated results shows that the design has the return loss of -14.7dB and insertion loss of -1.02dB. A wide bandwidth of 74GHz has been achieved.","PeriodicalId":174192,"journal":{"name":"2015 International Conference on Communications and Signal Processing (ICCSP)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130515299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-02DOI: 10.1109/ICCSP.2015.7322646
A. Bhagat, S. Hajare, P. Dakhole
Squaring circuits are among the fundamental components of digital system and hence power consumption, speed and area are prime concern. Today every circuit has to face many power consumption issue portable devices and its application such computer application aiming at large battery life and reliability that are too complex. Larger design requires more area and consumes more power. As for getting all these requirements, radix-4 squaring operation implemented by multiplier followed by truncation circuit. The theory of operation of circuit is described including radix-4 operand dual recoding. Dual recoding reward non negative partial squares and other features which simplify the design of approximate squaring circuit. Clearly the approach described in this work allows for improvement in various applications. Results of design on Tanner Tool in terms of delay, power and area in 180nm technology are presented and analyzed with conventional multiplier. The radix-4 approximate squaring circuit is shown to be efficient than a radix-2 state of art binary squaring circuit.
{"title":"Design of radix-4 squaring circuit using dual recoding technique","authors":"A. Bhagat, S. Hajare, P. Dakhole","doi":"10.1109/ICCSP.2015.7322646","DOIUrl":"https://doi.org/10.1109/ICCSP.2015.7322646","url":null,"abstract":"Squaring circuits are among the fundamental components of digital system and hence power consumption, speed and area are prime concern. Today every circuit has to face many power consumption issue portable devices and its application such computer application aiming at large battery life and reliability that are too complex. Larger design requires more area and consumes more power. As for getting all these requirements, radix-4 squaring operation implemented by multiplier followed by truncation circuit. The theory of operation of circuit is described including radix-4 operand dual recoding. Dual recoding reward non negative partial squares and other features which simplify the design of approximate squaring circuit. Clearly the approach described in this work allows for improvement in various applications. Results of design on Tanner Tool in terms of delay, power and area in 180nm technology are presented and analyzed with conventional multiplier. The radix-4 approximate squaring circuit is shown to be efficient than a radix-2 state of art binary squaring circuit.","PeriodicalId":174192,"journal":{"name":"2015 International Conference on Communications and Signal Processing (ICCSP)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132506014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-02DOI: 10.1109/ICCSP.2015.7322860
M. V. Divya Prabha, P. Seema
Design considerations of a zero voltage switching forward AC-DC PFC (Power Factor Correction) converter are presented here .The converter can achieve high PF in the entire universal input range. The forward converter topology also ensures that isolation of input is achieved and a novel single stage power factor correction circuit is realized. The converter is forced to operate in critical conduction mode (CRM) with the help of an improved constant on-time control. To confirm the validity of the proposed converter, simulations have been done using MATLAB/SIMULINK and are presented here.
{"title":"Design considerations of a ZVS forward AC-DC PFC converter with an improved constant on-time control","authors":"M. V. Divya Prabha, P. Seema","doi":"10.1109/ICCSP.2015.7322860","DOIUrl":"https://doi.org/10.1109/ICCSP.2015.7322860","url":null,"abstract":"Design considerations of a zero voltage switching forward AC-DC PFC (Power Factor Correction) converter are presented here .The converter can achieve high PF in the entire universal input range. The forward converter topology also ensures that isolation of input is achieved and a novel single stage power factor correction circuit is realized. The converter is forced to operate in critical conduction mode (CRM) with the help of an improved constant on-time control. To confirm the validity of the proposed converter, simulations have been done using MATLAB/SIMULINK and are presented here.","PeriodicalId":174192,"journal":{"name":"2015 International Conference on Communications and Signal Processing (ICCSP)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132052506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-02DOI: 10.1109/ICCSP.2015.7322862
V. Saminadan, P. Aishwarya, M. Manimegalai, M. Nivedhitha, G. Subhapriya
Images of outdoor scenes are usually degraded under bad weather conditions, which results in a hazy image. In this paper, two image priors, called the pixel-based dark channel prior and the pixel-based bright channel prior are used to remove haze from a hazy image. Based on the two priors with the haze imaging model, the atmospheric light is estimated via haze density analysis followed by finding the transmission map. Since the transmission map suffers from halos and block artifacts, we refine it via guided filter. The output of a guided filter is a linear transform of the guidance image. Guidance image can be the input image itself or another different image. In our case Guidance image is hazy image.
{"title":"Efficient image dehazing based on pixel based dark channel prior and guided filter","authors":"V. Saminadan, P. Aishwarya, M. Manimegalai, M. Nivedhitha, G. Subhapriya","doi":"10.1109/ICCSP.2015.7322862","DOIUrl":"https://doi.org/10.1109/ICCSP.2015.7322862","url":null,"abstract":"Images of outdoor scenes are usually degraded under bad weather conditions, which results in a hazy image. In this paper, two image priors, called the pixel-based dark channel prior and the pixel-based bright channel prior are used to remove haze from a hazy image. Based on the two priors with the haze imaging model, the atmospheric light is estimated via haze density analysis followed by finding the transmission map. Since the transmission map suffers from halos and block artifacts, we refine it via guided filter. The output of a guided filter is a linear transform of the guidance image. Guidance image can be the input image itself or another different image. In our case Guidance image is hazy image.","PeriodicalId":174192,"journal":{"name":"2015 International Conference on Communications and Signal Processing (ICCSP)","volume":"23 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130863937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-02DOI: 10.1109/ICCSP.2015.7322899
T. Reddy, B. Madhavi, K. Kishore
Research on run time reconfiguration of FPGAs has been in academia for more than two decades, attempting to derive more benefits for FPGA based designs. The Dynamic Partial Reconfiguration (DPR) with runtime partial bit file loading capability was found to be more useful for designing flexible hardware. Majority of researchers found the limitations with DPR approach, due to higher configuration time. The research presented here proposes a dual configuration memory approach, which can increase the scope of DPR to several categories of applications. A novel dual reconfiguration memory based approach is proposed for efficient block based processing. The proposed architecture is analysed in the context of Frequency Shift Keying (FSK) demodulator architecture. The FSK demodulator functionality is achieved with 7 stages, where each stage configured as reconfigurable block. The memory controller and data pre processing blocks are used to preserve the context across each partial reconfiguration cycle. The proposed architecture matches the block processing time with partial reconfiguration time, so that the maximum throughput is achieved. Analysis results show that under given circumstances 91% rise in throughput is possible with dual reconfigurable memory approach. The improved dynamic partial reconfiguration shall enable realizing several signal processing algorithms on FPGAs, while occupying less area.
{"title":"Improved block based processing with dual partial reconfiguration memory approach","authors":"T. Reddy, B. Madhavi, K. Kishore","doi":"10.1109/ICCSP.2015.7322899","DOIUrl":"https://doi.org/10.1109/ICCSP.2015.7322899","url":null,"abstract":"Research on run time reconfiguration of FPGAs has been in academia for more than two decades, attempting to derive more benefits for FPGA based designs. The Dynamic Partial Reconfiguration (DPR) with runtime partial bit file loading capability was found to be more useful for designing flexible hardware. Majority of researchers found the limitations with DPR approach, due to higher configuration time. The research presented here proposes a dual configuration memory approach, which can increase the scope of DPR to several categories of applications. A novel dual reconfiguration memory based approach is proposed for efficient block based processing. The proposed architecture is analysed in the context of Frequency Shift Keying (FSK) demodulator architecture. The FSK demodulator functionality is achieved with 7 stages, where each stage configured as reconfigurable block. The memory controller and data pre processing blocks are used to preserve the context across each partial reconfiguration cycle. The proposed architecture matches the block processing time with partial reconfiguration time, so that the maximum throughput is achieved. Analysis results show that under given circumstances 91% rise in throughput is possible with dual reconfigurable memory approach. The improved dynamic partial reconfiguration shall enable realizing several signal processing algorithms on FPGAs, while occupying less area.","PeriodicalId":174192,"journal":{"name":"2015 International Conference on Communications and Signal Processing (ICCSP)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125430258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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