Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694432
M. Kanamura, T. Ohki, S. Ozaki, M. Nishimori, S. Tomabechi, J. Kotani, T. Miyajima, N. Nakamura, N. Okamoto, T. Kikkawa, K. Watanabe
In this paper, we present a method of reducing threshold voltage shift for normally-off GaN MIS-HEMT by the optimization of dielectric deposition conditions. High-temperature deposition of Al2O3 insulator decreases the impurities in a dielectric film, leading to small C-V and I-V hysteresis under large positive gate voltage operation. Moreover, Al2O3 deposited at high temperature achieve high quality interface and bulk without post deposition annealing (PDA), preventing the degradation of electrodes and crystallization of insulator film. The fabricated device shows small C-V and I-V hysteresis, with a breakdown voltage of greater than 600 V.
{"title":"Suppression of threshold voltage shift for normally-Off GaN MIS-HEMT without post deposition annealing","authors":"M. Kanamura, T. Ohki, S. Ozaki, M. Nishimori, S. Tomabechi, J. Kotani, T. Miyajima, N. Nakamura, N. Okamoto, T. Kikkawa, K. Watanabe","doi":"10.1109/ISPSD.2013.6694432","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694432","url":null,"abstract":"In this paper, we present a method of reducing threshold voltage shift for normally-off GaN MIS-HEMT by the optimization of dielectric deposition conditions. High-temperature deposition of Al2O3 insulator decreases the impurities in a dielectric film, leading to small C-V and I-V hysteresis under large positive gate voltage operation. Moreover, Al2O3 deposited at high temperature achieve high quality interface and bulk without post deposition annealing (PDA), preventing the degradation of electrodes and crystallization of insulator film. The fabricated device shows small C-V and I-V hysteresis, with a breakdown voltage of greater than 600 V.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"C-17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126761117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694453
Kwangsik Ko, Sanghyun Lee, Dea-Hoon Kim, Jina Eum, Sung-Kun Park, I. Cho, Jong-Hwan Kim, K. Yoo
In this work, we developed a HB1340-0.13um BCD technology of the complimentary LDMOS including fully isolated structure device with dual drift layer. We could achieve LDMOS with best-in-class trade-off between specific on-resistance and breakdown voltage by its optimized drain engineering. The HB1340 process in 0.13um 1.5V/5V/6V CMOS technology platform can provide various kinds of high voltage devices such as LDMOS, DEMOS from 12V to 40V and fully isolated 24V LDNMOS for mobile and display power application. High gain BJT, Zener diode, high voltage diode, high resistor, MIM and EEPROM are also have been integrated in smart power technology.
{"title":"HB1340 ℄ Advanced 0.13um BCDMOS technology of complimentary LDMOS including fully isolated transistors","authors":"Kwangsik Ko, Sanghyun Lee, Dea-Hoon Kim, Jina Eum, Sung-Kun Park, I. Cho, Jong-Hwan Kim, K. Yoo","doi":"10.1109/ISPSD.2013.6694453","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694453","url":null,"abstract":"In this work, we developed a HB1340-0.13um BCD technology of the complimentary LDMOS including fully isolated structure device with dual drift layer. We could achieve LDMOS with best-in-class trade-off between specific on-resistance and breakdown voltage by its optimized drain engineering. The HB1340 process in 0.13um 1.5V/5V/6V CMOS technology platform can provide various kinds of high voltage devices such as LDMOS, DEMOS from 12V to 40V and fully isolated 24V LDNMOS for mobile and display power application. High gain BJT, Zener diode, high voltage diode, high resistor, MIM and EEPROM are also have been integrated in smart power technology.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114499928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694446
Yun Shi, Santosh K. Sharma, M. Zierak, R. Phelps, D. Cook, T. Letavic
In this paper, we discuss the fundamental design tradeoff among specific on-resistance (Ron, sp), gate charge (Cgg), quasi-saturation, and reliability characteristics for an integrated high voltage LDMOS. A novel patterned gate design is proposed and implemented in a 120V-rated NLDMOS. Optimal design characteristics are demonstrated with 30% improvement in switching FOM (Ron, sp*Qgg) and a robust Id, lin shift passing 15 years lifetime specification. The new design technique is proven to significantly improve the high voltage LDMOS design tradeoff.
{"title":"Novel high voltage LDMOS using a variable fermi-potential field plate for best switching FOM and reliability tradeoff","authors":"Yun Shi, Santosh K. Sharma, M. Zierak, R. Phelps, D. Cook, T. Letavic","doi":"10.1109/ISPSD.2013.6694446","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694446","url":null,"abstract":"In this paper, we discuss the fundamental design tradeoff among specific on-resistance (Ron, sp), gate charge (Cgg), quasi-saturation, and reliability characteristics for an integrated high voltage LDMOS. A novel patterned gate design is proposed and implemented in a 120V-rated NLDMOS. Optimal design characteristics are demonstrated with 30% improvement in switching FOM (Ron, sp*Qgg) and a robust Id, lin shift passing 15 years lifetime specification. The new design technique is proven to significantly improve the high voltage LDMOS design tradeoff.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123586589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694433
Ki-Sik Im, Y. Jo, Ki‐Won Kim, Dong‐Seok Kim, Hee-Sung Kang, C. Won, Ryun-Hwi Kim, S. Jeon, D. Son, Y. Kwon, Jae-Hoon Lee, S. Cristoloveanu, Jung-Hee Lee
Heavily doped GaN nanochannel FinFET has been proposed and fabricated, for the first time, which does not have any p-n junction or heterojunction. In spite of its easy and simple epitaxial growth and fabrication process, the fabricated device with nanochannel width of 80 nm and gate length of 1 μm exhibited excellent off-state performances such as extremely low off-state leakage current of ~ 10-11 mA with BV of ~ 300 V and subthreshold slope of 68 mV/decade, very close to the theoretically limited value, which leads to high Ion/Ioff ratio of 107 ~ 109. The device also exhibited high on-state performances such as maximum drain current of 562 mA/mm and maximum transconductance of 138 mS/mm. The proposed nanochannel GaN FinFET can be very promising candidate not only for high performance, but also high power applications.
{"title":"First demonstration of heterojunction-free GaN nanochannel FinFETs","authors":"Ki-Sik Im, Y. Jo, Ki‐Won Kim, Dong‐Seok Kim, Hee-Sung Kang, C. Won, Ryun-Hwi Kim, S. Jeon, D. Son, Y. Kwon, Jae-Hoon Lee, S. Cristoloveanu, Jung-Hee Lee","doi":"10.1109/ISPSD.2013.6694433","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694433","url":null,"abstract":"Heavily doped GaN nanochannel FinFET has been proposed and fabricated, for the first time, which does not have any p-n junction or heterojunction. In spite of its easy and simple epitaxial growth and fabrication process, the fabricated device with nanochannel width of 80 nm and gate length of 1 μm exhibited excellent off-state performances such as extremely low off-state leakage current of ~ 10-11 mA with BV of ~ 300 V and subthreshold slope of 68 mV/decade, very close to the theoretically limited value, which leads to high Ion/Ioff ratio of 107 ~ 109. The device also exhibited high on-state performances such as maximum drain current of 562 mA/mm and maximum transconductance of 138 mS/mm. The proposed nanochannel GaN FinFET can be very promising candidate not only for high performance, but also high power applications.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"07 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129746175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694417
T. Matsudai, T. Ogura, Yuuichi Oshino, T. Naijo, Taichi Kobayashi, K. Nakamura
In this paper, a 1200V novel PiN-diode concept realizing low forward voltage drop (VF), low reverse recovery loss and low leakage current at high temperature over 175°C has been proposed. To realize these above-mentioned characteristics, this concept of 1200V diode design adopts a combination of flat and linear distribution of carrier concentration from anode side to cathode side and reducing injection efficiency at both sides at forward bias condition. This carrier profile can also realize reduction of voltage ringing effectively at reverse condition. Furthermore, we have successfully obtained high reverse recovery ruggedness combining a new edge termination design with Schottky contact.
{"title":"1200V SC(Schottky controlled injection)-diode, an advanced fast recovery concept with high carrier lifetime","authors":"T. Matsudai, T. Ogura, Yuuichi Oshino, T. Naijo, Taichi Kobayashi, K. Nakamura","doi":"10.1109/ISPSD.2013.6694417","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694417","url":null,"abstract":"In this paper, a 1200V novel PiN-diode concept realizing low forward voltage drop (VF), low reverse recovery loss and low leakage current at high temperature over 175°C has been proposed. To realize these above-mentioned characteristics, this concept of 1200V diode design adopts a combination of flat and linear distribution of carrier concentration from anode side to cathode side and reducing injection efficiency at both sides at forward bias condition. This carrier profile can also realize reduction of voltage ringing effectively at reverse condition. Furthermore, we have successfully obtained high reverse recovery ruggedness combining a new edge termination design with Schottky contact.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125290552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694411
W. Ahn, O. Seok, M. Ha, Young-shil Kim, M. Han
Normally-off AlGaN/GaN MOS HEMTs were successfully fabricated and investigated by simple KOH wet etch and rf-sputtered HfO2 as a gate insulator. The proposed KOH wet etch resulted in an adequate recess-depth and smooth etched surface. The gate-recessed HEMT exhibits threshold voltage (Vth) shifts from -3 to 1.5 V after 150 s KOH-wet etch. The breakdown voltage of 1580 V and Ron, sp of 8.09 mΩ·cm2 was measured in the AlGaN/GaN HEMT with the gate-drain distance of 20 μm-long. The high FOM (figure of merit) of 308 MW/cm2 was achieved. Our experimental results indicate that the proposed simple KOH wet etching and rf sputtered HfO2-gate insulator may be promising for the normally-off AlGaN/GaN MOS HEMTs fabrication.
采用简单的KOH湿蚀刻和射频溅射HfO2作为栅绝缘体，成功制备了正常关闭的AlGaN/GaN MOS hemt。建议的KOH湿蚀刻导致了足够的凹槽深度和光滑的蚀刻表面。在KOH-wet蚀刻150 s后，门凹槽HEMT的阈值电压(Vth)从-3到1.5 V变化。在栅极-漏极距离为20 μm的AlGaN/GaN HEMT中，测得击穿电压为1580 V, Ron, sp为8.09 mΩ·cm2。达到了308 MW/cm2的高质量因数(FOM)。我们的实验结果表明，所提出的简单KOH湿法刻蚀和射频溅射hfo2栅极绝缘体有望用于正常关闭AlGaN/GaN MOS hemt的制造。
{"title":"Normally-off AlGaN/GaN MOS-HEMTs by KOH wet etch and rf-sputtered HfO2 gate insulator","authors":"W. Ahn, O. Seok, M. Ha, Young-shil Kim, M. Han","doi":"10.1109/ISPSD.2013.6694411","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694411","url":null,"abstract":"Normally-off AlGaN/GaN MOS HEMTs were successfully fabricated and investigated by simple KOH wet etch and rf-sputtered HfO<sub>2</sub> as a gate insulator. The proposed KOH wet etch resulted in an adequate recess-depth and smooth etched surface. The gate-recessed HEMT exhibits threshold voltage (V<sub>th</sub>) shifts from -3 to 1.5 V after 150 s KOH-wet etch. The breakdown voltage of 1580 V and R<sub>on, sp</sub> of 8.09 mΩ·cm<sup>2</sup> was measured in the AlGaN/GaN HEMT with the gate-drain distance of 20 μm-long. The high FOM (figure of merit) of 308 MW/cm<sup>2</sup> was achieved. Our experimental results indicate that the proposed simple KOH wet etching and rf sputtered HfO<sub>2</sub>-gate insulator may be promising for the normally-off AlGaN/GaN MOS HEMTs fabrication.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125340868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694396
R. Rupp, R. Kern, R. Gerlach
We developed a new backside contact formation process for SiC power devices based on pulsed laser annealing providing an ohmic contact with lower contact resistance and better adhesion properties than contacts formed by conventional rapid thermal annealing. This process does not add any significant thermal budget to the wafer front side and therefore allows a “short thin wafer” process, means completing the wafer front side including the imide process before thinning and backside metallization. By that means both the risk of wafer breakage and substrate contribution to the total device resistance are minimized at the same time. This is clearly shown by comparing 650V SiC Schottky diodes with identical device structure but different total chip thickness (360 vs 110 μm). Besides the advantage in differential resistance also other properties like heat flux through the device (Rth), non destructive surge current density (I2t) and reliability are improved by the SiC thin wafer technology enabled by the laser backside contact annealing.
我们开发了一种基于脉冲激光退火的SiC功率器件背面触点形成新工艺，提供了比传统快速热退火形成的触点具有更低接触电阻和更好粘附性能的欧姆触点。该工艺不会给晶圆正面增加任何显著的热预算，因此允许“短薄晶圆”工艺，这意味着在变薄和背面金属化之前完成晶圆正面，包括亚胺工艺。通过这种方法，晶圆破裂的风险和基板对器件总电阻的贡献同时被最小化。通过比较具有相同器件结构但总芯片厚度(360 vs 110 μm)不同的650V SiC肖特基二极管，可以清楚地表明这一点。除了在差分电阻方面的优势外，通过激光背面接触退火实现的SiC薄晶片技术还提高了其他性能，如通过器件的热流密度(Rth)，非破坏性浪涌电流密度(I2t)和可靠性。
{"title":"Laser backside contact annealing of SiC power devices: A prerequisite for SiC thin wafer technology","authors":"R. Rupp, R. Kern, R. Gerlach","doi":"10.1109/ISPSD.2013.6694396","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694396","url":null,"abstract":"We developed a new backside contact formation process for SiC power devices based on pulsed laser annealing providing an ohmic contact with lower contact resistance and better adhesion properties than contacts formed by conventional rapid thermal annealing. This process does not add any significant thermal budget to the wafer front side and therefore allows a “short thin wafer” process, means completing the wafer front side including the imide process before thinning and backside metallization. By that means both the risk of wafer breakage and substrate contribution to the total device resistance are minimized at the same time. This is clearly shown by comparing 650V SiC Schottky diodes with identical device structure but different total chip thickness (360 vs 110 μm). Besides the advantage in differential resistance also other properties like heat flux through the device (Rth), non destructive surge current density (I2t) and reliability are improved by the SiC thin wafer technology enabled by the laser backside contact annealing.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128790393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694458
D. Pattanayak, O. Tornblad
The small- and large-signal output capacitances of a super junction MOSFET and a conventional power MOSFET are obtained as a function of voltage and compared. The capacitors are charged and discharged by a voltage pulse through an external resistor and the voltage and current across the capacitors are measured as a function of time. The stored charge in the nonlinear output capacitor is shown to be related to the voltage across it in a piecewise nonlinear way as v=aq+bq2 for v<;vlp and v=vlp+c (q-qlp) +d (q-qlp) 2 for v>vlp. The voltage, vlp and the charge, qlp and the constants, a, b, c and d are related to the design of the super junction MOSFET drift region. It is shown experimentally that when the output capacitor associated with the super junction MOSFET is excited by a sinusoidal wave, a large number of harmonics of the fundamental frequency is obtained due to its nonlinearity. The product of the area specific on-resistance and the area specific energy stored in the output capacitor of an advanced super junction MOSFET is shown to be lower than that of a state of the art conventional MOSFET at high voltages.
{"title":"Large-signal and small-signal output capacitances of super junction MOSFETs","authors":"D. Pattanayak, O. Tornblad","doi":"10.1109/ISPSD.2013.6694458","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694458","url":null,"abstract":"The small- and large-signal output capacitances of a super junction MOSFET and a conventional power MOSFET are obtained as a function of voltage and compared. The capacitors are charged and discharged by a voltage pulse through an external resistor and the voltage and current across the capacitors are measured as a function of time. The stored charge in the nonlinear output capacitor is shown to be related to the voltage across it in a piecewise nonlinear way as v=aq+bq2 for v<;vlp and v=vlp+c (q-qlp) +d (q-qlp) 2 for v>vlp. The voltage, vlp and the charge, qlp and the constants, a, b, c and d are related to the design of the super junction MOSFET drift region. It is shown experimentally that when the output capacitor associated with the super junction MOSFET is excited by a sinusoidal wave, a large number of harmonics of the fundamental frequency is obtained due to its nonlinearity. The product of the area specific on-resistance and the area specific energy stored in the output capacitor of an advanced super junction MOSFET is shown to be lower than that of a state of the art conventional MOSFET at high voltages.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130029672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694427
E. Tee, A. Hoelke, S. Pilkington, D. K. Pal, M. Antoniou, F. Udrea, W. A. bin Wan Zainal Abidin, N. L. Yew
A 200V lateral insulated gate bipolar transistor (LIGBT) was successfully developed using lateral superjunction (SJ) in 0.18μm partial silicon on insulator (SOI) HV process. The results presented are based on extensive experimental measurements and numerical simulations. For an n-type lateral SJ LIGBT, the p layer in the SJ drift region helps in achieving uniform electric field distribution. Furthermore, the p-pillar contributes to the on-state current. Furthermore, the p-pillar contributes to sweep out holes during the turn-off process, thus leading to faster removal of plasma. To realize this device, one additional mask layer is required in the X-FAB 0.18μm partial SOI HV process.
{"title":"200V superjunction lateral IGBT fabricated on partial SOI","authors":"E. Tee, A. Hoelke, S. Pilkington, D. K. Pal, M. Antoniou, F. Udrea, W. A. bin Wan Zainal Abidin, N. L. Yew","doi":"10.1109/ISPSD.2013.6694427","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694427","url":null,"abstract":"A 200V lateral insulated gate bipolar transistor (LIGBT) was successfully developed using lateral superjunction (SJ) in 0.18μm partial silicon on insulator (SOI) HV process. The results presented are based on extensive experimental measurements and numerical simulations. For an n-type lateral SJ LIGBT, the p layer in the SJ drift region helps in achieving uniform electric field distribution. Furthermore, the p-pillar contributes to the on-state current. Furthermore, the p-pillar contributes to sweep out holes during the turn-off process, thus leading to faster removal of plasma. To realize this device, one additional mask layer is required in the X-FAB 0.18μm partial SOI HV process.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116752089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694460
B. Boksteen, A. Ferrara, A. Heringa, P. Steeneken, G. Koops, R. Hueting
A mathematical model for optimizing the 2-D potential distribution in the drift region of field-plate (FP)-assisted RESURF devices (Fig. 1) is presented. The proposed model extends earlier work [1-2] by including top-bottom dielectric asymmetry (typical in SOI devices [3]), non-zero field plate potentials VFP and grading of design parameters other than drift region doping. This generally-applicable, TCAD-verified [4], model provides a guideline for optimizing the drain extension in a wide range of FP-assisted RESURF devices.
{"title":"Design optimization of field-plate assisted RESURF devices","authors":"B. Boksteen, A. Ferrara, A. Heringa, P. Steeneken, G. Koops, R. Hueting","doi":"10.1109/ISPSD.2013.6694460","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694460","url":null,"abstract":"A mathematical model for optimizing the 2-D potential distribution in the drift region of field-plate (FP)-assisted RESURF devices (Fig. 1) is presented. The proposed model extends earlier work [1-2] by including top-bottom dielectric asymmetry (typical in SOI devices [3]), non-zero field plate potentials VFP and grading of design parameters other than drift region doping. This generally-applicable, TCAD-verified [4], model provides a guideline for optimizing the drain extension in a wide range of FP-assisted RESURF devices.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116359529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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