Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694448
Fang Jian, Jia Yaoyao, Pian Hua, Li Yuan, Wang Helong, Bo Zhang, L. Zhaoji
A high speed lateral SOI IGBT (BM-LIGBT) with an electronic barrier modulation structure, which was not reported in previous literatures, is proposed in this paper in order to remarkably improve turn-off speed of the SOI LIGBT. Two important mechanisms are realized in this device: one is the electronic barrier modulation for speeding up the device turn off and for providing the same injection efficiency as conventional SOI LIGBT's, the other is the super-junction structure for improving breakdown voltage of devices. Compared with the conventional SOI LIGBT, the proposed device shows that the turn-off time of BM LIGBT is only 27%-39% of a conventional SOI LIGBT under the same breakdown voltage of 600V and on-state current of 100A/cm2. Numerical analysis and experimental results show that the proposed device presents a better trade-off relationship between on-state resistance and turn-off time.
{"title":"A high speed SOI LIGBT with electronic barrier modulation structure","authors":"Fang Jian, Jia Yaoyao, Pian Hua, Li Yuan, Wang Helong, Bo Zhang, L. Zhaoji","doi":"10.1109/ISPSD.2013.6694448","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694448","url":null,"abstract":"A high speed lateral SOI IGBT (BM-LIGBT) with an electronic barrier modulation structure, which was not reported in previous literatures, is proposed in this paper in order to remarkably improve turn-off speed of the SOI LIGBT. Two important mechanisms are realized in this device: one is the electronic barrier modulation for speeding up the device turn off and for providing the same injection efficiency as conventional SOI LIGBT's, the other is the super-junction structure for improving breakdown voltage of devices. Compared with the conventional SOI LIGBT, the proposed device shows that the turn-off time of BM LIGBT is only 27%-39% of a conventional SOI LIGBT under the same breakdown voltage of 600V and on-state current of 100A/cm2. Numerical analysis and experimental results show that the proposed device presents a better trade-off relationship between on-state resistance and turn-off time.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133462757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694452
Jaejune Jang, Jaehyeon Jung, Hoon Chang, Yongdon Kim, Seoin Park, Hyun-Ju Kim, Jaehwan Kim, Sangbae Yi
This paper introduces mobility enhanced 5V CMOS through geometry optimization in 130nm technology for state-of-the-art RSP performance. By realizing <;100> channel direction on (100) wafer with grid-type layout, mobility of both NMOS and PMOS is enhanced in addition to increased effective width. Furthermore even higher mobility is achieved through introduction of biaxial compressive stress from nearby STI islands. As a result, IDSAT and IDLIN increase by 24%/29% for NMOS and 29%/37% for PMOS respectively compared to standard bar-type layout. All of this is obtained without any process change.
{"title":"Mobility enhanced power CMOS","authors":"Jaejune Jang, Jaehyeon Jung, Hoon Chang, Yongdon Kim, Seoin Park, Hyun-Ju Kim, Jaehwan Kim, Sangbae Yi","doi":"10.1109/ISPSD.2013.6694452","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694452","url":null,"abstract":"This paper introduces mobility enhanced 5V CMOS through geometry optimization in 130nm technology for state-of-the-art RSP performance. By realizing <;100> channel direction on (100) wafer with grid-type layout, mobility of both NMOS and PMOS is enhanced in addition to increased effective width. Furthermore even higher mobility is achieved through introduction of biaxial compressive stress from nearby STI islands. As a result, IDSAT and IDLIN increase by 24%/29% for NMOS and 29%/37% for PMOS respectively compared to standard bar-type layout. All of this is obtained without any process change.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134018233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694465
Liang Yan, G. Koops, P. Steeneken, A. Heringa, R. Surdeanu, L. van Dijk
Silicon on insulator (SOI) technology for power devices offers many distinct advantages compared to bulk Si technology, however in high power applications the buried oxide (BOX) layer can impede heat transport towards the backside of the silicon substrate. This paper demonstrates integration of heat sinks in SOI power devices to improve thermal performance. The heat sinks are formed by polysilicon plugs through the BOX layer that significantly reduce thermal resistance and thus increase the safe operating limits of the technology. The effectiveness of the integrated heat sinks was evaluated by the experimental AC conductance method and by thermal finite element modeling. The integrated heat sinks are shown to reduce the thermal resistance by 15%, improving both thermal and electrical performance of the SOI transistors.
{"title":"Integrated heat sinks for SOI power devices","authors":"Liang Yan, G. Koops, P. Steeneken, A. Heringa, R. Surdeanu, L. van Dijk","doi":"10.1109/ISPSD.2013.6694465","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694465","url":null,"abstract":"Silicon on insulator (SOI) technology for power devices offers many distinct advantages compared to bulk Si technology, however in high power applications the buried oxide (BOX) layer can impede heat transport towards the backside of the silicon substrate. This paper demonstrates integration of heat sinks in SOI power devices to improve thermal performance. The heat sinks are formed by polysilicon plugs through the BOX layer that significantly reduce thermal resistance and thus increase the safe operating limits of the technology. The effectiveness of the integrated heat sinks was evaluated by the experimental AC conductance method and by thermal finite element modeling. The integrated heat sinks are shown to reduce the thermal resistance by 15%, improving both thermal and electrical performance of the SOI transistors.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134396774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694422
R. Roggero, G. Croce, P. Gattari, E. Castellana, A. Molfese, G. Marchesi, L. Atzeni, C. Buran, A. Paleari, G. Ballarin, S. Manzini, F. Alagi, G. Pizzo
Advanced 0.16 μm BCD technology platform offering dense logic transistors (1.8 V-5 V CMOS) and high performance analog features has been developed. Thanks to dedicated field plate optimization, body and drain engineering, state of the art power devices (8 V to 42 V rated) have been obtained ensuring large Safe Operating Areas with best RONXAREA-BVDSS tradeoff.
开发了先进的0.16 μm BCD技术平台，提供密集逻辑晶体管(1.8 V-5 V CMOS)和高性能模拟功能。得益于专门的现场极板优化、阀体和漏极工程，获得了最先进的功率器件(额定8 V至42 V)，确保了具有最佳RONXAREA-BVDSS权衡的大安全操作区域。
{"title":"BCD8sP: An advanced 0.16 μm technology platform with state of the art power devices","authors":"R. Roggero, G. Croce, P. Gattari, E. Castellana, A. Molfese, G. Marchesi, L. Atzeni, C. Buran, A. Paleari, G. Ballarin, S. Manzini, F. Alagi, G. Pizzo","doi":"10.1109/ISPSD.2013.6694422","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694422","url":null,"abstract":"Advanced 0.16 μm BCD technology platform offering dense logic transistors (1.8 V-5 V CMOS) and high performance analog features has been developed. Thanks to dedicated field plate optimization, body and drain engineering, state of the art power devices (8 V to 42 V rated) have been obtained ensuring large Safe Operating Areas with best RONXAREA-BVDSS tradeoff.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133072078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694469
Masazumi Yamamoto, T. Terashima
This paper discusses the priority issues on the energy infrastructure before and after the Great East Japan Earthquake in Japan. For the issue before the earthquake “Development and implementation of technologies that realizes a co-existence between sustainability and living comfortableness,” seven technologies are explained, such as “Improvement of efficiency in Energy use” including “Improvement of efficiency through the progress of power device technology” as a solution. For the issue after that “Review and improvement of existing technologies to restore confidence in technology,” two items are listed, such as “Review and improvement of Security and Safety of Existing Technology”.
{"title":"Development of secured energy infrastructure in Japan","authors":"Masazumi Yamamoto, T. Terashima","doi":"10.1109/ISPSD.2013.6694469","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694469","url":null,"abstract":"This paper discusses the priority issues on the energy infrastructure before and after the Great East Japan Earthquake in Japan. For the issue before the earthquake “Development and implementation of technologies that realizes a co-existence between sustainability and living comfortableness,” seven technologies are explained, such as “Improvement of efficiency in Energy use” including “Improvement of efficiency through the progress of power device technology” as a solution. For the issue after that “Review and improvement of existing technologies to restore confidence in technology,” two items are listed, such as “Review and improvement of Security and Safety of Existing Technology”.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115541659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694484
Zhongda Li, T. Chow
We have examined the robustness of the novel enhancement-mode GaN vertical superjunction HEMT using numerical simulations, which has been designed previously and projected to have best Ron, sp of 4.2 mQ-cm2 and BV of 12.4kV, and compared it with a GaN vertical HEMT with conventional drift region. The GaN vertical superjunction HEMT with 8 μm pillar width shows 7X higher on-state current level and 1/5 of the Ron, sp compared with The simulated on-state breakdown voltage of the GaN vertical superjunction HEMT structure shows 4.5% drop from the off-state breakdown voltage, and is only slightly higher than the 1.7% drop of the conventional GaN vertical HEMT.
{"title":"Robustness of GaN vertical superjunction HEMT","authors":"Zhongda Li, T. Chow","doi":"10.1109/ISPSD.2013.6694484","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694484","url":null,"abstract":"We have examined the robustness of the novel enhancement-mode GaN vertical superjunction HEMT using numerical simulations, which has been designed previously and projected to have best Ron, sp of 4.2 mQ-cm2 and BV of 12.4kV, and compared it with a GaN vertical HEMT with conventional drift region. The GaN vertical superjunction HEMT with 8 μm pillar width shows 7X higher on-state current level and 1/5 of the Ron, sp compared with The simulated on-state breakdown voltage of the GaN vertical superjunction HEMT structure shows 4.5% drop from the off-state breakdown voltage, and is only slightly higher than the 1.7% drop of the conventional GaN vertical HEMT.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117198414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694416
S. Matthias, S. Geissmann, M. Bellini, A. Kopta, Munaf T. A. Rahimo
Traditionally, the major driver in IGBT and diode development is to minimize the static and dynamic losses. A significant reduction of the n-base thickness would yield this, however it can also jeopardize the switching characteristic leading to high overshoot voltages during diode reverse recovery. In this paper, we present an improved Field-Charge Extraction (FCE) concept that is achieving a soft reverse recovery behavior inherently. The new design allows for a 10% reduction of the thickness of the diode's n-base, while still maintaining the blocking capability and the softness of the conventional diode. Therefore, the technology curve and the ruggedness are improved significantly.
{"title":"Inherently soft free-wheeling diode for high temperature operation","authors":"S. Matthias, S. Geissmann, M. Bellini, A. Kopta, Munaf T. A. Rahimo","doi":"10.1109/ISPSD.2013.6694416","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694416","url":null,"abstract":"Traditionally, the major driver in IGBT and diode development is to minimize the static and dynamic losses. A significant reduction of the n-base thickness would yield this, however it can also jeopardize the switching characteristic leading to high overshoot voltages during diode reverse recovery. In this paper, we present an improved Field-Charge Extraction (FCE) concept that is achieving a soft reverse recovery behavior inherently. The new design allows for a 10% reduction of the thickness of the diode's n-base, while still maintaining the blocking capability and the softness of the conventional diode. Therefore, the technology curve and the ruggedness are improved significantly.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115249178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694404
M. Masunaga, T. Hashimoto, Kouichi Kato, H. Andou, Hideo Numabe, Zen Tomizawa, N. Matsuura
A novel low voltage power MOSFET with a low threshold voltage (Vth) region (sub-MOS) is proposed. The proposed MOSFET has a superior trade-off relationship between output efficiency and switching noise, with a spike voltage 82% lower than a conventional MOSFET and the same efficiency at 300 kHz with an output current of 20 A. Since the proposed device reduces the drain current through rate (dir/dt) by false turn-on of the sub-MOS, it decreases the spike voltage during diode reverse recovery. The false turn-on losses are suppressed by the saturation current of the sub-MOS, which is controlled by optimizing the sub-MOS area and the Vth. The low on-state resistance of sub-MOS compensates for the false turn-on losses to achieve high efficiency.
{"title":"A low noise and low loss power MOSFET with low Vth regions for voltage regulators","authors":"M. Masunaga, T. Hashimoto, Kouichi Kato, H. Andou, Hideo Numabe, Zen Tomizawa, N. Matsuura","doi":"10.1109/ISPSD.2013.6694404","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694404","url":null,"abstract":"A novel low voltage power MOSFET with a low threshold voltage (Vth) region (sub-MOS) is proposed. The proposed MOSFET has a superior trade-off relationship between output efficiency and switching noise, with a spike voltage 82% lower than a conventional MOSFET and the same efficiency at 300 kHz with an output current of 20 A. Since the proposed device reduces the drain current through rate (dir/dt) by false turn-on of the sub-MOS, it decreases the spike voltage during diode reverse recovery. The false turn-on losses are suppressed by the saturation current of the sub-MOS, which is controlled by optimizing the sub-MOS area and the Vth. The low on-state resistance of sub-MOS compensates for the false turn-on losses to achieve high efficiency.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121802194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694481
P. Feng, K. Teo, T. Oishi, K. Yamanaka, R. Ma
We propose the design and simulation study of novel gallium nitride (GaN) devices, consisting of nitride stacks with different polarity, to provide multiple channels by flexible gate(s) control. Calibrated TCAD device simulations visualize device characteristics of 0.62-μm-gate-length multi-channel transistors. E-mode operations demonstrate a positive small threshold voltage Vth below 2 V at Vds = 0.1 V for all multichannel devices, and a high on-state current Ion (Vgs = Vds = 4 V) up to 4 A/mm achieved by 4 channels induced within the device.
{"title":"Design of enhancement mode single-gate and doublegate multi-channel GaN HEMT with vertical polarity inversion heterostructure","authors":"P. Feng, K. Teo, T. Oishi, K. Yamanaka, R. Ma","doi":"10.1109/ISPSD.2013.6694481","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694481","url":null,"abstract":"We propose the design and simulation study of novel gallium nitride (GaN) devices, consisting of nitride stacks with different polarity, to provide multiple channels by flexible gate(s) control. Calibrated TCAD device simulations visualize device characteristics of 0.62-μm-gate-length multi-channel transistors. E-mode operations demonstrate a positive small threshold voltage V<sub>th</sub> below 2 V at V<sub>ds</sub> = 0.1 V for all multichannel devices, and a high on-state current I<sub>on</sub> (V<sub>gs</sub> = V<sub>ds</sub> = 4 V) up to 4 A/mm achieved by 4 channels induced within the device.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125123195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694424
S. Reggiani, G. Barone, E. Gnani, A. Gnudi, G. Baccarani, S. Poli, M.-Y Chuang, W. Tian, R. Wise
A new TCAD-based approach is used to investigate hot-carrier stress (HCS) effects, especially suited for power devices. Physically-based degradation models are used to determine the interface trap generation at different stress biases and ambient temperatures. Special attention has been given to the high current-voltage regimes, when significant self-heating effects and impact ionization play a relevant role. By monitoring the linear and saturation regimes of a rugged LDMOS at different stress biases and times, the spatial and energetic distribution of acceptor- and donor-type traps has been investigated for the first time confirming the experimental results.
{"title":"TCAD predictions of linear and saturation HCS degradation in STI-based LDMOS transistors stressed in the impact-ionization regime","authors":"S. Reggiani, G. Barone, E. Gnani, A. Gnudi, G. Baccarani, S. Poli, M.-Y Chuang, W. Tian, R. Wise","doi":"10.1109/ISPSD.2013.6694424","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694424","url":null,"abstract":"A new TCAD-based approach is used to investigate hot-carrier stress (HCS) effects, especially suited for power devices. Physically-based degradation models are used to determine the interface trap generation at different stress biases and ambient temperatures. Special attention has been given to the high current-voltage regimes, when significant self-heating effects and impact ionization play a relevant role. By monitoring the linear and saturation regimes of a rugged LDMOS at different stress biases and times, the spatial and energetic distribution of acceptor- and donor-type traps has been investigated for the first time confirming the experimental results.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125383757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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