Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694480
Tongde Huang, X. Zhu, K. Lau
Enhancement-mode (E-mode) metal-oxide semiconductor high electron mobility transistors (MOSHEMTs) have been fabricated by selective area regrowth technique on AlN/GaN heterostructure. A selectively regrown AlGaN barrier layer could effectively increase the 2-dimensional electron gas (2DEG) density underneath. In comparison with the conventional methods of plasma etching/treatment in the gate region, the regrowth technique can effectively avoid damage caused by the plasma process. Atomic layer deposition of Al2O3 was employed as the gate dielectric. It was found that the Al2O3 on the AlN barrier layer also could induce a higher density of 2DEG. The fabricated E-mode MOSHEMTs with a 1.4-μm gate length exhibited excellent performance of maximum drain current of 530 mA/mm and peak transconductance of 310 mS/mm. The threshold voltage of MOSHEMTs was around +0.2 V. The reverse leakage current was also observed to be around 3.6 × 10-4 mA/mm at Vgs = -1 V and Vds = 6 V. The peak channel electron mobility was extracted to be 880 cm2/Vs using split-CV method. These results indicate that the regrowth technique is a promising method to realize E-mode transistors.
{"title":"Enhancement-mode AlN/GaN MOSHEMTs fabricated by selective area regrowth of AlGaN barrier layer","authors":"Tongde Huang, X. Zhu, K. Lau","doi":"10.1109/ISPSD.2013.6694480","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694480","url":null,"abstract":"Enhancement-mode (E-mode) metal-oxide semiconductor high electron mobility transistors (MOSHEMTs) have been fabricated by selective area regrowth technique on AlN/GaN heterostructure. A selectively regrown AlGaN barrier layer could effectively increase the 2-dimensional electron gas (2DEG) density underneath. In comparison with the conventional methods of plasma etching/treatment in the gate region, the regrowth technique can effectively avoid damage caused by the plasma process. Atomic layer deposition of Al2O3 was employed as the gate dielectric. It was found that the Al2O3 on the AlN barrier layer also could induce a higher density of 2DEG. The fabricated E-mode MOSHEMTs with a 1.4-μm gate length exhibited excellent performance of maximum drain current of 530 mA/mm and peak transconductance of 310 mS/mm. The threshold voltage of MOSHEMTs was around +0.2 V. The reverse leakage current was also observed to be around 3.6 × 10-4 mA/mm at Vgs = -1 V and Vds = 6 V. The peak channel electron mobility was extracted to be 880 cm2/Vs using split-CV method. These results indicate that the regrowth technique is a promising method to realize E-mode transistors.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121686243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694398
M. Sasaki, H. Nishio, A. Shorten, W. Ng
A gate driver IC with programmable output resistance (Rout) capable of performing current balancing for parallel connected IGBTs is presented in this paper. This novel method is to dynamically adjust the gate driver Rout to minimize the difference in the turn-on/off delay times between parallel connected IGBTs. The programmable gate driver Rout is implemented using a segmented output stage technique. This gate driver IC is designed and fabricated using TSMC's 0.18μm BCD Gen-2 process. Experimental results are obtained by measuring the current distribution between two parallel connected IGBTs (600V, 90A). These results indicate an improvement in average current imbalance of 89% and 98% for the turn-on and off periods, respectively.
{"title":"Current balancing control for parallel connected IGBTs using programmable gate driver output resistance","authors":"M. Sasaki, H. Nishio, A. Shorten, W. Ng","doi":"10.1109/ISPSD.2013.6694398","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694398","url":null,"abstract":"A gate driver IC with programmable output resistance (Rout) capable of performing current balancing for parallel connected IGBTs is presented in this paper. This novel method is to dynamically adjust the gate driver Rout to minimize the difference in the turn-on/off delay times between parallel connected IGBTs. The programmable gate driver Rout is implemented using a segmented output stage technique. This gate driver IC is designed and fabricated using TSMC's 0.18μm BCD Gen-2 process. Experimental results are obtained by measuring the current distribution between two parallel connected IGBTs (600V, 90A). These results indicate an improvement in average current imbalance of 89% and 98% for the turn-on and off periods, respectively.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126571451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694410
S. Yamasaki, T. Makino, D. Takeuchi, M. Ogura, H. Kato, T. Matsumoto, T. Iwasaki, M. Hatano, M. Suzuki, S. Koizumi, H. Ohashi, H. Okushi
For the next generation power devices, we have developed several types of unique diamond power devices. By these device performances, we conclude that by using the unique properties of diamond in addition to the superior structural FOM (figure of merit) the diamond power devices have high potential for the power devices. We discuss the potential of diamond power devices, specially, for ultra-high voltage application.
{"title":"Potential of diamond power devices","authors":"S. Yamasaki, T. Makino, D. Takeuchi, M. Ogura, H. Kato, T. Matsumoto, T. Iwasaki, M. Hatano, M. Suzuki, S. Koizumi, H. Ohashi, H. Okushi","doi":"10.1109/ISPSD.2013.6694410","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694410","url":null,"abstract":"For the next generation power devices, we have developed several types of unique diamond power devices. By these device performances, we conclude that by using the unique properties of diamond in addition to the superior structural FOM (figure of merit) the diamond power devices have high potential for the power devices. We discuss the potential of diamond power devices, specially, for ultra-high voltage application.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128093276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694434
S. Bahl, M. Van Hove, X. Kang, D. Marcon, M. Zahid, S. Decoutere
We find that off-state breakdown in AlGaN/GaN insulated-gate HEMTs can occur at the source-side of the gate with increase in the drain voltage. This new finding is borne out by extensive electrical measurements and confirmed with the OBIRCH (Optical Beam Induced Resistance CHange) technique. It is explained by a hypothesis whereby holes generated at high Vds flow to the source-side of the gate, and due to the low valence band offset, enter the gate insulator and damage it. Holes also cause threshold voltage shifts that turn the device on. The damage occurs in discrete spots, as would be expected by defects. Finally, we show improved breakdown voltage with a better gate-dielectric interface.
{"title":"New source-side breakdown mechanism in AlGaN/GaN insulated-gate HEMTs","authors":"S. Bahl, M. Van Hove, X. Kang, D. Marcon, M. Zahid, S. Decoutere","doi":"10.1109/ISPSD.2013.6694434","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694434","url":null,"abstract":"We find that off-state breakdown in AlGaN/GaN insulated-gate HEMTs can occur at the source-side of the gate with increase in the drain voltage. This new finding is borne out by extensive electrical measurements and confirmed with the OBIRCH (Optical Beam Induced Resistance CHange) technique. It is explained by a hypothesis whereby holes generated at high Vds flow to the source-side of the gate, and due to the low valence band offset, enter the gate insulator and damage it. Holes also cause threshold voltage shifts that turn the device on. The damage occurs in discrete spots, as would be expected by defects. Finally, we show improved breakdown voltage with a better gate-dielectric interface.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130718300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694472
Chaofeng Cai, Li Zhang, Na Ren, Kuang Sheng
In this paper, a new rectifier structure in silicon carbide (SiC) is presented for the first time. The proposed structure involves neither Schottky contact nor minor carrier injection via P-N junction. With adjacent P+ areas placed sufficiently close, pinched barrier is formed for rectifier purpose. Numerical simulations are carried out to verify its function, and optimize its performance. Based on the simulation results, a good trade-off can be achieved between forward drop and reverse leakage, provided that this new structure offers flexibility of controlling onset voltage by adjusting channel parameters continuously.
{"title":"Silicon carbide pinched barrier rectifier (PBR)","authors":"Chaofeng Cai, Li Zhang, Na Ren, Kuang Sheng","doi":"10.1109/ISPSD.2013.6694472","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694472","url":null,"abstract":"In this paper, a new rectifier structure in silicon carbide (SiC) is presented for the first time. The proposed structure involves neither Schottky contact nor minor carrier injection via P-N junction. With adjacent P+ areas placed sufficiently close, pinched barrier is formed for rectifier purpose. Numerical simulations are carried out to verify its function, and optimize its performance. Based on the simulation results, a good trade-off can be achieved between forward drop and reverse leakage, provided that this new structure offers flexibility of controlling onset voltage by adjusting channel parameters continuously.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126323233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694392
M. Sumitomo, H. Sakane, K. Arakawa, Y. Higuchi, M. Matsui
We proposed a PNM-IGBT [1] that can realize performance close to the theoretical limit shown by Nakagawa, et, al [2, 3]. In that work, we confirmed PNM-IGBT can achieve a very low saturation voltage due to its great injection enhancement effect. However, it is accompanied by a slight increase in turn-off-loss. We believe that we can diminish this increase by our unique control technique. Therefore, in this paper, we propose a fundamentally new IGBT control technique. By combining this control technique and PNM-IGBT, it becomes possible to achieve both a low saturation voltage and fast switching speed. To demonstrate the above hypothesis, we have developed a double gate PNM-IGBT, and confirmed a decrease in turn-off-loss of 30% using this technique.
{"title":"Injection control technique for high speed switching with a double gate PNM-IGBT","authors":"M. Sumitomo, H. Sakane, K. Arakawa, Y. Higuchi, M. Matsui","doi":"10.1109/ISPSD.2013.6694392","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694392","url":null,"abstract":"We proposed a PNM-IGBT [1] that can realize performance close to the theoretical limit shown by Nakagawa, et, al [2, 3]. In that work, we confirmed PNM-IGBT can achieve a very low saturation voltage due to its great injection enhancement effect. However, it is accompanied by a slight increase in turn-off-loss. We believe that we can diminish this increase by our unique control technique. Therefore, in this paper, we propose a fundamentally new IGBT control technique. By combining this control technique and PNM-IGBT, it becomes possible to achieve both a low saturation voltage and fast switching speed. To demonstrate the above hypothesis, we have developed a double gate PNM-IGBT, and confirmed a decrease in turn-off-loss of 30% using this technique.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114586623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694438
K. Matsushita, H. Ninomiya, T. Naijo, M. Izumi, S. Umekawa
A novel IEGT (Injection Enhanced Gate Transistor) design for drastically reducing of gate capacitance has been proposed in this work. The device structure named IEGT-TSE (IEGT with Trench Shield Emitter) has a dummy trench electrode connected to an emitter electrode. It shields gate electrode from floating p-well during switching. To demonstrate this effect, we exhibit switching waveforms by a numerical simulation and a fabricated device at 1200 blocking voltage class.
本文提出了一种新型的注入增强型栅极晶体管(IEGT)设计，可大幅降低栅极电容。该器件结构名为IEGT- tse (IEGT with Trench Shield Emitter)，其假沟槽电极与发射极连接。它在开关过程中屏蔽栅电极的p阱浮动。为了证明这种效应，我们通过数值模拟和制造器件展示了1200级阻断电压下的开关波形。
{"title":"Low gate capacitance IEGT with Trench Shield Emitter (IEGT-TSE) realizing high frequency operation","authors":"K. Matsushita, H. Ninomiya, T. Naijo, M. Izumi, S. Umekawa","doi":"10.1109/ISPSD.2013.6694438","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694438","url":null,"abstract":"A novel IEGT (Injection Enhanced Gate Transistor) design for drastically reducing of gate capacitance has been proposed in this work. The device structure named IEGT-TSE (IEGT with Trench Shield Emitter) has a dummy trench electrode connected to an emitter electrode. It shields gate electrode from floating p-well during switching. To demonstrate this effect, we exhibit switching waveforms by a numerical simulation and a fabricated device at 1200 blocking voltage class.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133028624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694390
Jun Hu, M. Bobde, H. Yilmaz, A. Bhalla
A trench shielded planar gate IGBT is proposed in this paper. The unique 3D top cell structure, combining high density trench and low channel density, offers an excellent conduction vs. switching loss trade-off and a significantly better Short-circuit SOA compared to trench IEGTs. Measurements on fabricated devices show a 0.1V lower VCESAT for the same Eoff, and a 2x improvement in short circuit SOA.
{"title":"Trench shielded planar gate IGBT (TSPG-IGBT) for low loss and robust short-circuit capalibity","authors":"Jun Hu, M. Bobde, H. Yilmaz, A. Bhalla","doi":"10.1109/ISPSD.2013.6694390","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694390","url":null,"abstract":"A trench shielded planar gate IGBT is proposed in this paper. The unique 3D top cell structure, combining high density trench and low channel density, offers an excellent conduction vs. switching loss trade-off and a significantly better Short-circuit SOA compared to trench IEGTs. Measurements on fabricated devices show a 0.1V lower VCESAT for the same Eoff, and a 2x improvement in short circuit SOA.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131801918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694429
Kun Mao, M. Qiao, Lingli Jiang, Huaping Jiang, Zehong Li, Weizhong Chen, Zhaoji Li, Bo Zhang
Integrated in a 0.35 μm 700 V BCD process platform, ultra-low Ron, sp 700 V self-ISO (isolated) and NISO (non-isolated) DB-nLDMOS (dual P-buried-layer nLDMOS) are proposed in this paper. 800 V and 780 V are achieved for NISO and ISO DB-nLDMOS, of which Ron, sp are 11.5 Ω·mm2 and 11.2 Ω·mm2, respectively. Utra-low Ron, sp benefits from optimized device size and strict limitations for annealing temperature and time after P-bury-layer implantation. For ISO DB-nLDMOS, by separately implanting NWELLs, NWELL drift region of low doping concentration under gate poly is achieved and then premature avalanche breakdown around bird's beak is avoided. Moreover, a 600 V DB-nJFET (dual P-buried-layer nJFET) with innovative 3D pinch-off structure is also presented.
在0.35 μm 700 V BCD工艺平台上集成了超低Ron、sp 700 V自iso(隔离)和NISO(非隔离)DB-nLDMOS(双p埋层nLDMOS)。NISO和ISO DB-nLDMOS的电压分别为800 V和780 V，其中Ron, sp分别为11.5 Ω·mm2和11.2 Ω·mm2。超低Ron, sp得益于优化的器件尺寸和p -埋层植入后对退火温度和时间的严格限制。对于ISO DB-nLDMOS，通过单独植入NWELL，实现栅聚下低掺杂浓度的NWELL漂移区，避免了鸟喙周围过早的雪崩击穿。此外，还提出了一种新颖的具有三维掐断结构的600 V DB-nJFET(双p埋层nJFET)。
{"title":"A 0.35 μm 700 V BCD technology with self-isolated and non-isolated ultra-low specific on-resistance DB-nLDMOS","authors":"Kun Mao, M. Qiao, Lingli Jiang, Huaping Jiang, Zehong Li, Weizhong Chen, Zhaoji Li, Bo Zhang","doi":"10.1109/ISPSD.2013.6694429","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694429","url":null,"abstract":"Integrated in a 0.35 μm 700 V BCD process platform, ultra-low R<sub>on, sp</sub> 700 V self-ISO (isolated) and NISO (non-isolated) DB-nLDMOS (dual P-buried-layer nLDMOS) are proposed in this paper. 800 V and 780 V are achieved for NISO and ISO DB-nLDMOS, of which R<sub>on, sp</sub> are 11.5 Ω·mm<sup>2</sup> and 11.2 Ω·mm<sup>2</sup>, respectively. Utra-low R<sub>on, sp</sub> benefits from optimized device size and strict limitations for annealing temperature and time after P-bury-layer implantation. For ISO DB-nLDMOS, by separately implanting NWELLs, NWELL drift region of low doping concentration under gate poly is achieved and then premature avalanche breakdown around bird's beak is avoided. Moreover, a 600 V DB-nJFET (dual P-buried-layer nJFET) with innovative 3D pinch-off structure is also presented.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130315362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694419
Yamato Miki, M. Mukunoki, Takashi Matsuyoshi, M. Tsukuda, I. Omura
4.5 kV IEGT turn-on loss reduction is experimentally and numerically achieved by employing the proposed simple two step gate drive method without affecting PiN diode reverse recovery performance. It was found that 14% of turn-on loss is reduced only by the simple method. This study determines, for the first time, the optimum gate driving in the two step gate drive which can reduce IEGT turn-on loss maximally without affecting PiN diode reverse recovery performance by TCAD simulation. The method is simple yet effective for reducing switching loss of high voltage IEGT.
{"title":"High speed turn-on gate driving for 4.5kV IEGT without increase in PiN diode recovery current","authors":"Yamato Miki, M. Mukunoki, Takashi Matsuyoshi, M. Tsukuda, I. Omura","doi":"10.1109/ISPSD.2013.6694419","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694419","url":null,"abstract":"4.5 kV IEGT turn-on loss reduction is experimentally and numerically achieved by employing the proposed simple two step gate drive method without affecting PiN diode reverse recovery performance. It was found that 14% of turn-on loss is reduced only by the simple method. This study determines, for the first time, the optimum gate driving in the two step gate drive which can reduce IEGT turn-on loss maximally without affecting PiN diode reverse recovery performance by TCAD simulation. The method is simple yet effective for reducing switching loss of high voltage IEGT.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131023408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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