Pub Date : 2018-03-01DOI: 10.1109/ICDCSYST.2018.8605139
Krishna Chaitanya Sankisa, R. Sahoo, S. K. Sahoo
The Adder is one of the most important and basic units of arithmetic logics which is used to design many complex circuits. Till now, all arithmetic circuits are mostly use CMOS circuits for binary logic implementation. Recently Carbon nanotube field effect transistor (CNTFET) has attracted many researchers as its threshold voltage can be varied by changing the diameter of carbon nanotube which makes it useful for designing multivalued logic circuits. Exploring this property of CNTFET, few researchers have designed ternary adders. In this work, first time a Quaternary full adder using CNTFET based of circuit is proposed. The proposed circuit is designed based on the conventional CMOS architecture with utilization of inherent binary nature (0,1) of input carry signal. Since voltage at the output of the dynamic logic circuit is stored on a parasitic capacitance, a quaternary keeper circuit is used to alleviate charge sharing problems. The proposed design of Quaternary full adder circuit is simulated using HSPICE simulator with 14 nm Stanford CNTFET model. This adder consumes 103.18 nw power and has delay of 17.46 psec. This is a first effort to design a quaternary logic adder circuit.
{"title":"A CNTFET Based Quaternary Ful1 Adder","authors":"Krishna Chaitanya Sankisa, R. Sahoo, S. K. Sahoo","doi":"10.1109/ICDCSYST.2018.8605139","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605139","url":null,"abstract":"The Adder is one of the most important and basic units of arithmetic logics which is used to design many complex circuits. Till now, all arithmetic circuits are mostly use CMOS circuits for binary logic implementation. Recently Carbon nanotube field effect transistor (CNTFET) has attracted many researchers as its threshold voltage can be varied by changing the diameter of carbon nanotube which makes it useful for designing multivalued logic circuits. Exploring this property of CNTFET, few researchers have designed ternary adders. In this work, first time a Quaternary full adder using CNTFET based of circuit is proposed. The proposed circuit is designed based on the conventional CMOS architecture with utilization of inherent binary nature (0,1) of input carry signal. Since voltage at the output of the dynamic logic circuit is stored on a parasitic capacitance, a quaternary keeper circuit is used to alleviate charge sharing problems. The proposed design of Quaternary full adder circuit is simulated using HSPICE simulator with 14 nm Stanford CNTFET model. This adder consumes 103.18 nw power and has delay of 17.46 psec. This is a first effort to design a quaternary logic adder circuit.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121893285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ICDCSYST.2018.8605073
G. Thriveni, K. Ghosh
A numerical model using self consistent Poisson's equation solver is presented to elucidate the potential profile and current-voltage characteristics of double gate nanoMOSFET using 32nm technology. Here we have explored the performance of the nanodevice with different dielectric layers. The focus of this work is to identify the type of gate dielectric material which is capable enough to control the electrostatics across the channel through gate bias and reduce the tunneling current. We find that $mathrm {T}mathrm {i}mathrm {O}_{2}$ layer having k=80 produces higher tunneling current through gate leakage although it exhibited stronger gate control on the channel conduction. A combination of $mathrm {T}mathrm {i}mathrm {O}_{2}$ and $mathrm {S}mathrm {i}mathrm {O}_{2}$ dielectric layers is proposed to mitigate tunnelling in these devices and improve its performance.
{"title":"Choice of Gate Insulator for Effective Gate Electrostatics in Double Gate Nanoscale Mosfet","authors":"G. Thriveni, K. Ghosh","doi":"10.1109/ICDCSYST.2018.8605073","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605073","url":null,"abstract":"A numerical model using self consistent Poisson's equation solver is presented to elucidate the potential profile and current-voltage characteristics of double gate nanoMOSFET using 32nm technology. Here we have explored the performance of the nanodevice with different dielectric layers. The focus of this work is to identify the type of gate dielectric material which is capable enough to control the electrostatics across the channel through gate bias and reduce the tunneling current. We find that $mathrm {T}mathrm {i}mathrm {O}_{2}$ layer having k=80 produces higher tunneling current through gate leakage although it exhibited stronger gate control on the channel conduction. A combination of $mathrm {T}mathrm {i}mathrm {O}_{2}$ and $mathrm {S}mathrm {i}mathrm {O}_{2}$ dielectric layers is proposed to mitigate tunnelling in these devices and improve its performance.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127615256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ICDCSYST.2018.8605125
Narasimhulu Thoti, R. Haritha, A. K. Kumar, A. Yadav, V. Narasimha Rao
one of the futuristic devices in replacing the conventional MOS device structure is TFET. In the proposed work, a 3D-fin-TFET geometrical structure with various lower-band gap materials has been investigated and achieved the sophisticated results. The higher drive current (IDS) achievement with the use of InAs based source junction has been reported. In addition to this various DC and RF metrics have been investigated and shown with better results. These characteristics have been extracted by considering the source material variations with that of Si/Sio0.6Geo0.4/InAs and the rcst is of Si. Thc clectrical analysis is cxtracted by using HfO2 as the dielectric, hence the maximum drive current (ID) of 7.1 mA is reported with InAs as the source. A least subthreshold swing of 11.90mV/decade is reported. For an InAs as source improved characteristics have been observed in the various DC characteristics are of Subthreshols swing, transconductance, output impedance and intrinsic gain. Also, RF metrics such as unity gain cutoff frequency (ft), maximum oscillation frequencies (fmax) with higher ft of 338.03 GHz and fmax of 776.26 GHz are reported.
{"title":"Comparative investigation of Si/Sio.6Geo.4/InAs 3D-fin-TFET for its optimized performance","authors":"Narasimhulu Thoti, R. Haritha, A. K. Kumar, A. Yadav, V. Narasimha Rao","doi":"10.1109/ICDCSYST.2018.8605125","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605125","url":null,"abstract":"one of the futuristic devices in replacing the conventional MOS device structure is TFET. In the proposed work, a 3D-fin-TFET geometrical structure with various lower-band gap materials has been investigated and achieved the sophisticated results. The higher drive current (IDS) achievement with the use of InAs based source junction has been reported. In addition to this various DC and RF metrics have been investigated and shown with better results. These characteristics have been extracted by considering the source material variations with that of Si/Sio0.6Geo0.4/InAs and the rcst is of Si. Thc clectrical analysis is cxtracted by using HfO2 as the dielectric, hence the maximum drive current (ID) of 7.1 mA is reported with InAs as the source. A least subthreshold swing of 11.90mV/decade is reported. For an InAs as source improved characteristics have been observed in the various DC characteristics are of Subthreshols swing, transconductance, output impedance and intrinsic gain. Also, RF metrics such as unity gain cutoff frequency (ft), maximum oscillation frequencies (fmax) with higher ft of 338.03 GHz and fmax of 776.26 GHz are reported.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127732382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ICDCSYST.2018.8605155
P. Bruntha, Jaisil Rose. D, Shruthi A. T, Glory Juliet. K, Kanimozhi M
An effective methodology is proposed for early detection of lung cancer using computed tomography. A detailed literature survey and real time happenings led to capture the abnormal nodules. Initially, gaussian filter was used in pre-processing to remove noise. For segmenting lung parenchyma, an adaptive intensity thresholding method was used. To detect nodules, morphological operation as well as selective region growing algorithm was used. The abnormal nodules were detected by filtering the segmented image based on area.
{"title":"Application Of Selective Region Growing Algorithm In Lung Nodule Segmentation","authors":"P. Bruntha, Jaisil Rose. D, Shruthi A. T, Glory Juliet. K, Kanimozhi M","doi":"10.1109/ICDCSYST.2018.8605155","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605155","url":null,"abstract":"An effective methodology is proposed for early detection of lung cancer using computed tomography. A detailed literature survey and real time happenings led to capture the abnormal nodules. Initially, gaussian filter was used in pre-processing to remove noise. For segmenting lung parenchyma, an adaptive intensity thresholding method was used. To detect nodules, morphological operation as well as selective region growing algorithm was used. The abnormal nodules were detected by filtering the segmented image based on area.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130442458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ICDCSYST.2018.8605169
V. Adinarayana, K. Krishna, P. R. Kumar
In 5G cellular networks Massive MIMO system offers many advantages including high performance due to simple transmit and receive operations. Essential feature for such system is the proper evaluation of channel state information at the transmitter (CSIT) which is not easy due to larger dimensional channels. Using standard techniques LS and proposed CS schemes simultaneously results in reduction of pilot overhead. This paper explains an estimation of channel in TDD domain with both least squares, CS techniques lessens the pilot overhead through NMSE against training sequence, Normalized beam forming gain against Tp at a specific SNR value, NMSE for different Fading block index with Tp as 60 under scattering evolution with ULA, UPA environment.
{"title":"Compressed sensing aided estimation of channel in downlink TDD large scale MIMO system","authors":"V. Adinarayana, K. Krishna, P. R. Kumar","doi":"10.1109/ICDCSYST.2018.8605169","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605169","url":null,"abstract":"In 5G cellular networks Massive MIMO system offers many advantages including high performance due to simple transmit and receive operations. Essential feature for such system is the proper evaluation of channel state information at the transmitter (CSIT) which is not easy due to larger dimensional channels. Using standard techniques LS and proposed CS schemes simultaneously results in reduction of pilot overhead. This paper explains an estimation of channel in TDD domain with both least squares, CS techniques lessens the pilot overhead through NMSE against training sequence, Normalized beam forming gain against Tp at a specific SNR value, NMSE for different Fading block index with Tp as 60 under scattering evolution with ULA, UPA environment.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114285764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ICDCSYST.2018.8605152
D. Shylu, J. Helan, Jackuline Moni
This paper presents a design of 12-bit low power Delta Sigma ADC using telescopic op-amp architecture for space application. The self-biased technique used in the designed telescopic op-amp which eliminates the need for an external bias circuit. The combination of common source stage and common gate with the operational amplifier consumes less power and operated at high speed. This is achieved by changing the bias values of the currents in the input and the output stages. The circuit consists of less number of transistors in order to reduce the complexity and is designed with Refracting Telescopic amplifier. The simulation of the design is carried in 90nm standard CMOS technology and consumes 51.1pw power with 0.6 V(p-p)diff input signal and achieves the open loop gain of 41dB.
{"title":"Design of 12 Bit 100MS/s Low Power Delta Sigma ADC Using Telescopic Amplifier","authors":"D. Shylu, J. Helan, Jackuline Moni","doi":"10.1109/ICDCSYST.2018.8605152","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605152","url":null,"abstract":"This paper presents a design of 12-bit low power Delta Sigma ADC using telescopic op-amp architecture for space application. The self-biased technique used in the designed telescopic op-amp which eliminates the need for an external bias circuit. The combination of common source stage and common gate with the operational amplifier consumes less power and operated at high speed. This is achieved by changing the bias values of the currents in the input and the output stages. The circuit consists of less number of transistors in order to reduce the complexity and is designed with Refracting Telescopic amplifier. The simulation of the design is carried in 90nm standard CMOS technology and consumes 51.1pw power with 0.6 V(p-p)diff input signal and achieves the open loop gain of 41dB.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"269 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121219388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/icdcsyst.2018.8605136
A. K. Ray, Alok Kumar Lenka
This paper presents a novel method to control the transmitter output power of PCMC (precision coherent monopulse C-band) radar by isolating the CFA (cross field amplifier) stage of MOPA (master oscillator power amplifier) chain. The isolation is achieved by switching mechanism in case of short-range tracking and it provides signal amplification in long-range tracking. The proposed scheme also reduces CFA operation time and TWT (traveling wave tube) output load.
{"title":"Transmitter Output Power Control of PCMC Radar for Short Range Tracking Bypassing Cross-field Amplifier","authors":"A. K. Ray, Alok Kumar Lenka","doi":"10.1109/icdcsyst.2018.8605136","DOIUrl":"https://doi.org/10.1109/icdcsyst.2018.8605136","url":null,"abstract":"This paper presents a novel method to control the transmitter output power of PCMC (precision coherent monopulse C-band) radar by isolating the CFA (cross field amplifier) stage of MOPA (master oscillator power amplifier) chain. The isolation is achieved by switching mechanism in case of short-range tracking and it provides signal amplification in long-range tracking. The proposed scheme also reduces CFA operation time and TWT (traveling wave tube) output load.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116155149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ICDCSYST.2018.8605163
Ayisha B S, C. Saha, S. Joy, Apren T. J
This paper explains the design and simulation of a 2-stage $S$-band cascadable amplifier using $pHEMT-ATF 54143$ with wide band characteristics. $A$ modified tunable equalizer is proposed using which the amplifier is operated in S-band. Tunability of the equalizer is verified by designing the amplifier in 2–3 GHz, 3- $4GHz$ and in the entire $S$-band (2–4GHz). The gain obtained from all the three designs are flat when compared with previously reported results using equalizer. $A$ theoretical formulation to calculate the $S_{21}$ of the device is proposed and validated.
{"title":"Design of Cascadable S-band Amplifier using Tunable Equalizer","authors":"Ayisha B S, C. Saha, S. Joy, Apren T. J","doi":"10.1109/ICDCSYST.2018.8605163","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605163","url":null,"abstract":"This paper explains the design and simulation of a 2-stage $S$-band cascadable amplifier using $pHEMT-ATF 54143$ with wide band characteristics. $A$ modified tunable equalizer is proposed using which the amplifier is operated in S-band. Tunability of the equalizer is verified by designing the amplifier in 2–3 GHz, 3- $4GHz$ and in the entire $S$-band (2–4GHz). The gain obtained from all the three designs are flat when compared with previously reported results using equalizer. $A$ theoretical formulation to calculate the $S_{21}$ of the device is proposed and validated.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114561370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ICDCSYST.2018.8605151
T. Ravibabu, C. D. Raj
Higher data rates and reliability have been problems in the wireless communication systems from the outset. It is essential and necessary even by deal with multiple antennas at both ends; simultaneously fading occurs to each link can be considered due to multipath propagation this leads to increase BER performance at the receiver. We can achieve reliability and high data rates through MIMO-OFDM with STBC and spatial multiplexing techniques are used respectively. This paper explores to analyze different fading channels (Rayleigh and Nakagami) under AWGN environment on spatial multiplexing (SM) based MIMO systems, Zero forcing with Successive interference Cancellation (ZF-SIC), MMSE-SIC and ML equalization techniques are used to channel equalization. And of transmit diversity, STBC based MIMO-OFDM systems, Maximum Ratio Combining (MRC) technique is used. Simulation results showed with various modulation techniques (BPSK/QPSK/64QAM/32PSK) both Systems. Furthermore, BER performance of coded MIMO-Wi-Max systems also describes to transmit diversity.
{"title":"BER Analysis of spatial multiplexing and STBC MIMO-OFDM System","authors":"T. Ravibabu, C. D. Raj","doi":"10.1109/ICDCSYST.2018.8605151","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605151","url":null,"abstract":"Higher data rates and reliability have been problems in the wireless communication systems from the outset. It is essential and necessary even by deal with multiple antennas at both ends; simultaneously fading occurs to each link can be considered due to multipath propagation this leads to increase BER performance at the receiver. We can achieve reliability and high data rates through MIMO-OFDM with STBC and spatial multiplexing techniques are used respectively. This paper explores to analyze different fading channels (Rayleigh and Nakagami) under AWGN environment on spatial multiplexing (SM) based MIMO systems, Zero forcing with Successive interference Cancellation (ZF-SIC), MMSE-SIC and ML equalization techniques are used to channel equalization. And of transmit diversity, STBC based MIMO-OFDM systems, Maximum Ratio Combining (MRC) technique is used. Simulation results showed with various modulation techniques (BPSK/QPSK/64QAM/32PSK) both Systems. Furthermore, BER performance of coded MIMO-Wi-Max systems also describes to transmit diversity.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129305553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ICDCSYST.2018.8605069
Jun-jie Zhu, Qinsong Qian, Shengli Lu, Weifeng Sun
This paper proposes a novel PSSB converter with three shared leading-legs. The ZVS of all the primary-side switches can be realized with wide conversion range and full load range. Moreover, the effective duty cycle has nothing to do with the dead-time. Thus, the PSSB would be useful for high switching frequency application. A 100W PSSB converter has been made with GaN transistors and planar transformers to verify the characteristics of PSSB. The experimental results show that the PSSB converter can achieve a peak efficiency of 93.8% when the switching frequency is 300kHz.
{"title":"A Phase-shift Single Ful1-bridge (PSSB) Converter with Three Shared Leading-legs","authors":"Jun-jie Zhu, Qinsong Qian, Shengli Lu, Weifeng Sun","doi":"10.1109/ICDCSYST.2018.8605069","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605069","url":null,"abstract":"This paper proposes a novel PSSB converter with three shared leading-legs. The ZVS of all the primary-side switches can be realized with wide conversion range and full load range. Moreover, the effective duty cycle has nothing to do with the dead-time. Thus, the PSSB would be useful for high switching frequency application. A 100W PSSB converter has been made with GaN transistors and planar transformers to verify the characteristics of PSSB. The experimental results show that the PSSB converter can achieve a peak efficiency of 93.8% when the switching frequency is 300kHz.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132292748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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