Pub Date : 2018-03-16DOI: 10.1109/ICDCSYST.2018.8605178
A. Napolean, N. M. Sivamangai, Joel Samuel, Vimukth John
This review contribute the consequence of compliance current (CC) on a widely used metal oxide Resistive Random Access Memory (RRAM) device distinctive characteristics of resistive switching and reliability. Article starts with the current trends of RRAM technology, then short knowledge about different nonvolatile memory technology forces to limit, RRAM device structure, switching principles, material selection and reliability controversy. Next a detailed short account of CC value with other RRAM device measure. This review ends with the decisive of electing an optimized CC value for a superior switching and reliability.
{"title":"Overview of Current Compliance Effect on Reliability of Nano Scaled Metal Oxide Resistive Random Access Memory Device","authors":"A. Napolean, N. M. Sivamangai, Joel Samuel, Vimukth John","doi":"10.1109/ICDCSYST.2018.8605178","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605178","url":null,"abstract":"This review contribute the consequence of compliance current (CC) on a widely used metal oxide Resistive Random Access Memory (RRAM) device distinctive characteristics of resistive switching and reliability. Article starts with the current trends of RRAM technology, then short knowledge about different nonvolatile memory technology forces to limit, RRAM device structure, switching principles, material selection and reliability controversy. Next a detailed short account of CC value with other RRAM device measure. This review ends with the decisive of electing an optimized CC value for a superior switching and reliability.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134154088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-16DOI: 10.1109/ICDCSYST.2018.8605070
C. J., Ponmudi Selvan T., S. M., I. Sheebha, V. B, R. S.
Orthorhombic molybdenum trioxide (MoO3) and monoclinic molybdenum dioxide (MoO2) thin films were prepared using the pulsed laser deposition technique under the oxygen (O2) and Argon (Ar) processing gas atmospheres. The MoO3 samples were pulsed laser deposited over a range of deposition temperature, 303K to 873K at 10Hz in the O2 atmosphere. The characterisation of both the oxide thin films was studied using FESEM, XRD, UV-Visible spectroscopy, Hall measurement systems and linear sweep voltammetry. This deposition technique would be an effective deposition method for MoO3 and MoO2 thin films due to the fast, high quality, stoichiometric and eco-friendly process. The surface morphology dramatically changed by substrate deposition and deposition time at different temperatures. The samples were annealed at 673K and the properties were analysed. The neatly decorated nanostructures of 500 nm thick MoO3 and MoO2 are obtained for 12000 shots laser ablated samples and are then characterized. The IV characteristics, optical and electrical properties provide essential characteristics results for the potential nanoelectronics applications.
{"title":"Pulsed Laser Deposited Molybdenum Oxides (MoO3 & MoO2) Thin Films for Nanoelectronics Device Application","authors":"C. J., Ponmudi Selvan T., S. M., I. Sheebha, V. B, R. S.","doi":"10.1109/ICDCSYST.2018.8605070","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605070","url":null,"abstract":"Orthorhombic molybdenum trioxide (MoO3) and monoclinic molybdenum dioxide (MoO2) thin films were prepared using the pulsed laser deposition technique under the oxygen (O2) and Argon (Ar) processing gas atmospheres. The MoO3 samples were pulsed laser deposited over a range of deposition temperature, 303K to 873K at 10Hz in the O2 atmosphere. The characterisation of both the oxide thin films was studied using FESEM, XRD, UV-Visible spectroscopy, Hall measurement systems and linear sweep voltammetry. This deposition technique would be an effective deposition method for MoO3 and MoO2 thin films due to the fast, high quality, stoichiometric and eco-friendly process. The surface morphology dramatically changed by substrate deposition and deposition time at different temperatures. The samples were annealed at 673K and the properties were analysed. The neatly decorated nanostructures of 500 nm thick MoO3 and MoO2 are obtained for 12000 shots laser ablated samples and are then characterized. The IV characteristics, optical and electrical properties provide essential characteristics results for the potential nanoelectronics applications.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121578404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-16DOI: 10.1109/ICDCSYST.2018.8605130
D. Shylu, S. Jasmine, D. Moni
210MS/s 12-bit pipelined SAR ADC that can be used for mobile applications consists of various components that can reduce the precision and the power consumption of the device. It has been identified that the main component that causes a high power consumption in the circuit design is the dynamic comparator. The proposed design of the dynamic comparator shows a double tail dynamic comparator with an output buffer, which creates an impedance that can reduce the power consumption of the circuit considerably. The maximum power consumption of the comparator used is measured to be 402.3pW.
{"title":"A Low Power Dynamic Comparator For A 12-Bit Pipelined Successive Approximation Register (SAR) ADC","authors":"D. Shylu, S. Jasmine, D. Moni","doi":"10.1109/ICDCSYST.2018.8605130","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605130","url":null,"abstract":"210MS/s 12-bit pipelined SAR ADC that can be used for mobile applications consists of various components that can reduce the precision and the power consumption of the device. It has been identified that the main component that causes a high power consumption in the circuit design is the dynamic comparator. The proposed design of the dynamic comparator shows a double tail dynamic comparator with an output buffer, which creates an impedance that can reduce the power consumption of the circuit considerably. The maximum power consumption of the comparator used is measured to be 402.3pW.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":" 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113947221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ICDCSYST.2018.8605129
Hema Mehta, H. Kaur
In the present work, performance of short channel symmetric Double Gate Gaussian Doped Ferroelectric FET (DGGDFEFET) has been studied by using fully coupled TCAD simulations with Landau Khalatnikov equation. Ferroelectric layer of PVDF-TrFE (polyvinyledenedifluoride-trifluoroethylene) is considered as gate insulator with an intermediate layer of SiO2. The channel is non-uniformily doped in vertical direction and the analog and digital performance of DGGDFEFET has been investigated by obtaining transfer characteristics, subthreshold swing, transconductance ($g_{m}$), transconductance generation factor (TGF), output characteristics and output conductance ($g_{d}$). It has been demonstrated that due to negative capacitance and vertical non-uniform doping, DGGDFEFET shows superior analog and digital performance since it offers super steep transfer characteristics and substantially improved TGF and output characteristics.
{"title":"Performance Study of Short Channel Symmetric Double Gate Gaussian Doped Ferroelectric FET for Analog and Digital Applications","authors":"Hema Mehta, H. Kaur","doi":"10.1109/ICDCSYST.2018.8605129","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605129","url":null,"abstract":"In the present work, performance of short channel symmetric Double Gate Gaussian Doped Ferroelectric FET (DGGDFEFET) has been studied by using fully coupled TCAD simulations with Landau Khalatnikov equation. Ferroelectric layer of PVDF-TrFE (polyvinyledenedifluoride-trifluoroethylene) is considered as gate insulator with an intermediate layer of SiO2. The channel is non-uniformily doped in vertical direction and the analog and digital performance of DGGDFEFET has been investigated by obtaining transfer characteristics, subthreshold swing, transconductance ($g_{m}$), transconductance generation factor (TGF), output characteristics and output conductance ($g_{d}$). It has been demonstrated that due to negative capacitance and vertical non-uniform doping, DGGDFEFET shows superior analog and digital performance since it offers super steep transfer characteristics and substantially improved TGF and output characteristics.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115258218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ICDCSYST.2018.8605174
B. Jain, K. K. Jha, M. Pattanaik
In this work we have analyzed the impact of charge carrier’s injection mechanism on analog performance of amplifier. The present study is based on comparative analysis of two different FET based amplifiers i.e., Metal Oxide Semiconductor FET (MOSFET) amplifier and Sandwich Tunnel Barrier FET (STBFET) amplifier. The performance parameters for both the devices such as output characteristics, transfer characteristics, trans-conductance, output resistance, transconductance to drive current ratio, intrinsic gain, and unity gain cutoff frequency have been analyzed using numerical simulations. The analog performance of STBFET, which shows good drain current saturation, has been analyzed. Moreover its high trans-conductance to drive current ratio makes it suitable for high frequency applications. The output resistance of STBFET is found to be more than eight orders of magnitude higher than that for the MOSFET. Further STBFET based common source (CS) resistive load amplifier shows 2 to 3 times variations in amplification with variable load than that of MOSFET based amplifier. The qualitative analysis with variable input bias, oxide thickness and peak to peak swing is also reported.
{"title":"Comparative analysis of MOSFET and STBFET based amplifier for analog application","authors":"B. Jain, K. K. Jha, M. Pattanaik","doi":"10.1109/ICDCSYST.2018.8605174","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605174","url":null,"abstract":"In this work we have analyzed the impact of charge carrier’s injection mechanism on analog performance of amplifier. The present study is based on comparative analysis of two different FET based amplifiers i.e., Metal Oxide Semiconductor FET (MOSFET) amplifier and Sandwich Tunnel Barrier FET (STBFET) amplifier. The performance parameters for both the devices such as output characteristics, transfer characteristics, trans-conductance, output resistance, transconductance to drive current ratio, intrinsic gain, and unity gain cutoff frequency have been analyzed using numerical simulations. The analog performance of STBFET, which shows good drain current saturation, has been analyzed. Moreover its high trans-conductance to drive current ratio makes it suitable for high frequency applications. The output resistance of STBFET is found to be more than eight orders of magnitude higher than that for the MOSFET. Further STBFET based common source (CS) resistive load amplifier shows 2 to 3 times variations in amplification with variable load than that of MOSFET based amplifier. The qualitative analysis with variable input bias, oxide thickness and peak to peak swing is also reported.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122271867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ICDCSYST.2018.8605066
Patil Siddhant Vitthal, Amartya Basak, P. Mane
In the current age of having sophisticated appliances with sophisticated circuits, it becomes necessary to have circuit designs that are exploited to their full potential by making minimal changes in their basic designs. Low Power, high gain, high voltage swing and stable operating voltage amplifiers are required at various stages in these appliances. Therefore, the paper focuses on improving designs that have two stages. The three designs, namely, the simple two stage operational amplifier, the two stage operational amplifier with cascoding in the inner stage and lead compensation, and the two stage operational amplifier with cascoding in the inner stage, lead compensation and gain boosting are compared. The circuits are designed and simulated using the GPDK045 and Analog Library in the Cadence Virtuoso Design Environment with Length of MOSFETs as 180nm and VDD as 2V. Out of the three methods, the two stage operational amplifier with cascoding in the inner stage and lead compensation is found to give the highest unity gain bandwidth of 1.1436 GHz and the method with gain boosting is found to give the highest DC Gain of 117.1087dB. The corresponding phase margin and power dissipation of the two methods are 57.8963 degrees, 57.3776 degrees and 0.69mW, 0.235mW.
{"title":"Design of Voltage Amplifiers with optimization of Multiple Design Parameters","authors":"Patil Siddhant Vitthal, Amartya Basak, P. Mane","doi":"10.1109/ICDCSYST.2018.8605066","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605066","url":null,"abstract":"In the current age of having sophisticated appliances with sophisticated circuits, it becomes necessary to have circuit designs that are exploited to their full potential by making minimal changes in their basic designs. Low Power, high gain, high voltage swing and stable operating voltage amplifiers are required at various stages in these appliances. Therefore, the paper focuses on improving designs that have two stages. The three designs, namely, the simple two stage operational amplifier, the two stage operational amplifier with cascoding in the inner stage and lead compensation, and the two stage operational amplifier with cascoding in the inner stage, lead compensation and gain boosting are compared. The circuits are designed and simulated using the GPDK045 and Analog Library in the Cadence Virtuoso Design Environment with Length of MOSFETs as 180nm and VDD as 2V. Out of the three methods, the two stage operational amplifier with cascoding in the inner stage and lead compensation is found to give the highest unity gain bandwidth of 1.1436 GHz and the method with gain boosting is found to give the highest DC Gain of 117.1087dB. The corresponding phase margin and power dissipation of the two methods are 57.8963 degrees, 57.3776 degrees and 0.69mW, 0.235mW.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133750157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ICDCSYST.2018.8605160
S. K. Sriwas, Pramod Kumar
In the field of wireless communication, satellite communication and radar communication a selective microwave band of low pass filter (LPF) is used. The LPF of microwave band is used to reject the harmonic components of cut off frequency. This paper describes the design of a 5th order Mircostrip Elliptical LPF. The physical dimensions are calculated theoretically. The width and length of the stubs are later tuned and optimized to get the best insertion loss in stop and band with a high roll off rate. Kewwords:- Microstrip, LPF, Elliptic
{"title":"A Novel on Microstrip Low Pass Filter for Elliptic Response","authors":"S. K. Sriwas, Pramod Kumar","doi":"10.1109/ICDCSYST.2018.8605160","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605160","url":null,"abstract":"In the field of wireless communication, satellite communication and radar communication a selective microwave band of low pass filter (LPF) is used. The LPF of microwave band is used to reject the harmonic components of cut off frequency. This paper describes the design of a 5th order Mircostrip Elliptical LPF. The physical dimensions are calculated theoretically. The width and length of the stubs are later tuned and optimized to get the best insertion loss in stop and band with a high roll off rate. Kewwords:- Microstrip, LPF, Elliptic","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115632995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ICDCSYST.2018.8605134
S. Franklin, J. G. Jency
Transparent flexible capacitors are important in the development of advanced future electronics devices like transparent sensors, electronic devices, high pixel displays, thin film multilayer solar cells and transparent circuit. Transparent conducting films has a composite structure of Aluminium doped zinc Oxide - silver nanowire (AgNWs) is deposited using pulsed laser deposition technique. The resistance of transparent conducting films is 120 Ω/mm when ITO and AgNW network were involved. Transparent capacitors with the dielectric structure of AhO3-TiO2- AI2O3 were fabricated on the composite electrodes, with a capacitance density of 10.1fF μm-2. The broad frequency ranges from 3 kHz to 1 MHz. The flexibility is found to be a maximum of 25mm without changing the capacitance. Transparency of capacitor is demonstrated at an average optical transmittance of over 75–80% in the visible range, and thus the practical application of transparent devices and integrated circuits is obtained.
{"title":"A Study on Transparent and Flexible Capacitor using Hybrid Zinc Oxide: Indium Tin Oxide and Silver as electrodes","authors":"S. Franklin, J. G. Jency","doi":"10.1109/ICDCSYST.2018.8605134","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605134","url":null,"abstract":"Transparent flexible capacitors are important in the development of advanced future electronics devices like transparent sensors, electronic devices, high pixel displays, thin film multilayer solar cells and transparent circuit. Transparent conducting films has a composite structure of Aluminium doped zinc Oxide - silver nanowire (AgNWs) is deposited using pulsed laser deposition technique. The resistance of transparent conducting films is 120 Ω/mm when ITO and AgNW network were involved. Transparent capacitors with the dielectric structure of AhO3-TiO2- AI2O3 were fabricated on the composite electrodes, with a capacitance density of 10.1fF μm-2. The broad frequency ranges from 3 kHz to 1 MHz. The flexibility is found to be a maximum of 25mm without changing the capacitance. Transparency of capacitor is demonstrated at an average optical transmittance of over 75–80% in the visible range, and thus the practical application of transparent devices and integrated circuits is obtained.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114922408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ICDCSYST.2018.8605158
Avashesh Dubey, Mridula Gupta, R. Narang, M. Saxena
In this paper, a quantitative comparison study of the CMOS based Double Gate RADFET, Gate All Around (GAA) RADFET, Junctionless Double Gate (JL-DG) RADFET dosimeter and their electrical performance has been carried out. Gamma radiation Model of Sentaurus 3D Device simulator has been used to investigate the trapping detrapping of electron hole due to the moderate dose radiation environment. The impact of the total dose on the threshold voltage and drain current has been addressed. The obtained results indicate improvement in the subthreshold parameters of JL DG RADFET as compared to the conventional DG RADFET and GAA RADFET dosimeter.
本文对CMOS双栅RADFET、GAA型RADFET、JL-DG型无结双栅RADFET剂量计及其电学性能进行了定量比较研究。利用Sentaurus 3D Device模拟器的伽马辐射模型，研究了中等剂量辐射环境下电子空穴的俘获脱陷。讨论了总剂量对阈值电压和漏极电流的影响。所得结果表明，与传统的DG RADFET和GAA RADFET剂量计相比，JL DG RADFET的亚阈值参数有所改善。
{"title":"Comparative Study of CMOS based Dosimeters for Gamma Radiation","authors":"Avashesh Dubey, Mridula Gupta, R. Narang, M. Saxena","doi":"10.1109/ICDCSYST.2018.8605158","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605158","url":null,"abstract":"In this paper, a quantitative comparison study of the CMOS based Double Gate RADFET, Gate All Around (GAA) RADFET, Junctionless Double Gate (JL-DG) RADFET dosimeter and their electrical performance has been carried out. Gamma radiation Model of Sentaurus 3D Device simulator has been used to investigate the trapping detrapping of electron hole due to the moderate dose radiation environment. The impact of the total dose on the threshold voltage and drain current has been addressed. The obtained results indicate improvement in the subthreshold parameters of JL DG RADFET as compared to the conventional DG RADFET and GAA RADFET dosimeter.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114983490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ICDCSYST.2018.8605138
D. NarainPonraj, Esther Christy, A. G., S. G, Monica Sharu
Lung Cancer tops the list among all cancers. According to a study by IASLC (International Association For the study of Lung Cancer) it is found that more than 1.6 million deaths are witnessed every year due to Lung Cancer, which is more than the death rate caused by prostrate, colon and breast cancers combined. Thus there is a need for an early detection followed by early treatment in order to improve the patient's chance of survival. In this paper a Lung Cancer detection model is developed using image processing technique. This model involves three stages to detect the presence of cancer nodule which are preprocessing, feature extraction and classification. The extracted features classify the lung as normal or abnormal with the help of SVM classifier. In this paper we extract texture features using Local Optimal Oriented Pattern(LOOP) and classify them using K-fold cross validation technique. The results obtained are then compared to the results of various binary patterns-LBP(Local Binary Pattern),LBC(Local Binary Count) and LDP(Local Directional Pattern).
{"title":"Analysis of LBP and LOOP Based Textural Feature Extraction for the Classification of CT Lung Images","authors":"D. NarainPonraj, Esther Christy, A. G., S. G, Monica Sharu","doi":"10.1109/ICDCSYST.2018.8605138","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605138","url":null,"abstract":"Lung Cancer tops the list among all cancers. According to a study by IASLC (International Association For the study of Lung Cancer) it is found that more than 1.6 million deaths are witnessed every year due to Lung Cancer, which is more than the death rate caused by prostrate, colon and breast cancers combined. Thus there is a need for an early detection followed by early treatment in order to improve the patient's chance of survival. In this paper a Lung Cancer detection model is developed using image processing technique. This model involves three stages to detect the presence of cancer nodule which are preprocessing, feature extraction and classification. The extracted features classify the lung as normal or abnormal with the help of SVM classifier. In this paper we extract texture features using Local Optimal Oriented Pattern(LOOP) and classify them using K-fold cross validation technique. The results obtained are then compared to the results of various binary patterns-LBP(Local Binary Pattern),LBC(Local Binary Count) and LDP(Local Directional Pattern).","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123977556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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