Pub Date : 2018-03-01DOI: 10.1109/ICDCSYST.2018.8605141
N. Nithin Kumar, P. Vimala
This paper presents a 2D analytical surface potential model and lateral electric field for undoped double gate (DG) tunnel field effect transistors (TFETs). With suitable boundary condition 2D Poisson’s equation is solved by using superposition method. The Surface potential and lateral electric field is modeled by considering mobile charges. The analytical results of the proposed model have been compared with the Silvaco TCAD atlas results. The proposed results are in excellent agreement with the simulation results and having higher performance in small dimensions.
{"title":"Two Dimensional Analytical Potential Model for Double Gate TFETs","authors":"N. Nithin Kumar, P. Vimala","doi":"10.1109/ICDCSYST.2018.8605141","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605141","url":null,"abstract":"This paper presents a 2D analytical surface potential model and lateral electric field for undoped double gate (DG) tunnel field effect transistors (TFETs). With suitable boundary condition 2D Poisson’s equation is solved by using superposition method. The Surface potential and lateral electric field is modeled by considering mobile charges. The analytical results of the proposed model have been compared with the Silvaco TCAD atlas results. The proposed results are in excellent agreement with the simulation results and having higher performance in small dimensions.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133109551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ICDCSYST.2018.8605126
M. Rakshitha, S. Gandhi
In this paper, 2 dimensional (2-D) photonic crystal ring resonator based lx4 and lx8 optical power splitters have been designed and analysed. By using ring resonators and waveguides, the splitter is designed which has nearly equal power at each of the output ports. This equal output power at the output ports are obtained due to the symmetrical structure. Plane wave expansion method is used to calculate the Photonic Bandgap of the structure. FDTD method is used for design, simulation and analysation of the structure. The structure is designed using square lattice with $25times 43$ rods in x-z direction and hence the structure is ultra-compact with an area of $313.2mu m^{2}.$
{"title":"1x4 and 1x8 Photonic crystal ring resonator based Optical Splitters","authors":"M. Rakshitha, S. Gandhi","doi":"10.1109/ICDCSYST.2018.8605126","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605126","url":null,"abstract":"In this paper, 2 dimensional (2-D) photonic crystal ring resonator based lx4 and lx8 optical power splitters have been designed and analysed. By using ring resonators and waveguides, the splitter is designed which has nearly equal power at each of the output ports. This equal output power at the output ports are obtained due to the symmetrical structure. Plane wave expansion method is used to calculate the Photonic Bandgap of the structure. FDTD method is used for design, simulation and analysation of the structure. The structure is designed using square lattice with $25times 43$ rods in x-z direction and hence the structure is ultra-compact with an area of $313.2mu m^{2}.$","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126913442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ICDCSYST.2018.8605071
Pratik P Pandit, L. Arivazhagan, P. Prajoon, J. Rajkumar, J. Ajayan, D. Nirmal
In this work, we analyzed the DC performance of asymmetric AlGaN/GaN High Electron Mobility Transistors (HEMTs) on SiC substarte using Silvaco-TCAD software. The highlights of the proposed HEMT are intrinsic GaN channel, AlN nucleation layer, AIGaN barrier layer and asymmetric gate technology and GaN cap layer. The $mathrm {L}_{mathrm {g}} = 50$ nm proposed HEMT on SiC substrate exhibits a $mathrm {g}_{mathrm {m}_{-}max }$ of 170 mS/mm and $mathrm {I}_{mathrm {D}mathrm {S}_{-}max }$ of 800 mA/mm and breakdown voltage of 550 V. The proposed HEMT on SiC substrate exhibits a threshold voltage of -5V which indicates its D-Mode operation of the device. This excellent DC and breakdown characteristics of the proposed HEMT makes them an excellent candidate for future high power and high frequency applications.
{"title":"DC Performance analysis of AlGaN/GaN HEMT for future High power applications","authors":"Pratik P Pandit, L. Arivazhagan, P. Prajoon, J. Rajkumar, J. Ajayan, D. Nirmal","doi":"10.1109/ICDCSYST.2018.8605071","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605071","url":null,"abstract":"In this work, we analyzed the DC performance of asymmetric AlGaN/GaN High Electron Mobility Transistors (HEMTs) on SiC substarte using Silvaco-TCAD software. The highlights of the proposed HEMT are intrinsic GaN channel, AlN nucleation layer, AIGaN barrier layer and asymmetric gate technology and GaN cap layer. The $mathrm {L}_{mathrm {g}} = 50$ nm proposed HEMT on SiC substrate exhibits a $mathrm {g}_{mathrm {m}_{-}max }$ of 170 mS/mm and $mathrm {I}_{mathrm {D}mathrm {S}_{-}max }$ of 800 mA/mm and breakdown voltage of 550 V. The proposed HEMT on SiC substrate exhibits a threshold voltage of -5V which indicates its D-Mode operation of the device. This excellent DC and breakdown characteristics of the proposed HEMT makes them an excellent candidate for future high power and high frequency applications.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133362731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ICDCSYST.2018.8605153
S. Ramson, Deepthi Bhavanam, Srirupa Draksharam, Ranjeet Kumar, D. Moni, A. Kirubaraj
A variety of technologies provided solution for innumerable problems. But, still human wastes are handled by human beings. Solid waste management is the method of collecting, transporting, processing or dumping, managing and monitoring the waste materials. Radio Frequency Identification (RFID) and Wireless Sensor Networks (WSNs) plays a vital role in the field of solid waste management. A small number of RFID and WSNs based solid waste bin level monitoring systems have been deployed to handle solid wastes. This article presents the review of various bin level monitoring systems with the insight for advanced researches in the field of waste management.
{"title":"Radio Frequency Identification and Sensor Networks based Bin Level Monitoring Systems-A Review","authors":"S. Ramson, Deepthi Bhavanam, Srirupa Draksharam, Ranjeet Kumar, D. Moni, A. Kirubaraj","doi":"10.1109/ICDCSYST.2018.8605153","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605153","url":null,"abstract":"A variety of technologies provided solution for innumerable problems. But, still human wastes are handled by human beings. Solid waste management is the method of collecting, transporting, processing or dumping, managing and monitoring the waste materials. Radio Frequency Identification (RFID) and Wireless Sensor Networks (WSNs) plays a vital role in the field of solid waste management. A small number of RFID and WSNs based solid waste bin level monitoring systems have been deployed to handle solid wastes. This article presents the review of various bin level monitoring systems with the insight for advanced researches in the field of waste management.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130871767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ICDCSYST.2018.8605166
R. Thakur, Pragati Singh
As the technology has been scaling down very rapidly, it is becoming diflicult to isolate the oxide-semiconductor layer to prevent tunneling of carriers to the gate and thus the leakage is becoming a major threat in MOSFET based semiconductor devices for applications in the Nano Regime. In this paper, a method for having a good isolation between Si-SiO2has been shown by replacing the earlier SiO2With High-k. In this study, Hafnium Oxide (HfO2) and Zirconium Oxide (ZrO2) were found to be the good alternatives for Sifh.The device was simulated using Sentaurus TCAD and mathematical calculations were done using MATLAB.
{"title":"Effects of Interface Charge (Qit) and Interface Trap Density (Dit) on A12O3, ZrO2 and HfO2 based Nano Regime Multi-Gate Devices","authors":"R. Thakur, Pragati Singh","doi":"10.1109/ICDCSYST.2018.8605166","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605166","url":null,"abstract":"As the technology has been scaling down very rapidly, it is becoming diflicult to isolate the oxide-semiconductor layer to prevent tunneling of carriers to the gate and thus the leakage is becoming a major threat in MOSFET based semiconductor devices for applications in the Nano Regime. In this paper, a method for having a good isolation between Si-SiO2has been shown by replacing the earlier SiO2With High-k. In this study, Hafnium Oxide (HfO2) and Zirconium Oxide (ZrO2) were found to be the good alternatives for Sifh.The device was simulated using Sentaurus TCAD and mathematical calculations were done using MATLAB.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127376845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, FinFET device with metalloid source/drain and GaAs channel has been proposed for Analog/RF Applications. Drain current, transconductance, intrinsic gain, device efficiency, cut-off frequency, and VIP3 has been analysed by using ATLAS 3D TCAD simulator. A comprehensive comparative analysis has been carried out between FinFET device with and without metalloid source/drain. The drastic enhancement in device performance makes Metalloid-S/D-GaAs FinFET as a ultimate novel device structure for high-frequency applications.
本文提出了一种具有金属状源/漏极和GaAs通道的FinFET器件，用于模拟/射频应用。利用ATLAS 3D TCAD模拟器对漏极电流、跨导、固有增益、器件效率、截止频率和VIP3进行了分析。对具有和不具有类金属源极/漏极的FinFET器件进行了全面的比较分析。器件性能的急剧提高使Metalloid-S/D-GaAs FinFET成为高频应用的终极新型器件结构。
{"title":"Performance Analysis Of Metalloid Source/ Drain GaAs-FinFET For Analog/RF Applications","authors":"Yogesh Pratap, Reshma Sinha, Praveen Pal, Sarul Malik, S. Kabra, Sachin Kumar","doi":"10.1109/ICDCSYST.2018.8605159","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605159","url":null,"abstract":"In this paper, FinFET device with metalloid source/drain and GaAs channel has been proposed for Analog/RF Applications. Drain current, transconductance, intrinsic gain, device efficiency, cut-off frequency, and VIP3 has been analysed by using ATLAS 3D TCAD simulator. A comprehensive comparative analysis has been carried out between FinFET device with and without metalloid source/drain. The drastic enhancement in device performance makes Metalloid-S/D-GaAs FinFET as a ultimate novel device structure for high-frequency applications.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128707432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ICDCSYST.2018.8605149
H. M. Vijay, V. N. Ramakrishnan
Memristor is a nano-electronic device which relates charge and flux. It is an excellent candidate for emerging technologies. Memristor exits as either two- or three-terminal device. In this work, As far as we know to the best of our knowledge we are for the first time proposing four terminal memristor known as double gated memristor. The structure of the double gated memristor resembles double gate MOSFET. The current-voltage analysis of double gated memristor is carried out in this paper work. It is observed that there is an improvement in the current of the double gated memristor in comparison to conventional memristor. It finds important application in analog, digital and neuromorphic circuits.
{"title":"A Novel Approach to Analyze Current-Voltage Characteristics of Double Gated-Memristor","authors":"H. M. Vijay, V. N. Ramakrishnan","doi":"10.1109/ICDCSYST.2018.8605149","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605149","url":null,"abstract":"Memristor is a nano-electronic device which relates charge and flux. It is an excellent candidate for emerging technologies. Memristor exits as either two- or three-terminal device. In this work, As far as we know to the best of our knowledge we are for the first time proposing four terminal memristor known as double gated memristor. The structure of the double gated memristor resembles double gate MOSFET. The current-voltage analysis of double gated memristor is carried out in this paper work. It is observed that there is an improvement in the current of the double gated memristor in comparison to conventional memristor. It finds important application in analog, digital and neuromorphic circuits.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125737671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ICDCSYST.2018.8605068
T. A. Jones, Vidhya Priyadarshni, Angelin Esther, R. Sowjanya, Ranso
In recent years development of miniaturized patch antenna for quality application plays an important role. This paper presents the planning of rectangular microstrip antenna with 2 completely different slots appropriate for future Global Positioning System(GPS). The planned antenna operates at frequency at L1 (1.559 GHz-1.610GHz). The designs are based on an equivalent patch dimensions loaded with 2 completely different slots of U-shaped slot and inverted H-Shaped slot. The experimental results show that this style is ideally fitted to GPS mobile communications. Simulation are done using FEKO software.
{"title":"Slotted Antenna Deign For GPS Applications Using Feko Software","authors":"T. A. Jones, Vidhya Priyadarshni, Angelin Esther, R. Sowjanya, Ranso","doi":"10.1109/ICDCSYST.2018.8605068","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605068","url":null,"abstract":"In recent years development of miniaturized patch antenna for quality application plays an important role. This paper presents the planning of rectangular microstrip antenna with 2 completely different slots appropriate for future Global Positioning System(GPS). The planned antenna operates at frequency at L1 (1.559 GHz-1.610GHz). The designs are based on an equivalent patch dimensions loaded with 2 completely different slots of U-shaped slot and inverted H-Shaped slot. The experimental results show that this style is ideally fitted to GPS mobile communications. Simulation are done using FEKO software.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121513537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ICDCSYST.2018.8605065
P. Umasankar, V. Thiagarasu
The most common death is due to the condition that affects the heart is Cardiovascular disease (CVD). The inadequate oxygen to the heart leads to the symptoms like fatigue and chest pain (angina). This paper proposes a framework which incorporates the pre-processing step, Interval Vague set, Fuzzy Association Rule mining and Fuzzy Correlation rule mining for the decision making process. In this paper, the proposed framework mainly focused on the criteria that are causing the heart attack among the people. The pre-processing step is used to reduce the size of the heart disease dataset. Using the Rule Mining algorithm, the set of rules are generated for the prediction of heart diseases based on the selected criteria. Interval vague set is used to solve the decision making problem among the doctors regarding the heart disease among the patient who are in the hesitant state.
{"title":"Decision Support System for Heart Disease Diagnosis Using Interval Vague Set and Fuzzy Association Rule Mining","authors":"P. Umasankar, V. Thiagarasu","doi":"10.1109/ICDCSYST.2018.8605065","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605065","url":null,"abstract":"The most common death is due to the condition that affects the heart is Cardiovascular disease (CVD). The inadequate oxygen to the heart leads to the symptoms like fatigue and chest pain (angina). This paper proposes a framework which incorporates the pre-processing step, Interval Vague set, Fuzzy Association Rule mining and Fuzzy Correlation rule mining for the decision making process. In this paper, the proposed framework mainly focused on the criteria that are causing the heart attack among the people. The pre-processing step is used to reduce the size of the heart disease dataset. Using the Rule Mining algorithm, the set of rules are generated for the prediction of heart diseases based on the selected criteria. Interval vague set is used to solve the decision making problem among the doctors regarding the heart disease among the patient who are in the hesitant state.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116768784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-17DOI: 10.1109/ICDCSYST.2018.8605140
M. Chaudhary
This paper presents a novel RF load pull test setup that allows for the presentation of user specified impedances at both the RF (Radio frequency) and IF (intermediate frequency) domain, to enable the investigation of linear high efficiency power amplifier design using measurement data. The RF load pull impedances at the fundamental, and second harmonic were set to produce a derivative of a class J amplifier to emulate a high efficiency mode of operation. The IF impedance up to the fifth IF product was then varied to quantify its effect on linearity. To enable this investigation a multi-sine stimuli was synthesized using multiple signal sources all phase locked to reference local oscillator. It was found that a greater than 10dB improvement in linearity was achieved by actively injecting a signal at IF that can be applied in an envelope tracking system.
{"title":"Synthesis of Broadband IF and RF Impedances under Multi-sine Stimuli","authors":"M. Chaudhary","doi":"10.1109/ICDCSYST.2018.8605140","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605140","url":null,"abstract":"This paper presents a novel RF load pull test setup that allows for the presentation of user specified impedances at both the RF (Radio frequency) and IF (intermediate frequency) domain, to enable the investigation of linear high efficiency power amplifier design using measurement data. The RF load pull impedances at the fundamental, and second harmonic were set to produce a derivative of a class J amplifier to emulate a high efficiency mode of operation. The IF impedance up to the fifth IF product was then varied to quantify its effect on linearity. To enable this investigation a multi-sine stimuli was synthesized using multiple signal sources all phase locked to reference local oscillator. It was found that a greater than 10dB improvement in linearity was achieved by actively injecting a signal at IF that can be applied in an envelope tracking system.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-02-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115812560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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