Pub Date : 2018-03-01DOI: 10.1109/ICDCSYST.2018.8605162
R. Bank, Soumyashree Mangaraj
Adders are basic integral part of arithmetic circuits. The adders have been realized with two styles: fixed stage and variable stage size. This paper presents the correlation investigation of execution examination of 64-bit Carry Lookahead Adders utilizing conventional and hierarchical structure styles with fixed stages and variable stages. We utilize different diverse parameter to evaluate conventional carry lookahead adder (CLA) and hierarchical carry lookahead adder (HCLA) and variable stage carry lookahead adder. Our outline is actualized into Zedboard Xilinx Zynq XC7Z020-1CLG484. Our intrigued of investigation are delay, area, and power. In this paper we show conventional CLA required small area using radix-2, while in hierarchical CLA delay is diminished to a great extent. Furthermore, we demonstrated variable stages CLA would be able to tradeoff between the area, delay and power.
{"title":"Design and Implementation of 64-bit Carry Lookahead Adders Using Fixed and Variable Stage Structure","authors":"R. Bank, Soumyashree Mangaraj","doi":"10.1109/ICDCSYST.2018.8605162","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605162","url":null,"abstract":"Adders are basic integral part of arithmetic circuits. The adders have been realized with two styles: fixed stage and variable stage size. This paper presents the correlation investigation of execution examination of 64-bit Carry Lookahead Adders utilizing conventional and hierarchical structure styles with fixed stages and variable stages. We utilize different diverse parameter to evaluate conventional carry lookahead adder (CLA) and hierarchical carry lookahead adder (HCLA) and variable stage carry lookahead adder. Our outline is actualized into Zedboard Xilinx Zynq XC7Z020-1CLG484. Our intrigued of investigation are delay, area, and power. In this paper we show conventional CLA required small area using radix-2, while in hierarchical CLA delay is diminished to a great extent. Furthermore, we demonstrated variable stages CLA would be able to tradeoff between the area, delay and power.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117148353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ICDCSyst.2018.8605157
Ajay, S. Chander, Mridula Gupta
In this paper, a systematic studies have been performed on the different architectures of AlGaN/GaN high-electron-mobility transistors (HEMTs) through Sentaurus simulation software. The DC characteristics have been investigated for three different architectures of AlGaN/GaN HEMTs (Common Drain, Common Source and Conventional HEMTs). The common drain (CD) AlGaN/GaN HEMT shows the better DC characteristics in comparison to the common source (CS) AlGaN/GaN HEMT and conventional AlGaN/GaN HEMT.
{"title":"Analysis of DC Characteristics of AlGaN/GaN HEMTs: Simulation","authors":"Ajay, S. Chander, Mridula Gupta","doi":"10.1109/ICDCSyst.2018.8605157","DOIUrl":"https://doi.org/10.1109/ICDCSyst.2018.8605157","url":null,"abstract":"In this paper, a systematic studies have been performed on the different architectures of AlGaN/GaN high-electron-mobility transistors (HEMTs) through Sentaurus simulation software. The DC characteristics have been investigated for three different architectures of AlGaN/GaN HEMTs (Common Drain, Common Source and Conventional HEMTs). The common drain (CD) AlGaN/GaN HEMT shows the better DC characteristics in comparison to the common source (CS) AlGaN/GaN HEMT and conventional AlGaN/GaN HEMT.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115398631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ICDCSYST.2018.8605175
S. Janakiraman, P. Roshini, Sundararaman Rajagopalan, K. Thenmozhi, Rengarajan Amirtharajan
Internet advancements and the arrival of new embedded gadgets have radically raised the information sharing in the form of images. In turn, the encryption algorithms have been widely used to secure images. Most of these image encryption algorithms have to run on resource-constrained devices that demand less computational complexity. In this regard, the algorithm proposed in this paper satisfies the need for a computationally less complex image encryption process with its simpler and efficient key generation procedure. The analysis of the implementation results in terms of statistical parameters in addition to its ability to withstand differential attacks validates the security level of the proposed Iightweight image encryption algorithm.
{"title":"Permutated Symmetric Key for Perfect Lightweight Image Encryption","authors":"S. Janakiraman, P. Roshini, Sundararaman Rajagopalan, K. Thenmozhi, Rengarajan Amirtharajan","doi":"10.1109/ICDCSYST.2018.8605175","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605175","url":null,"abstract":"Internet advancements and the arrival of new embedded gadgets have radically raised the information sharing in the form of images. In turn, the encryption algorithms have been widely used to secure images. Most of these image encryption algorithms have to run on resource-constrained devices that demand less computational complexity. In this regard, the algorithm proposed in this paper satisfies the need for a computationally less complex image encryption process with its simpler and efficient key generation procedure. The analysis of the implementation results in terms of statistical parameters in addition to its ability to withstand differential attacks validates the security level of the proposed Iightweight image encryption algorithm.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121158915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ICDCSYST.2018.8605154
M. Elangovan, K. Gunavathi
Carbon Nano Tube Field Effect Transistor (CNTFET) is a best futuristic device for nano scale range VLSI design than MOSFETs. This is due to the favourable physical properties of CNTFET. In this paper we present the comparative Stability analysis of a CNTFET based six transistor Static Random Access Memory (6T SRAM) cell for single nano tube CNTFET and multiple nano tubes CNTFET. The SRAM cell stability is measured by Static Noise Margin (SNM) of the cell. The SNM of 6T SRAM is also analysed for different chiral vectors. The comparison shows that the single tube and low chiral vector values provides high stability of CNTFET 6T SRAM cell than multiple tubes with high chiral vector. The simulation is carried out with 32nm technology.
{"title":"Stability Analysis of 6T CNTFET SRAM Cell for Single and Multiple CNTs","authors":"M. Elangovan, K. Gunavathi","doi":"10.1109/ICDCSYST.2018.8605154","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605154","url":null,"abstract":"Carbon Nano Tube Field Effect Transistor (CNTFET) is a best futuristic device for nano scale range VLSI design than MOSFETs. This is due to the favourable physical properties of CNTFET. In this paper we present the comparative Stability analysis of a CNTFET based six transistor Static Random Access Memory (6T SRAM) cell for single nano tube CNTFET and multiple nano tubes CNTFET. The SRAM cell stability is measured by Static Noise Margin (SNM) of the cell. The SNM of 6T SRAM is also analysed for different chiral vectors. The comparison shows that the single tube and low chiral vector values provides high stability of CNTFET 6T SRAM cell than multiple tubes with high chiral vector. The simulation is carried out with 32nm technology.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133712050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ICDCSYST.2018.8605123
C. Sarumathi, T. Neebha, M. Nesasudha
Implantable antennas have shown novel developments in wireless body centric paradigm. Miniaturization concept in the antenna is key to its success as it provides compactness to the user. The design and development of implantable antenna also deals with other issues like biocompatibility, propagation, detuning effects, patient safety etc. Hence miniaturization techniques are incorporated with antenna to fulfill a tradeoff between size and performance. This work aims to examine the miniaturization techniques and performance evaluation available for body area network (BAN) antennas in ISM band. In this work we consider strip loading techniques with miniaturized profile suitable for medical application. Notably, strip loaded at the center of Complementary split ring resonator (CSRR) structure has high degree of miniaturization when fed by a directional microstrip line. Five types of low profile serpentine antennas integrated with CSRR structures have been consider for analysis of medical implantable devices. Analysis of these design structure indicated a strong relation of resonance frequency with antenna geometry and the position of loaded strip. Finally, the designed S-CSRR5 structure exhibited good response in terms of resonance, impedance matching and gain. Measurement results also showed good agreement with the simulated design.
{"title":"On The Design Of Miniaturized Implantable Serpentine Radiating Structures Using Strip Loading Method","authors":"C. Sarumathi, T. Neebha, M. Nesasudha","doi":"10.1109/ICDCSYST.2018.8605123","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605123","url":null,"abstract":"Implantable antennas have shown novel developments in wireless body centric paradigm. Miniaturization concept in the antenna is key to its success as it provides compactness to the user. The design and development of implantable antenna also deals with other issues like biocompatibility, propagation, detuning effects, patient safety etc. Hence miniaturization techniques are incorporated with antenna to fulfill a tradeoff between size and performance. This work aims to examine the miniaturization techniques and performance evaluation available for body area network (BAN) antennas in ISM band. In this work we consider strip loading techniques with miniaturized profile suitable for medical application. Notably, strip loaded at the center of Complementary split ring resonator (CSRR) structure has high degree of miniaturization when fed by a directional microstrip line. Five types of low profile serpentine antennas integrated with CSRR structures have been consider for analysis of medical implantable devices. Analysis of these design structure indicated a strong relation of resonance frequency with antenna geometry and the position of loaded strip. Finally, the designed S-CSRR5 structure exhibited good response in terms of resonance, impedance matching and gain. Measurement results also showed good agreement with the simulated design.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134311242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/icdcsyst.2018.8605120
N. Amamath, H. M. Vijay, S. V. V. Satyanarayana, N. Ramakrishnan, Sridevi Sriadibhatla
CAM (Content Addressable Memory) is one of the promising memory family used in high speed search applications. CAM power dissipation is more due to large number of search operation. NAND and NOR type match-line CAMs are useful in low power applications but they have drawbacks like charge sharing and short circuit at match-lines of the CAM array. Recently the CAM cell was implemented with free of pre-charge circuit by adding a control bit in order to boost-up the match-line only, but not the internal SRAM. In this paper, we are proposing a precharge-free PMOS logic based CAM cell and comparing the metrics of proposed CAM cell with precharge-free NMOS based CAM cell in terms of delay, power and Power-Delay Product (PDP). The simulations are carried out in technology node Cadence design environment. The simulation results shows the PDP of proposed design is 91.17% reduction than NMOS based precharge-free CAM. We also performed a radiation study on both PMOS and NMOS based precharge-free CAM cell. Match-line of PMOS based CAM cell is more sensitive than Match-line of NMOS based CAM cell. The threshold current value of PMOS based CAM cell is 100μA and for NMOS based CAM cell is 1.3mA.
{"title":"SEU sensitivity analysis of low power, precharge-free modified CAM cell","authors":"N. Amamath, H. M. Vijay, S. V. V. Satyanarayana, N. Ramakrishnan, Sridevi Sriadibhatla","doi":"10.1109/icdcsyst.2018.8605120","DOIUrl":"https://doi.org/10.1109/icdcsyst.2018.8605120","url":null,"abstract":"CAM (Content Addressable Memory) is one of the promising memory family used in high speed search applications. CAM power dissipation is more due to large number of search operation. NAND and NOR type match-line CAMs are useful in low power applications but they have drawbacks like charge sharing and short circuit at match-lines of the CAM array. Recently the CAM cell was implemented with free of pre-charge circuit by adding a control bit in order to boost-up the match-line only, but not the internal SRAM. In this paper, we are proposing a precharge-free PMOS logic based CAM cell and comparing the metrics of proposed CAM cell with precharge-free NMOS based CAM cell in terms of delay, power and Power-Delay Product (PDP). The simulations are carried out in technology node Cadence design environment. The simulation results shows the PDP of proposed design is 91.17% reduction than NMOS based precharge-free CAM. We also performed a radiation study on both PMOS and NMOS based precharge-free CAM cell. Match-line of PMOS based CAM cell is more sensitive than Match-line of NMOS based CAM cell. The threshold current value of PMOS based CAM cell is 100μA and for NMOS based CAM cell is 1.3mA.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130750484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ICDCSYST.2018.8605131
S. Priya, B. Raju, B. Benita, Dharani
The low power adder is designed in this paper using Carry-Select Modified-Tree(CSMT) adder for fast carry generation and for binary addition. The results are analyzed and the performances are compared. This adder makes the use of multiplexers. The greatest advantage of this adder is that it uses very few multiplexers and consumes least amount of energy for specified latency. Carry-select addition is used in the architecture. The adder is implemented using Multiplexer block and longer carry-select adders are be replaced by modified tree structure to maintain the multiplexer complexity. The CSMT architecture in adder can reduce the multiplexer complexity. By using this concept the 3 8 % power is reduced when compared to the conventional adder.
{"title":"A Design of low power Adders","authors":"S. Priya, B. Raju, B. Benita, Dharani","doi":"10.1109/ICDCSYST.2018.8605131","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605131","url":null,"abstract":"The low power adder is designed in this paper using Carry-Select Modified-Tree(CSMT) adder for fast carry generation and for binary addition. The results are analyzed and the performances are compared. This adder makes the use of multiplexers. The greatest advantage of this adder is that it uses very few multiplexers and consumes least amount of energy for specified latency. Carry-select addition is used in the architecture. The adder is implemented using Multiplexer block and longer carry-select adders are be replaced by modified tree structure to maintain the multiplexer complexity. The CSMT architecture in adder can reduce the multiplexer complexity. By using this concept the 3 8 % power is reduced when compared to the conventional adder.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127614316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ICDCSYST.2018.8605147
R. Sahoo, R. R. Mishra
Now a day’s graphene is of keen interest for its application in carbon nanotube Field Effect Transistors, Graphene Transistors etc. Graphene is a single layer of graphite which is 2D in structure. In this paper, we are focusing on the thermal property of graphene. For 3D crystalline graphite and 2D graphene layers, the dominant contribution for the heat capacity comes from the phonons. This is because the electronic contribution to the heat capacity is very small and hence can be essentially neglected, even at low temperatures. In this paper we have calculated the lattice specific heat of graphene in a simpler method and studied its variation with respect to the number of nearest neighbors considered for the calculation as well as temperature.
{"title":"Lattice Specific Heat of Graphene","authors":"R. Sahoo, R. R. Mishra","doi":"10.1109/ICDCSYST.2018.8605147","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605147","url":null,"abstract":"Now a day’s graphene is of keen interest for its application in carbon nanotube Field Effect Transistors, Graphene Transistors etc. Graphene is a single layer of graphite which is 2D in structure. In this paper, we are focusing on the thermal property of graphene. For 3D crystalline graphite and 2D graphene layers, the dominant contribution for the heat capacity comes from the phonons. This is because the electronic contribution to the heat capacity is very small and hence can be essentially neglected, even at low temperatures. In this paper we have calculated the lattice specific heat of graphene in a simpler method and studied its variation with respect to the number of nearest neighbors considered for the calculation as well as temperature.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114897575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ICDCSYST.2018.8605139
Krishna Chaitanya Sankisa, R. Sahoo, S. K. Sahoo
The Adder is one of the most important and basic units of arithmetic logics which is used to design many complex circuits. Till now, all arithmetic circuits are mostly use CMOS circuits for binary logic implementation. Recently Carbon nanotube field effect transistor (CNTFET) has attracted many researchers as its threshold voltage can be varied by changing the diameter of carbon nanotube which makes it useful for designing multivalued logic circuits. Exploring this property of CNTFET, few researchers have designed ternary adders. In this work, first time a Quaternary full adder using CNTFET based of circuit is proposed. The proposed circuit is designed based on the conventional CMOS architecture with utilization of inherent binary nature (0,1) of input carry signal. Since voltage at the output of the dynamic logic circuit is stored on a parasitic capacitance, a quaternary keeper circuit is used to alleviate charge sharing problems. The proposed design of Quaternary full adder circuit is simulated using HSPICE simulator with 14 nm Stanford CNTFET model. This adder consumes 103.18 nw power and has delay of 17.46 psec. This is a first effort to design a quaternary logic adder circuit.
{"title":"A CNTFET Based Quaternary Ful1 Adder","authors":"Krishna Chaitanya Sankisa, R. Sahoo, S. K. Sahoo","doi":"10.1109/ICDCSYST.2018.8605139","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605139","url":null,"abstract":"The Adder is one of the most important and basic units of arithmetic logics which is used to design many complex circuits. Till now, all arithmetic circuits are mostly use CMOS circuits for binary logic implementation. Recently Carbon nanotube field effect transistor (CNTFET) has attracted many researchers as its threshold voltage can be varied by changing the diameter of carbon nanotube which makes it useful for designing multivalued logic circuits. Exploring this property of CNTFET, few researchers have designed ternary adders. In this work, first time a Quaternary full adder using CNTFET based of circuit is proposed. The proposed circuit is designed based on the conventional CMOS architecture with utilization of inherent binary nature (0,1) of input carry signal. Since voltage at the output of the dynamic logic circuit is stored on a parasitic capacitance, a quaternary keeper circuit is used to alleviate charge sharing problems. The proposed design of Quaternary full adder circuit is simulated using HSPICE simulator with 14 nm Stanford CNTFET model. This adder consumes 103.18 nw power and has delay of 17.46 psec. This is a first effort to design a quaternary logic adder circuit.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121893285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ICDCSYST.2018.8605073
G. Thriveni, K. Ghosh
A numerical model using self consistent Poisson's equation solver is presented to elucidate the potential profile and current-voltage characteristics of double gate nanoMOSFET using 32nm technology. Here we have explored the performance of the nanodevice with different dielectric layers. The focus of this work is to identify the type of gate dielectric material which is capable enough to control the electrostatics across the channel through gate bias and reduce the tunneling current. We find that $mathrm {T}mathrm {i}mathrm {O}_{2}$ layer having k=80 produces higher tunneling current through gate leakage although it exhibited stronger gate control on the channel conduction. A combination of $mathrm {T}mathrm {i}mathrm {O}_{2}$ and $mathrm {S}mathrm {i}mathrm {O}_{2}$ dielectric layers is proposed to mitigate tunnelling in these devices and improve its performance.
{"title":"Choice of Gate Insulator for Effective Gate Electrostatics in Double Gate Nanoscale Mosfet","authors":"G. Thriveni, K. Ghosh","doi":"10.1109/ICDCSYST.2018.8605073","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605073","url":null,"abstract":"A numerical model using self consistent Poisson's equation solver is presented to elucidate the potential profile and current-voltage characteristics of double gate nanoMOSFET using 32nm technology. Here we have explored the performance of the nanodevice with different dielectric layers. The focus of this work is to identify the type of gate dielectric material which is capable enough to control the electrostatics across the channel through gate bias and reduce the tunneling current. We find that $mathrm {T}mathrm {i}mathrm {O}_{2}$ layer having k=80 produces higher tunneling current through gate leakage although it exhibited stronger gate control on the channel conduction. A combination of $mathrm {T}mathrm {i}mathrm {O}_{2}$ and $mathrm {S}mathrm {i}mathrm {O}_{2}$ dielectric layers is proposed to mitigate tunnelling in these devices and improve its performance.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127615256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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