Pub Date : 1997-06-12DOI: 10.1109/VLSIC.1997.623822
Komurasaki, Sasaki, Miki
This paper describes a 2.0V 1.9GHz Si down-mixer with LC phase shifter in 20GHz bipolar process. In this circuit a lower emitter-coupled pair in a Gilbert cell is removed to enable low voltage operation, and instead of it an LC phase shifter is inserted between two current sources. It acts as a 180 degrees phase shifter, and keeps both high conversion gain and low distortion. The experimental results show conversion gain of 7.0dB and the 3rd-order intercept point of -1.OdBm are realized at 2.0V.
{"title":"A 2V 1.9GHz Si Down-mixer With LC Phase Shifter","authors":"Komurasaki, Sasaki, Miki","doi":"10.1109/VLSIC.1997.623822","DOIUrl":"https://doi.org/10.1109/VLSIC.1997.623822","url":null,"abstract":"This paper describes a 2.0V 1.9GHz Si down-mixer with LC phase shifter in 20GHz bipolar process. In this circuit a lower emitter-coupled pair in a Gilbert cell is removed to enable low voltage operation, and instead of it an LC phase shifter is inserted between two current sources. It acts as a 180 degrees phase shifter, and keeps both high conversion gain and low distortion. The experimental results show conversion gain of 7.0dB and the 3rd-order intercept point of -1.OdBm are realized at 2.0V.","PeriodicalId":175678,"journal":{"name":"Symposium 1997 on VLSI Circuits","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132522899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-12DOI: 10.1109/VLSIC.1997.623838
Larsson, Nicol
{"title":"Self-adjusting Bit-precision For Low-power Digital Filters","authors":"Larsson, Nicol","doi":"10.1109/VLSIC.1997.623838","DOIUrl":"https://doi.org/10.1109/VLSIC.1997.623838","url":null,"abstract":"","PeriodicalId":175678,"journal":{"name":"Symposium 1997 on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131341074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-12DOI: 10.1109/VLSIC.1997.623832
Weinan Gao, Snelgrove
This paper presents a second-order LC bandpass AZ modulator implemented in a 0.5 pm bipolar process for digitizing RF and high IF signals. It employs an integrated LC resonator with active Q-enhancement and two non-return-to-zero digital-to-analog pulse shaping feedback loops. The modulator test chip achieves a signal-to-noise ratio of 56 dB over a 200 kHz bandwidth for converting a 950 MHz signal, and dissipates 135 mW with a 5-V supply. Introduction Digitizing signals early in a receiver, at a high IF or even in the RF stage, makes for flexibility and low component count at the cost of demanding specifications on the analog-to-digita1 (A/D) converters [ 11 [2]. In this paper, an integrated second-order LC bandpass AZ modulator (BPAZM) implemented in a 0.5 pm bipolar process that converts 950 MHz RF signals with sampling rates of 3.8 GHz is explored. The modulator is built with an active Q-enhanced monolithic LC resonator and non-return-to-zero digital-to-analog (DAC) pulse shaping feedback loops. This modulator is a proof-of-concept prototype, showing a fully monolithic active-LC AX modulator for the first time, and showing GHz bandpass operation for the first time. A commercial version would probably have higher order and feature multi-bit quantization. These circuits can be used to digitize IF signals for systems with carriers in the 5-30 GHz range such as LMCSLMDS (“wireless cable”) and wireless LAN. If re-engineered for increased sensitivity, they might even be applied to directly convert RF signals for microcell base stations. Modulator Architecture and Circuit Design To approach the speed required for RF direct A/D conversion, a continuous-time technique based on integrated LC resonators is utilized in the work. Fig. 1 shows a block diagram of our second-order LC bandpass AZ modulator. Transconductor G, translates the input differential voltage to an output differential current which is summed with DAC feedback switching currents and then fed into the differential LC resonators. Transconductor G, is placed in positive feedback to operate as a negative resistor for compensating the losses in the monolithic inductors. The clocked comparator acts as a signal sampler and one-bit quantizer. The comparator output signal is latched twice (for one full clock delay) for one DAC feedback loop and three times (one and a half clock delays) for another feedback loop before it is used for noise-shaping, Feedback DAC pulse shaping coefficients are adjusted by tuning DAC switching currents to achieve the right noise-shaping transfer function and to compensate timedomain nonidealities [3]. The differential LC tanks plus transconductor G, and transconductor G, give a second-order bandpass filter response with Q-enhancement. A multi-tanh doublet using unbalanced series-diode-connected differential pairs proposed in [4] is used to implement G, for obtaining reasonable linear range with tunability. The ratioed transistors are formed by connecting four transis
{"title":"A 950MHz Second-order Integrated LC Bandpass /spl alpha/spl sigma/ Modulator","authors":"Weinan Gao, Snelgrove","doi":"10.1109/VLSIC.1997.623832","DOIUrl":"https://doi.org/10.1109/VLSIC.1997.623832","url":null,"abstract":"This paper presents a second-order LC bandpass AZ modulator implemented in a 0.5 pm bipolar process for digitizing RF and high IF signals. It employs an integrated LC resonator with active Q-enhancement and two non-return-to-zero digital-to-analog pulse shaping feedback loops. The modulator test chip achieves a signal-to-noise ratio of 56 dB over a 200 kHz bandwidth for converting a 950 MHz signal, and dissipates 135 mW with a 5-V supply. Introduction Digitizing signals early in a receiver, at a high IF or even in the RF stage, makes for flexibility and low component count at the cost of demanding specifications on the analog-to-digita1 (A/D) converters [ 11 [2]. In this paper, an integrated second-order LC bandpass AZ modulator (BPAZM) implemented in a 0.5 pm bipolar process that converts 950 MHz RF signals with sampling rates of 3.8 GHz is explored. The modulator is built with an active Q-enhanced monolithic LC resonator and non-return-to-zero digital-to-analog (DAC) pulse shaping feedback loops. This modulator is a proof-of-concept prototype, showing a fully monolithic active-LC AX modulator for the first time, and showing GHz bandpass operation for the first time. A commercial version would probably have higher order and feature multi-bit quantization. These circuits can be used to digitize IF signals for systems with carriers in the 5-30 GHz range such as LMCSLMDS (“wireless cable”) and wireless LAN. If re-engineered for increased sensitivity, they might even be applied to directly convert RF signals for microcell base stations. Modulator Architecture and Circuit Design To approach the speed required for RF direct A/D conversion, a continuous-time technique based on integrated LC resonators is utilized in the work. Fig. 1 shows a block diagram of our second-order LC bandpass AZ modulator. Transconductor G, translates the input differential voltage to an output differential current which is summed with DAC feedback switching currents and then fed into the differential LC resonators. Transconductor G, is placed in positive feedback to operate as a negative resistor for compensating the losses in the monolithic inductors. The clocked comparator acts as a signal sampler and one-bit quantizer. The comparator output signal is latched twice (for one full clock delay) for one DAC feedback loop and three times (one and a half clock delays) for another feedback loop before it is used for noise-shaping, Feedback DAC pulse shaping coefficients are adjusted by tuning DAC switching currents to achieve the right noise-shaping transfer function and to compensate timedomain nonidealities [3]. The differential LC tanks plus transconductor G, and transconductor G, give a second-order bandpass filter response with Q-enhancement. A multi-tanh doublet using unbalanced series-diode-connected differential pairs proposed in [4] is used to implement G, for obtaining reasonable linear range with tunability. The ratioed transistors are formed by connecting four transis","PeriodicalId":175678,"journal":{"name":"Symposium 1997 on VLSI Circuits","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117237672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The proposed PCCL (Pass-TransistodCMOS Collaborated Logic) aims at superior aredpoweridelay to either conventional CMOS or pass-transistor circuits irrespective of the logic function. The PCCL uses both pass-transistors and CMOSs in a logic block. We have found full potential of both circuits are derived by our new design flow, i.e., full pass-transistor circuit construction followed by partial replacement with CMOS. Unique f e a m is that one can flexibly optimize poweriarea t r a d e d point by changing the ratio of passtransistors. Benchmark test of random logics selected from a microprocessor showed that it is possible to reduce the area by about 20% and the power by about 40% compared to conventional CMOS circuits without any delay penalty.
{"title":"Pass-transistor/CMOS Collaborated Logic: The Best Of Both Worlds","authors":"Yamashita, Yano, Sasaki, Akita, Chikata, Rikino, Seki","doi":"10.1109/VLSIC.1997.623787","DOIUrl":"https://doi.org/10.1109/VLSIC.1997.623787","url":null,"abstract":"The proposed PCCL (Pass-TransistodCMOS Collaborated Logic) aims at superior aredpoweridelay to either conventional CMOS or pass-transistor circuits irrespective of the logic function. The PCCL uses both pass-transistors and CMOSs in a logic block. We have found full potential of both circuits are derived by our new design flow, i.e., full pass-transistor circuit construction followed by partial replacement with CMOS. Unique f e a m is that one can flexibly optimize poweriarea t r a d e d point by changing the ratio of passtransistors. Benchmark test of random logics selected from a microprocessor showed that it is possible to reduce the area by about 20% and the power by about 40% compared to conventional CMOS circuits without any delay penalty.","PeriodicalId":175678,"journal":{"name":"Symposium 1997 on VLSI Circuits","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124548734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-12DOI: 10.1109/VLSIC.1997.623816
Haraguchi, Wada, Arita
This paper proposes a new hicrarchical sensing scheme (HSS) that realizes stability in READ/WRITE operation for a small SRAM memory cell. By adopting the HSS, highdensity and low-voltage operation SRAMs with a small diesize, which is suitable for mobile multi-media devices, can be realized. The HSS makes best use of Cb/Cs relation in the circuit design. The simulation show that the HSS SRAM functions satisfactory with a cell ratio of 1.5 (< 50% of conventional) at Vcc = 3V and 2.5 at Vcc = 1.8V. 1, Introduct ion As portable machinery such as handy terminals and lap-top personal computers increase their market share, the demand for high-density and low-voltage operation memories has increased. A large cell ratio such as 3 to 4 is necessary for stablc memory cell operation. Therefore, 3 to 4 times large transistor has to be integrated in a memory cell. Because of this large cell ratio requirement, it is difficult to realize a high-density SRAM. For a low-voltage operation, the six-transistor full-CMOS cell [l] or the boosted word line technique [21 are used. These technologies, however, require a larger die size or elaborated circuits and fabrication processes. This paper proposes a hierarchical sensing scheme (HSS) that make both high-density and low-voltage operation possible for SRAMs with smaller memory cells. 2. Hierarchical Sensine Scheme (HSS)
{"title":"A Hierarchical Sensing Scheme (HSS) Of High-density And Low-voltage Operation SRAMs","authors":"Haraguchi, Wada, Arita","doi":"10.1109/VLSIC.1997.623816","DOIUrl":"https://doi.org/10.1109/VLSIC.1997.623816","url":null,"abstract":"This paper proposes a new hicrarchical sensing scheme (HSS) that realizes stability in READ/WRITE operation for a small SRAM memory cell. By adopting the HSS, highdensity and low-voltage operation SRAMs with a small diesize, which is suitable for mobile multi-media devices, can be realized. The HSS makes best use of Cb/Cs relation in the circuit design. The simulation show that the HSS SRAM functions satisfactory with a cell ratio of 1.5 (< 50% of conventional) at Vcc = 3V and 2.5 at Vcc = 1.8V. 1, Introduct ion As portable machinery such as handy terminals and lap-top personal computers increase their market share, the demand for high-density and low-voltage operation memories has increased. A large cell ratio such as 3 to 4 is necessary for stablc memory cell operation. Therefore, 3 to 4 times large transistor has to be integrated in a memory cell. Because of this large cell ratio requirement, it is difficult to realize a high-density SRAM. For a low-voltage operation, the six-transistor full-CMOS cell [l] or the boosted word line technique [21 are used. These technologies, however, require a larger die size or elaborated circuits and fabrication processes. This paper proposes a hierarchical sensing scheme (HSS) that make both high-density and low-voltage operation possible for SRAMs with smaller memory cells. 2. Hierarchical Sensine Scheme (HSS)","PeriodicalId":175678,"journal":{"name":"Symposium 1997 on VLSI Circuits","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127987020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-12DOI: 10.1109/VLSIC.1997.623831
Saeki, Nakamura, Shimizu
This paper demonstrates that an Interleaved Synchronous Mirror delay (I-SMD) drastically reduces jitter in CMOS digital clock generators. I-SMD jitter reduction process consists of (1) SMD's inherent characteristics, (2) interleaving, and (3) their synergistic jitter suppression effect using an OR type MUX. Simulation results based on a tpd=300ps CMOS process demonstrate that the quadruple I- SMD achieves a jitter=lOps. The results also demonstrate that an optimized I-SMD reduces jitter without increasing circuit size or power consumption.
{"title":"A 10ps Jitter 2 Clock Cycle Lock Time Cmos Digital Clock Generator Based On An Interleaved Synchronous Mirror Delay Scheme","authors":"Saeki, Nakamura, Shimizu","doi":"10.1109/VLSIC.1997.623831","DOIUrl":"https://doi.org/10.1109/VLSIC.1997.623831","url":null,"abstract":"This paper demonstrates that an Interleaved Synchronous Mirror delay (I-SMD) drastically reduces jitter in CMOS digital clock generators. I-SMD jitter reduction process consists of (1) SMD's inherent characteristics, (2) interleaving, and (3) their synergistic jitter suppression effect using an OR type MUX. Simulation results based on a tpd=300ps CMOS process demonstrate that the quadruple I- SMD achieves a jitter=lOps. The results also demonstrate that an optimized I-SMD reduces jitter without increasing circuit size or power consumption.","PeriodicalId":175678,"journal":{"name":"Symposium 1997 on VLSI Circuits","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128146254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：