Symposium 1997 on VLSI Circuits最新文献

{"title":"Circuit Technologies For A Single-1.8V Flash Memory","authors":"Tanzawa, Tanaka, Takeuchi, Nakamura","doi":"10.1109/VLSIC.1997.623808","DOIUrl":"https://doi.org/10.1109/VLSIC.1997.623808","url":null,"abstract":"Introduction This paper proposes three circuit technologies, a Vpp switch, row decoder and charge pump circuit, to realize a single-1.W Flash memory. Unlike a D W S R A M , a Flash memory requires a voltage as high as 2OV to rewrite data [l]. For low-voltage operation, there are two serious problems which we should overcome; one is highvoltage (Vpp) switching and the other is its generation. Vpp switches composed of only high-voltage nMOSFET’s have been used in Flash memories [2,3]. Unlike CMOS switches with large parasitic capacitance of N-well for pMOSFET’s, this nMOS-only Vpp switch has small junction and wiring capacitance, resulting in a short Vppcharging time and high-speed programming. However, this switch also has disadvantage that the minimum operating Vcc is mainly limited by a threshold voltage of an enhancement transistor which prevents the leakage current from flowing in the Vpp switch during the inactive state (Fig.1). Another serious problem with a single low-voltage Flash memoly is that efficiency of charge pump circuits is drastically degraded with Vcc lowering. Area for charge pump circuits in a single low-voltage Flash memory will drastically increase for a constant Vpp-charging time (Fig.5). Focusing on Vpp switching and generation, this paper describes (1) a Vpp switch composed of only intrinsic high-voltage transistors without channel implantation, which flows no leakage current from Vpp, reduces the maximum voltage applied to the gate of the switchmg transistor and can operate even at a Vcc of 1.W, (2) a row decoder scheme such that all blocks are in selected state in standby, preventing the standby leak from flowing in the Vpp switches used in row decoders, and (3) a merged pump scheme enabling a charge pump circuit to output two voltage levels with an individually optimized efficiency while reducing the circuit area in comparison with the conventional scheme which requires two charge pump circuits for two voltage levels. Vpp Switch Figs.1 and 2 respectively illustrate the conventional [2,3] and proposed Vpp switches. In the conventional switch, an enhancement transistor M1 is used to prevent the leakage current from Vpp when unselected (Sw=L) and an intrinsic transistor without channel implantation M2 is used to improve the positive-feedback efficiency of the booster when selected (Sw=H). The switching operation is as follows. The source voltage Vcap of the M1 is equal to the gate voltage Vg of the M1 minus the threshold voltage Vt(E) of the M1 with the clock Clk high (Vcap=Vg-Vt(E)). After that, the Clk turns to low and the gate voltage of the M1 increases to Vg’=Vcap+Vcc-Vt(I), where Vt(1) is a threshold voltage of an intrinsic transistor. Thus the voltage gain per cycle is Vg’-Vg, i.e., Vcc-Vt(E)-Vt(1). When Vg reaches Vpp+Vt(E) due to this positive feedback, the M5 outputs Vpp. As descrived above, efficiency of the positive feedback for switching depends on Vcc-Vt(E)-Vt(I), so that the mini” operating Vcc is limited b","PeriodicalId":175678,"journal":{"name":"Symposium 1997 on VLSI Circuits","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130122713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An 8-GSa/s 8-bit ADC System","authors":"Ken Poulton, K. Knudsen, John Kerley, James Kang, Jon Tani, Eldon Cornish, Michael VanGrouw","doi":"10.1109/VLSIC.1997.623783","DOIUrl":"https://doi.org/10.1109/VLSIC.1997.623783","url":null,"abstract":"We report on an analog to digital converter (ADC) system with 8 bit resolution and a sam le rate of 8 GSa/s. The system is composed of 2 thick-fh hybrid substrates, each holding a silicon bipolar ADC chip and a custom CMOS memory chip. Each ADC chip contains two differential track and hold circuits and two folding and interpolating 2 GSa/s flash digitizers. The custom memory chip accepts data at 2 GSa/s on each of two input ports, and stores the data in a 256 Kbit SUM. The ADC system uses time interleaving of 4 paths to reach 8 GSa/s and combines hardware dither with software calibration techniques to achieve 7.6 effective bits at low frequencies and 5.3 effective bits at 2 GHz input. Thick-film Hybrid","PeriodicalId":175678,"journal":{"name":"Symposium 1997 on VLSI Circuits","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122549217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Multi-page Cell Architecture For High-speed Programming Multi-level NAND Flash Memories","authors":"Takeuchi, Tanaka, Tanzawa","doi":"10.1109/VLSIC.1997.623810","DOIUrl":"https://doi.org/10.1109/VLSIC.1997.623810","url":null,"abstract":"To realize low-cost, highly reliable, high-speed pro- gramming, and high-density multilevel flash memories, a mul- tipage cell architecture has been proposed. This architecture enables both precise control of the of a memory cell and fast programming without any area penalty. In the case of a four-level cell, a high programming speed of 236 s/512 bytes or 2.2 Mbytes/s can be obtained, which is 2.3 times faster than the conventional method. A small die size can be achieved with the newly developed compact four-level column latch circuit. A preferential page select method has also been proposed so as to improve the data retention characteristics. The IC error rate can be decreased by as much as 43%, and a highly reliable operation can be realized.","PeriodicalId":175678,"journal":{"name":"Symposium 1997 on VLSI Circuits","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125842124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 4.5 Megabit, 560MHz, 4.5 Gbyte/s High Bandwidth SRAM","authors":"Greason, Buehler, Kolousek, Yong-Gee Ng, Sarkez, Shay, Waizman","doi":"10.1109/VLSIC.1997.623779","DOIUrl":"https://doi.org/10.1109/VLSIC.1997.623779","url":null,"abstract":"High performance microprocessors require large caches with very high bandwidth and low latency to attain maximum performance. However, as technology scales to smaller dimensions and lower operating voltages, continuous improvements in memory performance require more aggressive chip architectures. This work focuses on the design and implementation of a large, fully pipelined, synchronous SRAM intended to demonstrate techniques for the design of high performance caches. This particular design was also used to gather yield and performance data on a developing silicon technology, and so process-independent design was necessary. The part is fabricated on Intel’s 0.25 micron, 1.8V suppIy voltage CMOS technology, described in [I]. Maximum frequency at 1.8V, 25OC is 560MHz (1.79nS cycle). Ignoring the error correction bits, that yields a buss bandwidth of 4.48 GByteIsecond. The die size is 142mm2.","PeriodicalId":175678,"journal":{"name":"Symposium 1997 on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129123311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 0.6/spl mu/m CMOS 4Gb/s Transceiver With Data Recovery Using Oversampling","authors":"C. Yang, R. Farjad-Rad, Horowitz","doi":"10.1109/VLSIC.1997.623812","DOIUrl":"https://doi.org/10.1109/VLSIC.1997.623812","url":null,"abstract":"A 0.6pm CMOS 4Gb/s Transceiver with Data Recovery usi Chih-Kong Ken Yang, Ramin Farjad-Rad, and Mark Horowitz Center for Integrated Systems, Stanford University Stanford, CA 94305 ABSTRACT A 4Gb/s serial link transmitter and receiver fabricated in the MOSIS HP0.6pm CMOS process uses edges tapped from a PLL to multiplex (transmit) and demultiplex (receive) the data. For data recovery the input is sampled at 3x the bit rate and uses a digital phase picking logic that allows very fast tracking of the bit window. With a 3.3V supply, the chip has a measured BER of < Architecture The architecture to achieve the 4Gb/s transmission and reception is shown in Fig. 1. Due to intrinsic process limitations, generating a 4Gb/s bit stream directly in a 0.6pm technology is impossible (maximum ring oscillator frequency is <2GHz.) The bit stream is generated by 8: 1 multiplexing using 8 different clock phases from a 4stage ring oscillator (Tx-PLL), so that the on-chip frequency is 1/8th the data rate. Various techniques exist for generating multiple clock phases [2], [3]; this paper uses the one discussed in [l]. The data recovery requires a 1:8 demultiplexing using similar multi-phased clocks. 24 clocks are generated by interpolating phases from a 6-stage ring oscillator (Rx-PLL) for the 3x oversampling [l]. The oversampled data is processed by a decision algorithm and simultaneously delayed so that the decision can be applied to the appropriate samples to recover the actual data. To facilitate the digital design, the data is first re-synchronized from the multiple clock phases to a global clock (this re-synchronizing process is reversed in the transmitter). Fig. 2 shows the timing for generating the transmitted and received signals. The re-synchronizing clocks and global clock are chosen and buffered carefully to prevent hold-time violation. The sampling and re-timing requires 2 cycles of latency. For bit error rate (BER) testing, a 27-1 PRBS encoder and decoder was built on chip as well as a scannable transmit data pattem. Decision Algorithm The algorithm for resolving the data from the samples depends upon the channel characteristics and the application. The algorithm serves a dual purpose of determining the value and timing of the data. The 3x oversampling was chosen as a trade-off of better sampling resolution and data recovery against increased power, area, and complexity. The BER for each oversampling ratio shown in Fig. 4 are calculated by averaging the BER of all possible phase positions. To determine the data value, we can weigh and sum the three samples such as majority voting which rejects high frequency glitches. However, even if the cablelfiber is not bandwidth limiter, the parasitic capacitance from the bank of input samplers required for the oversampling and demultiplexing as well as the parallel current-mode drivers for the output multiplexing forms a significant low-pass filter near the data frequency (85ps RC.) Majority voting becomes less usef","PeriodicalId":175678,"journal":{"name":"Symposium 1997 on VLSI Circuits","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128098362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 1Gbit SDRAM With An Independent Sub-array Controlled Scheme And A Hierarchical Decoding Scheme","authors":"Yoon, Lee, Moon, Kim, Cho","doi":"10.1109/VLSIC.1997.623828","DOIUrl":"https://doi.org/10.1109/VLSIC.1997.623828","url":null,"abstract":"A s the realm of high performance DRAM has been extended up to the Gigabit scale [1 ,2 ] , the large device size has been the major concern, presenting challenges in attaining acceptable yield and power consumption. A s the ratio of the total chip s ize and the minimum feature s ize is rapidly increased, even the smallest defects will cause failures, often very difficult t o analyze. Moreover, with high speed synchronous bank interleaving operation, the power consumption is large, requring a tight control of the power budget in the peripheral regions. Th i s paper presents design techniques utilizing the i n d e p e n d e n t sub-array controlled scheme and the hierarchical decoding scheme t o achieve enhanced failure analysis, lower power consumption, and smaller chip size in a prototype lGbit synchronous DRAM (SDRAM).","PeriodicalId":175678,"journal":{"name":"Symposium 1997 on VLSI Circuits","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129328526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"CMOS Charge-transfer Preamplifier For Offset-fluctuation In Low-power, High-accuracy Comparators","authors":"Kotani, Shibata, Ohmi","doi":"10.1109/VLSIC.1997.623782","DOIUrl":"https://doi.org/10.1109/VLSIC.1997.623782","url":null,"abstract":"We have developed a low-power and high-accuracy comparator composed of a dynamic latch and a CMOS charge transfer preamplifier (CT preamp). The CT preamp amplifies the input signal with no dc power dissipation and the operation is almost insensitive to the device parameter fluctuations in the preamp. The fluctuation in the offset voltage of a dynamic latch is reduced by a factor of the preamp gain. The circuit operation has been verified by measurements on test circuits fabricated by 0.6 pm CMOS process. Introduction Low power operation of analog-to-digital converters (ADC) is becoming increasingly important in portable applications. For this purpose, we have proposed a low- power two-step ADC circuitry which consists of a capacitive dividing reference voltage generator and dynamic latch comparators (l). It operates in a purely dynamic mode, resulting in very low power consumption. However, a dynamic latch has large fluctuation in the offset voltage (several tens mV) due to the threshold-voltage mismatch of pair transistors in the difference amplifier circuit. Therefore, the new ADC architecture is not applicable to video signal application which requires 8-10 bit resolution (2-8 mV accuracy for comparators). In order to solve the problem of large offset-voltage fluctuation in a dynamic latch circuitry, we have introduced a CMOS charge-transfer preamplifier (CT preamp) in front of a dynamic latch. The CT preamp is insensitive to the device parameter fluctuations and amplifies the input signal with no dc power dissipation, resulting in realization of a high- accuracy and low-power comparator. In this paper, we present a circuit operation of the CMOS CT preamp and the effectiveness of the circuit is demonstrated by the HSPICE simulation results and the measurement results of fabricated test circuits. CMOS Charge Transfer Preamplifier Fig. 1 shows the circuit diagram and the operation of the CMOS CT preamp. Capacitance(CT)-loaded nMOS and PMOS share the common drain electrode and the common gate electrode. The common drain forms the output of the CT preamp which is fed to the dynamic latch circuit. The gate electrode is capacitively coupled to VIN or VREF (comparator inputs). The capacitance CO corresponds to the input capacitance of the dynamic latch. The circuit operates in three cycles. In the first cycle, the two capacitors (CT) are discharged by shorting the electrodes. In the second cycle, the two capacitors (CT) are charged through the source follower action of PMOS and nMOS transistors whose gate electrodes are biased to VPR. The charging automatically stops when the gate-source voltages of the PMOS and the nMOS reach the threshold voltages, VTP and VTN, respectively. As a result, the two capacitors are precharged to VpR-VTp and VPR- VTN. Then, in the third cycle, the common drain is made floating and the comparator input is switched from VIN to VWF. The charge redistribution occurs between CO and CT through the source follower action of eit","PeriodicalId":175678,"journal":{"name":"Symposium 1997 on VLSI Circuits","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125075511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High Speed Low EMI Digital Video Interface With Cable Deskewing and transition Minimization Coding","authors":"Kyeongho Lee, Deog-Kyoon Jeong, Da Costa, Kim","doi":"10.1109/VLSIC.1997.623788","DOIUrl":"https://doi.org/10.1109/VLSIC.1997.623788","url":null,"abstract":"This paper presents a high speed digital video display interface system implemented with 0.5~ CMOS technology, which can overcome the EM1 and power bottlenecks in the high resolution flat panel display systems. The proposed interface system enables high speed (up to 800 Mbps) low voltage swing serial data transmission which drastically cuts the number of parallel lines down to 4 pairs and reduces EM1 effects in the video data transmission. A newly proposed transition controlled coding scheme minimizes the number of transitions on the serial data stream down to 22% per byte. The high speed low voltage swing serial interface using proposed digital PLL and the transition controlled coding scheme supports resolutions beyond XGA (1 024 X 768) without the EM1 and power problem.","PeriodicalId":175678,"journal":{"name":"Symposium 1997 on VLSI Circuits","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114891335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Designing High Performance Microprocessors","authors":"Paul Gronowski","doi":"10.1109/VLSIC.1997.623803","DOIUrl":"https://doi.org/10.1109/VLSIC.1997.623803","url":null,"abstract":"Alpha microprocessors have maintained leadership performance since their introduction in 1992. Three generations of microprocessors were designed by an experienced, highly skilled design team using a proven design methodology. These microprocessors achieve performance by focusing on high frequency design. The Alpha instruction set architecture (ISA) facilitates high clock speed, and the chip organization for each generation is carefully chosen to meet critical paths. In addition, Digital¿s CMOS technologies included specific features to enable high frequency, low-skew clock distribution. Complex circuit styles were used throughout these designs to meet aggressive cycle time goals. Close interaction between all of theses disciplines was essential to the success of these microprocessors. This paper will discusses some of the key technologies that have enabled Alpha microprocessors to maintain leadership performance.","PeriodicalId":175678,"journal":{"name":"Symposium 1997 on VLSI Circuits","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125180453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 900-MHz CMOS Direct Conversion Receiver","authors":"Razavi","doi":"10.1109/VLSIC.1997.623833","DOIUrl":"https://doi.org/10.1109/VLSIC.1997.623833","url":null,"abstract":"This paper describes the design of a single-chip 900-MHz CMOS direct conversion receiver (DCR) fabricated in a digital 0.6-pm technology and operating from a 3-V supply. Shown in Fig. 1 is the DCR architecture, consisting of a low-noise amplifier (LNA), quadrature mixers, simple low-pass filters (LPFs), a local oscillator (LO), a divide-by-two circuit, and baseband amplifiers, A1. An important goal in the design has been to achieve a relatively high gain (approximately 35 dB) in the RF section so as to minimize the effect of the l/f noise contributed by the baseband amplifiers. For this reason, passive mixers have been avoided even though they provide potentially higher linearity than do their active counterparts. Another goal has been to include the LO on the chip so as to obtain a realistic estimate of the leakage to the front end. The design incorporates on-chip inductors extensively to improve the performance. Fig. 2 shows the implementation of the LNA and the quadrature mixers. The LNA is configured as a cascode stage, M1 and Mz, with a 10-nH inductive load [l]. Providing high isolation between the output and the input, the cascode transistor not only improves the stability of the circuit but suppresses the LO leakage to the antenna as well. Utilizing large devices [(W/L)l = 2000 pm/0.6 pm)] and a relatively high bias current (= 5 mA), the LNA achieves a noise figure of less than 2 dB and a voltage gain of approximately 20 dB. The inductive load provides a high gain while consuming negligible voltage headroom. The use of an inductive load in the LNA prohibits the use of feedback to define the bias current and the output dc voltage of the circuit. While M3 and Ib determine the bias current, the output voltage remains close to VDD, a serious problem with respect to the bias point of thefollowing stage-the mixer. This issue is resolved as explained below. The mixer employs a single-balanced topology consisting of an input transistor M4 and a switching pair &f5-M6. In order to improve the linearity of the voltage-to-current conversion performed by the input stage, capacitor C1 degenerates transistor M4 at 900 MHz [2]. The current source defines the bias condition of M4 with little dependence on its gate voltage. The problem of noise differentiation [2] is overcome by allowing Lz and the bottom-plate parasitic capacitance of C2 (C,) to resonate in the vicinity of 900 MHz and shunt the noise current at higher harmonics of this frequency. Capacitor C2 provides ac coupling, relaxing the limited voltage headrooom issues in the switching stage and also suppressing low-frequency beat signals that are generated if two input interferers experience even-order distortion in M I , M2, and M4. Even without the voltage headroom loss that would otherwise accompany M4 in a simple mixer, the switching stage in Fig. 2 entails a number of trade-offs. To achieve a high conversion gain, M5 and M6 must remain in saturation and, more importantly, the voltage drop acro","PeriodicalId":175678,"journal":{"name":"Symposium 1997 on VLSI Circuits","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121584194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}