Pub Date : 2020-03-04DOI: 10.1109/ISDCS49393.2020.9263006
Keshab Das, Nigidita Pradhan, Vipin Kumar, S. K. Jana
This paper presents a comparative study between two Ring oscillators architecture (CMOS, NMOS) and current- starved Voltage-controlled oscillator (CS-VCO) on the basis of their performance parameters (Power consumption, Phase- Noise and Output Swing). All the design has been done in 180- nm CMOS technology node and 2.5 GHz Centre frequency have been opted for the comparison because of their applications in Wi-Fi and Bluetooth regime. An intuitive idea of the stated performance parameters has been achieved through the comparative study. The comparative data shows that NMOS based Ring oscillator is best option in terms of the phase noise performance. In this study NMOS Ring Oscillator have achieved a phase noise -72.94 dBc/Hz at 1 MHz offset frequency from 2.5 GHz centre frequency. The comparative data also mirrors that CMOS Ring oscillator is the best option in terms of power consumption. In this work CMOS Ring oscillator drained a power of 4.61 μW which is quite low.
{"title":"Comparison and Performance Analysis of Ring Oscillators and Current-Starved VCO in 180-nm CMOS Technology","authors":"Keshab Das, Nigidita Pradhan, Vipin Kumar, S. K. Jana","doi":"10.1109/ISDCS49393.2020.9263006","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9263006","url":null,"abstract":"This paper presents a comparative study between two Ring oscillators architecture (CMOS, NMOS) and current- starved Voltage-controlled oscillator (CS-VCO) on the basis of their performance parameters (Power consumption, Phase- Noise and Output Swing). All the design has been done in 180- nm CMOS technology node and 2.5 GHz Centre frequency have been opted for the comparison because of their applications in Wi-Fi and Bluetooth regime. An intuitive idea of the stated performance parameters has been achieved through the comparative study. The comparative data shows that NMOS based Ring oscillator is best option in terms of the phase noise performance. In this study NMOS Ring Oscillator have achieved a phase noise -72.94 dBc/Hz at 1 MHz offset frequency from 2.5 GHz centre frequency. The comparative data also mirrors that CMOS Ring oscillator is the best option in terms of power consumption. In this work CMOS Ring oscillator drained a power of 4.61 μW which is quite low.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128021087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-04DOI: 10.1109/ISDCS49393.2020.9263014
Alen Sebastian, F. Jose, K. Gopakumar, P. Thiyagarajan
Fast multipliers play a significant role in digital signal processing (DSP) and Arithmetic Logic Unit (ALU) systems. Delay and area are cardinal factors that limit the performance of a VLSI design circuit. The paper focuses on new approaches to Dadda Multiplier using Novel compressor designs. Two novel 4-2 compressors and modified higher order compressors are introduced. Three multiplier designs are proposed and compared with existing multiplier designs. Proposed design is found to be more optimal with the existing design in terms of delay and area, and can be used for exact multiplier applications. The designs are simulated using Xilinx ISE tool.
{"title":"Design and Implementation of an Efficient Dadda Multiplier Using Novel Compressors and Fast Adder","authors":"Alen Sebastian, F. Jose, K. Gopakumar, P. Thiyagarajan","doi":"10.1109/ISDCS49393.2020.9263014","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9263014","url":null,"abstract":"Fast multipliers play a significant role in digital signal processing (DSP) and Arithmetic Logic Unit (ALU) systems. Delay and area are cardinal factors that limit the performance of a VLSI design circuit. The paper focuses on new approaches to Dadda Multiplier using Novel compressor designs. Two novel 4-2 compressors and modified higher order compressors are introduced. Three multiplier designs are proposed and compared with existing multiplier designs. Proposed design is found to be more optimal with the existing design in terms of delay and area, and can be used for exact multiplier applications. The designs are simulated using Xilinx ISE tool.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130909120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-04DOI: 10.1109/ISDCS49393.2020.9262974
Nilanjan Chattaraj, R. Ganguli
This paper presents a design of a piezoelectric bending actuator to achieve enhanced performance by redistributing its piezoelectric material. The performance of the present design has been evaluated by using commercial finite element package. The result reveals that the tip deflection, block force, output energy, output energy density and energy efficiency can be improved by around 20%, 110%, 147%, 147% and 147%, respectively, compared to its existing topologically equivalent counterparts of equal amount of mass and capacitance. However, the frequency of the first mode of vibration that often defines the mechanical bandwidth of the actuator, will be reduced by around 41% compared to its existing topologically equivalent counterparts. Nevertheless, there are many applications, where a piezoelectric cantilever actuator is either vibrated at low resonant frequency, or operated under low bandwidth with enhanced performance. Therefore, the proposed design of piezoelectric bending actuator exhibits prospective usefulness for many applications. Since this research is a comparative study of different structural designs of piezoelectric actuators, therefore, a comparative analysis using finite element models will be sufficient to rationalize the benefits of the proposed design.
{"title":"Enhanced Performance of Piezoelectric Bending Actuator by Material Redistribution","authors":"Nilanjan Chattaraj, R. Ganguli","doi":"10.1109/ISDCS49393.2020.9262974","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9262974","url":null,"abstract":"This paper presents a design of a piezoelectric bending actuator to achieve enhanced performance by redistributing its piezoelectric material. The performance of the present design has been evaluated by using commercial finite element package. The result reveals that the tip deflection, block force, output energy, output energy density and energy efficiency can be improved by around 20%, 110%, 147%, 147% and 147%, respectively, compared to its existing topologically equivalent counterparts of equal amount of mass and capacitance. However, the frequency of the first mode of vibration that often defines the mechanical bandwidth of the actuator, will be reduced by around 41% compared to its existing topologically equivalent counterparts. Nevertheless, there are many applications, where a piezoelectric cantilever actuator is either vibrated at low resonant frequency, or operated under low bandwidth with enhanced performance. Therefore, the proposed design of piezoelectric bending actuator exhibits prospective usefulness for many applications. Since this research is a comparative study of different structural designs of piezoelectric actuators, therefore, a comparative analysis using finite element models will be sufficient to rationalize the benefits of the proposed design.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130664432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-04DOI: 10.1109/ISDCS49393.2020.9263024
Sneha Bharti, Suruchi Sharma, A. Verma, Manisha Bharti, B. Kaur
The Junction less tunnel field-effect transistor (JLTFET) is a charming device because of its brilliant electrical properties and less inconstancy in contrast with MOSFET at the nanometer system. Right now, explore a silicon-based pocket doped JLTFET in which an InAs pocket is embedded over the source-channel intersection to upgrade tunneling likelihood. Right now, have thought about DC and linearity parameter analysis for the conventional and pocket doped JLTFET (PD-JLTFET) in terms of electric field, transfer characteristics, transconductance, second-order voltage intercept point, third-order voltage intercept point, third-order input intercept point and 1-dB compression point. Also, we have analyzed the impact of spacer length variation over the source-channel intersection. The proposed PD-JLTFET has indicated higher ION/IOFF proportion (~1013) and improved subthreshold swing (~9.08 mV/decade). The remarkable qualities showed by PD-JLTFET make it a potential device for low power applications.
{"title":"Performance analysis of Pocket Doped Junction-Less TFET","authors":"Sneha Bharti, Suruchi Sharma, A. Verma, Manisha Bharti, B. Kaur","doi":"10.1109/ISDCS49393.2020.9263024","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9263024","url":null,"abstract":"The Junction less tunnel field-effect transistor (JLTFET) is a charming device because of its brilliant electrical properties and less inconstancy in contrast with MOSFET at the nanometer system. Right now, explore a silicon-based pocket doped JLTFET in which an InAs pocket is embedded over the source-channel intersection to upgrade tunneling likelihood. Right now, have thought about DC and linearity parameter analysis for the conventional and pocket doped JLTFET (PD-JLTFET) in terms of electric field, transfer characteristics, transconductance, second-order voltage intercept point, third-order voltage intercept point, third-order input intercept point and 1-dB compression point. Also, we have analyzed the impact of spacer length variation over the source-channel intersection. The proposed PD-JLTFET has indicated higher ION/IOFF proportion (~1013) and improved subthreshold swing (~9.08 mV/decade). The remarkable qualities showed by PD-JLTFET make it a potential device for low power applications.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115278521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-04DOI: 10.1109/ISDCS49393.2020.9263022
Sarangi Patel, Tanya Garg, Geet Patel, Roshani, Bhaskar Chaudhury, T. Maiti
Accurate tracking and training of human movements can lead to efficient humanoid robot manipulation. Machine learning can pave the way for training these movements as it makes use of algorithms and statistical models to predict new movements relying on patterns and inference. We propose a model that explores the use of machine learning algorithms as a first step to improve humanoid robot manipulation. The implementation consists of two parts, firstly a motion tracking experimental setup that has been developed to accurately capture the movements of human body. Secondly, the development of a machine learning model to train the robot, especially wrist movements, for a given stimuli via music. We described the experimental challenges involved during the implementation such as setting up the experiment, extraction of relevant features for machine learning model and selection of fine-tuning parameters. Our initial results are encouraging thus supporting our hypothesis that the training of humanoid robot can be improved by using machine learning.
{"title":"Motion Retargeting and Machine Learning for Humanoid Robotics","authors":"Sarangi Patel, Tanya Garg, Geet Patel, Roshani, Bhaskar Chaudhury, T. Maiti","doi":"10.1109/ISDCS49393.2020.9263022","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9263022","url":null,"abstract":"Accurate tracking and training of human movements can lead to efficient humanoid robot manipulation. Machine learning can pave the way for training these movements as it makes use of algorithms and statistical models to predict new movements relying on patterns and inference. We propose a model that explores the use of machine learning algorithms as a first step to improve humanoid robot manipulation. The implementation consists of two parts, firstly a motion tracking experimental setup that has been developed to accurately capture the movements of human body. Secondly, the development of a machine learning model to train the robot, especially wrist movements, for a given stimuli via music. We described the experimental challenges involved during the implementation such as setting up the experiment, extraction of relevant features for machine learning model and selection of fine-tuning parameters. Our initial results are encouraging thus supporting our hypothesis that the training of humanoid robot can be improved by using machine learning.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123733706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-04DOI: 10.1109/ISDCS49393.2020.9263004
Chirantan Das, S. Chakraborty, A. Karmakar, S. Chattopadhyay
Electrical Impedance Spectroscopy (EIS) technique is found to be an excellent candidate for bio-sensing and food quality monitoring applications due to its rapid, robust, cost-effective and point-of-care approach. The present research work investigates the implementation of EIS technique supported by several optical spectroscopic techniques such as Ultraviolet-Visible (UV-Vis) and Fourier Transform Mid Infrared (FT-MIR) to detect and quantify several toxic adulterants in foods and bio-consumables. In the current work, the technique is applied to adulterated saccharides, honey, turmeric and milk samples. EIS study exhibited a steady variation of the electrical impedance with increasing adulterant percentage in the solution. Variation of such properties due to adulteration provides a systematic sensor plot through which one can determine their percentage of adulteration in unknown adulterated samples. Alternatively, extensive justification of UV-Vis and FT-MIR results have been enclosed in this study and has been corroborated with the EIS results, wherever applicable. Focus has been given on the process of design and fabrication of bio-sensor devices for detection and quantification of a variety of adulterants in milk samples.
{"title":"Comparative study for the impedimetric detection and quantification of adulterants in different bio-consumables","authors":"Chirantan Das, S. Chakraborty, A. Karmakar, S. Chattopadhyay","doi":"10.1109/ISDCS49393.2020.9263004","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9263004","url":null,"abstract":"Electrical Impedance Spectroscopy (EIS) technique is found to be an excellent candidate for bio-sensing and food quality monitoring applications due to its rapid, robust, cost-effective and point-of-care approach. The present research work investigates the implementation of EIS technique supported by several optical spectroscopic techniques such as Ultraviolet-Visible (UV-Vis) and Fourier Transform Mid Infrared (FT-MIR) to detect and quantify several toxic adulterants in foods and bio-consumables. In the current work, the technique is applied to adulterated saccharides, honey, turmeric and milk samples. EIS study exhibited a steady variation of the electrical impedance with increasing adulterant percentage in the solution. Variation of such properties due to adulteration provides a systematic sensor plot through which one can determine their percentage of adulteration in unknown adulterated samples. Alternatively, extensive justification of UV-Vis and FT-MIR results have been enclosed in this study and has been corroborated with the EIS results, wherever applicable. Focus has been given on the process of design and fabrication of bio-sensor devices for detection and quantification of a variety of adulterants in milk samples.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131178709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-04DOI: 10.1109/ISDCS49393.2020.9262982
Nigidita Pradhan, Keshab Das, S. K. Jana, M. C. Govil
This paper presents the modified design of the pass transistor-based PFD with improved output characteristics for phase locked loop. The proposed design modifies the reset approach which improves the speed of the PFD to 3.3GHz. Here, the number of transistors has been reduced which adds the advantage of low power consumption. The power consumption achieved as 253.5µw at 3.3GHz reference frequency. The design is based on cadence 0.18 µm CMOS process with the supply voltage of 1.8 V. The design is used for low power and high-speed application.
{"title":"Design of Pass Transistor based Phase Frequency Detector for Fast Frequency Acquisition Phase Locked Loop","authors":"Nigidita Pradhan, Keshab Das, S. K. Jana, M. C. Govil","doi":"10.1109/ISDCS49393.2020.9262982","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9262982","url":null,"abstract":"This paper presents the modified design of the pass transistor-based PFD with improved output characteristics for phase locked loop. The proposed design modifies the reset approach which improves the speed of the PFD to 3.3GHz. Here, the number of transistors has been reduced which adds the advantage of low power consumption. The power consumption achieved as 253.5µw at 3.3GHz reference frequency. The design is based on cadence 0.18 µm CMOS process with the supply voltage of 1.8 V. The design is used for low power and high-speed application.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124342169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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