Pub Date : 2020-03-04DOI: 10.1109/ISDCS49393.2020.9262983
I. Maity, H. Rahaman, P. Bhattacharyya
This paper predicts the adsorption probability (sensitivity performance) of various alcohol vapors in graphene oxide (GO) and reduced graphene oxide (rGO) based gas sensor devices, where the role of oxygen containing functional groups of GO and rGO like, epoxy, carbonyl, carboxyl, hydroxyl (sp2 hybridized) and hydroxyl (sp3 hybridized) were investigated for physisorption of methanol and ethanol with the help of first principle calculation (density functional theory (DFT)) employing Atomistix Toolkit QuantumATK (version: P_2019.03-SP1). Among the above mentioned oxygenated functional groups, carbonyl, carboxyl and sp2 hybridized hydroxyl groups were placed at the edges of the GO and rGO basal plane, however epoxy and sp3 hybridized hydroxyl groups were placed vertically to that basal plane. For the considered test species (methanol and ethanol), the optimal positions for gas adsorption onto the oxygenated functional groups, favorable adsorption energy value and charge transfer capacity were calculated for the above stated two planes, separately. It was observed that among the other functional groups, edge carbonyl group showed better adsorption probability with respect to minimum adsorption distance, favorable adsorption energy and charge transfer efficiency towards methanol and ethanol. However, the better sensitivity and selectivity performance was found towards methanol compared to that of ethanol in GO and rGO based gas sensor devices.
{"title":"DFT Based Simulation for Predicting Alcohol Adsorption on Oxygenated Functional Group Containing GO and rGO Based Gas Sensor Devices","authors":"I. Maity, H. Rahaman, P. Bhattacharyya","doi":"10.1109/ISDCS49393.2020.9262983","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9262983","url":null,"abstract":"This paper predicts the adsorption probability (sensitivity performance) of various alcohol vapors in graphene oxide (GO) and reduced graphene oxide (rGO) based gas sensor devices, where the role of oxygen containing functional groups of GO and rGO like, epoxy, carbonyl, carboxyl, hydroxyl (sp2 hybridized) and hydroxyl (sp3 hybridized) were investigated for physisorption of methanol and ethanol with the help of first principle calculation (density functional theory (DFT)) employing Atomistix Toolkit QuantumATK (version: P_2019.03-SP1). Among the above mentioned oxygenated functional groups, carbonyl, carboxyl and sp2 hybridized hydroxyl groups were placed at the edges of the GO and rGO basal plane, however epoxy and sp3 hybridized hydroxyl groups were placed vertically to that basal plane. For the considered test species (methanol and ethanol), the optimal positions for gas adsorption onto the oxygenated functional groups, favorable adsorption energy value and charge transfer capacity were calculated for the above stated two planes, separately. It was observed that among the other functional groups, edge carbonyl group showed better adsorption probability with respect to minimum adsorption distance, favorable adsorption energy and charge transfer efficiency towards methanol and ethanol. However, the better sensitivity and selectivity performance was found towards methanol compared to that of ethanol in GO and rGO based gas sensor devices.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127233203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-04DOI: 10.1109/ISDCS49393.2020.9263018
Subhajit Das, S. Bhattacharya, Debaprasad Das, H. Rahaman
On-chip VLSI interconnects is considered very promising area in the field of IC design in recent years. The delay of interconnect system becomes pre-dominant than the on-chip transistor gate delay in ultra large scale integration due to the substantial parasitic effects. Further the increase in Joule heating and significant increase of grain boundary scattering posed a harsh challenge for future technologies. Subsequently the VLSI industry started a searching the alternative of conventional copper interconnect to get rid of these issues. Here the surprise innovation, graphene, came in picture. Graphene is the material with high electron mobility and high mean free path, so the high current density and lowest resistivity. For interconnect application, due to lower resistivity, graphene nano ribbon (GNR), further multi-layer GNR (MLGNR) has been considered to the most suitable for nano-interconnect application. Further intercalation doping improves the conductivity for MLGNR interconnect. This article demonstrates the basic structural properties and depicts the electrical models of single and multi-layer and intercalation doped GNR. A preliminary discussion on production methods for structuring pristine and intercalated GNR interconnect has also been discussed in this article.
{"title":"A Short Review on Graphene Nanoribbon Interconnect","authors":"Subhajit Das, S. Bhattacharya, Debaprasad Das, H. Rahaman","doi":"10.1109/ISDCS49393.2020.9263018","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9263018","url":null,"abstract":"On-chip VLSI interconnects is considered very promising area in the field of IC design in recent years. The delay of interconnect system becomes pre-dominant than the on-chip transistor gate delay in ultra large scale integration due to the substantial parasitic effects. Further the increase in Joule heating and significant increase of grain boundary scattering posed a harsh challenge for future technologies. Subsequently the VLSI industry started a searching the alternative of conventional copper interconnect to get rid of these issues. Here the surprise innovation, graphene, came in picture. Graphene is the material with high electron mobility and high mean free path, so the high current density and lowest resistivity. For interconnect application, due to lower resistivity, graphene nano ribbon (GNR), further multi-layer GNR (MLGNR) has been considered to the most suitable for nano-interconnect application. Further intercalation doping improves the conductivity for MLGNR interconnect. This article demonstrates the basic structural properties and depicts the electrical models of single and multi-layer and intercalation doped GNR. A preliminary discussion on production methods for structuring pristine and intercalated GNR interconnect has also been discussed in this article.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126349834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-04DOI: 10.1109/ISDCS49393.2020.9263023
Alivia Basak, S. Chakraborty, Chirantan Das, A. Mukherjee, R. Saha, A. Karmakar, S. Chattopadhyay
The current study sought to detect and quantify different folic acid concentrations in Phosphate Buffer Saline (PBS) by employing Electrical Impedance Spectroscopy (EIS).This technique provides a simple, rapid, precise and cost-effective platform for folic acid monitoring. An on-wafer platform has been developed to perform the necessary electrical measurements. Variation of electrical parameters such as impedance, capacitance and conductance for six different concentrations ranging from 4 mg/dl to 6 mg/dl are analyzed. The capacitance and conductance are observed to increase whereas impedance has been found to decrease with increasing folic acid content in saline. FT-MIR spectrum shows distinct confirmatory peaks relevant to the folic acid constituents in the IR range 4000 cm-1 to 400 cm-1.
{"title":"Electrically isolated buried electrode biosensor for detecting folic acid concentration","authors":"Alivia Basak, S. Chakraborty, Chirantan Das, A. Mukherjee, R. Saha, A. Karmakar, S. Chattopadhyay","doi":"10.1109/ISDCS49393.2020.9263023","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9263023","url":null,"abstract":"The current study sought to detect and quantify different folic acid concentrations in Phosphate Buffer Saline (PBS) by employing Electrical Impedance Spectroscopy (EIS).This technique provides a simple, rapid, precise and cost-effective platform for folic acid monitoring. An on-wafer platform has been developed to perform the necessary electrical measurements. Variation of electrical parameters such as impedance, capacitance and conductance for six different concentrations ranging from 4 mg/dl to 6 mg/dl are analyzed. The capacitance and conductance are observed to increase whereas impedance has been found to decrease with increasing folic acid content in saline. FT-MIR spectrum shows distinct confirmatory peaks relevant to the folic acid constituents in the IR range 4000 cm-1 to 400 cm-1.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121353662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-04DOI: 10.1109/ISDCS49393.2020.9263017
L. Biswal, Khokan Mondal, A. Bhattacharjee, H. Rahaman
The high potential quantum computer has promised to solve classically intractable problems. In practicability of such high scalable general purpose quantum computer, the foremost challenge is to protect fragile quantum state from inherent noise sources. In this regards, the most promising surface code has been used for continuous encoding and decoding of quantum information so as to achieve fault tolerance. Besides, each code has threshold level within which the said code can detect and correct the error. The fault-tolerant quantum logic is used to contain error rate below threshold which needs transversal quantum operators. On the other hands, due to much difference the Boolean logic is no more useful in quantum computing. However, the quantum computer has to perform both classical solvable as well as classically intractable problem. In this conjecture, we focus on fault tolerant quantum implementation of Priority Encoder Circuit using Clifford+T gate library which is an essential component information processor.
{"title":"Fault-tolerant Quantum Implementation of Priority Encoder Circuit using Clifford+T-group","authors":"L. Biswal, Khokan Mondal, A. Bhattacharjee, H. Rahaman","doi":"10.1109/ISDCS49393.2020.9263017","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9263017","url":null,"abstract":"The high potential quantum computer has promised to solve classically intractable problems. In practicability of such high scalable general purpose quantum computer, the foremost challenge is to protect fragile quantum state from inherent noise sources. In this regards, the most promising surface code has been used for continuous encoding and decoding of quantum information so as to achieve fault tolerance. Besides, each code has threshold level within which the said code can detect and correct the error. The fault-tolerant quantum logic is used to contain error rate below threshold which needs transversal quantum operators. On the other hands, due to much difference the Boolean logic is no more useful in quantum computing. However, the quantum computer has to perform both classical solvable as well as classically intractable problem. In this conjecture, we focus on fault tolerant quantum implementation of Priority Encoder Circuit using Clifford+T gate library which is an essential component information processor.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121853932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-04DOI: 10.1109/ISDCS49393.2020.9263007
Oliver Keszöcze, R. Wille, R. Drechsler
With the advances of the microfluidic technology, the design of Digital Microfluidic Biochips (DMFBs) received significant attention in the recent past. The corresponding design process usually consists of multiple, consecutive design tasks, namely binding, scheduling, placement, and routing. These tasks, however, are often considered and solved separately. This can lead to design gaps between the individual steps, yielding less-than-optimal overall solutions or prevent to solve the next step altogether. In order to address these shortcomings, the concept of one-pass synthesis for DMFBs has been introduced. In this survey paper, we review the main ideas of this concept and provide an overview on two different implementations of it: (1) an exact, SAT-based approach which guarantees optimal solutions with respect to area and/or timing and (2) a heuristic graph-based approach which focuses on run-time efficiency. We discuss the (dis-)advantages of those approaches with respect to their quality as well as scalability and illustrate them on various benchmark assays.
{"title":"One-pass Synthesis for Digital Microfluidic Biochips: A Survey","authors":"Oliver Keszöcze, R. Wille, R. Drechsler","doi":"10.1109/ISDCS49393.2020.9263007","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9263007","url":null,"abstract":"With the advances of the microfluidic technology, the design of Digital Microfluidic Biochips (DMFBs) received significant attention in the recent past. The corresponding design process usually consists of multiple, consecutive design tasks, namely binding, scheduling, placement, and routing. These tasks, however, are often considered and solved separately. This can lead to design gaps between the individual steps, yielding less-than-optimal overall solutions or prevent to solve the next step altogether. In order to address these shortcomings, the concept of one-pass synthesis for DMFBs has been introduced. In this survey paper, we review the main ideas of this concept and provide an overview on two different implementations of it: (1) an exact, SAT-based approach which guarantees optimal solutions with respect to area and/or timing and (2) a heuristic graph-based approach which focuses on run-time efficiency. We discuss the (dis-)advantages of those approaches with respect to their quality as well as scalability and illustrate them on various benchmark assays.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132123707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-04DOI: 10.1109/ISDCS49393.2020.9262988
T. Iizuka
Two-dimensional current flow in the lightly-doped resistive region in a lateral double-diffused MOS (LDMOS) transistor was analyzed through 2D device simulation. While retaining its theoretical backbone of HiSIM_HV, the industry-standard surface-potential-based compact model for high-voltage MOSFETs, a conceptual extension is explored. Owing to a smooth transit of current flowlines from the channel to the lightly doped region adjacent to the channel of the intrinsic MOSFET part of LDMOS, the surface accumulation occurring at the gate-overlapped surface of the lightly doped resistive region is regarded as an extended channel rather than an extended drain. The channel offset length (ΔL) can be expressed within the framework of the drift-diffusion model and can be related with a characteristic quasi-Fermi voltage Vdive where accumulation current flowlines have already completely dived away from the surface. The HiSIM_HV’s internal drain node (DP or alternatively d’) is regarded as being placed at an opening bounded by the gate-controlled transverse and the drain-controlled lateral extension of depletion region, while many compact models place DP at the boundary between the channel and the lightly doped region. The intrinsic MOSFET’s effective drain voltage (Vdseff) is related to gate controlled Vdive rather than the quasi-Fermi voltage (Vdp) at DP. Hence, a difficulty in that the intrinsic MOSFET’s drain voltage stays almost as high as externally applied drain voltage at the off-state, while it suddenly drops at the onset of on-state of the intrinsic MOSFET part is expected to be mitigated.
{"title":"Carrier Dynamics in Lightly-doped Resistance Region in Power MOSFETs","authors":"T. Iizuka","doi":"10.1109/ISDCS49393.2020.9262988","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9262988","url":null,"abstract":"Two-dimensional current flow in the lightly-doped resistive region in a lateral double-diffused MOS (LDMOS) transistor was analyzed through 2D device simulation. While retaining its theoretical backbone of HiSIM_HV, the industry-standard surface-potential-based compact model for high-voltage MOSFETs, a conceptual extension is explored. Owing to a smooth transit of current flowlines from the channel to the lightly doped region adjacent to the channel of the intrinsic MOSFET part of LDMOS, the surface accumulation occurring at the gate-overlapped surface of the lightly doped resistive region is regarded as an extended channel rather than an extended drain. The channel offset length (ΔL) can be expressed within the framework of the drift-diffusion model and can be related with a characteristic quasi-Fermi voltage Vdive where accumulation current flowlines have already completely dived away from the surface. The HiSIM_HV’s internal drain node (DP or alternatively d’) is regarded as being placed at an opening bounded by the gate-controlled transverse and the drain-controlled lateral extension of depletion region, while many compact models place DP at the boundary between the channel and the lightly doped region. The intrinsic MOSFET’s effective drain voltage (Vdseff) is related to gate controlled Vdive rather than the quasi-Fermi voltage (Vdp) at DP. Hence, a difficulty in that the intrinsic MOSFET’s drain voltage stays almost as high as externally applied drain voltage at the off-state, while it suddenly drops at the onset of on-state of the intrinsic MOSFET part is expected to be mitigated.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133016402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The immense computation and huge memory requirement are challenging the computation efficiency of today’s systems. Consequently, neuromorphic systems have become a topical subject in research to mimic the brain’s power efficiency and computational speed. There have always been certain major bottlenecks in the conventional architectures. In this paper, we develop a Network-on-Chip based Spiking Neural Network (NoCSNN), having a highly parallel architecture for the neuromorphic computing systems. It also benefits from the use of NoC in terms of scalability, latency and speed. The neurons in our proposed SNN model communicates through NoC architecture. Our proposed model consisting of 64 neurons is synthesized in 28nm technology node achieving a power dissipation of 29.22 mW and a die area of 1.61 mm2. The NoC model is also explored in terms of latency, throughput and energy.
{"title":"NoCSNN: A Scalable Interconnect Architecture for Neuromorphic Computing Systems","authors":"Ayut Ghosh, Aneek Jash, Ramapati Patra, Hemanta Kumar Mondal","doi":"10.1109/ISDCS49393.2020.9263025","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9263025","url":null,"abstract":"The immense computation and huge memory requirement are challenging the computation efficiency of today’s systems. Consequently, neuromorphic systems have become a topical subject in research to mimic the brain’s power efficiency and computational speed. There have always been certain major bottlenecks in the conventional architectures. In this paper, we develop a Network-on-Chip based Spiking Neural Network (NoCSNN), having a highly parallel architecture for the neuromorphic computing systems. It also benefits from the use of NoC in terms of scalability, latency and speed. The neurons in our proposed SNN model communicates through NoC architecture. Our proposed model consisting of 64 neurons is synthesized in 28nm technology node achieving a power dissipation of 29.22 mW and a die area of 1.61 mm2. The NoC model is also explored in terms of latency, throughput and energy.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"67 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114113665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-04DOI: 10.1109/ISDCS49393.2020.9262973
Debanjan Dhara, B. K. Roy
Distance relay detect fault and distance of fault in the transmission line. But during power swing malfunction occurs and it trips circuit breaker (CB) for which power swing increase again and causes another circuit breaker trip. This recurring process may cause power blackout if it is not stopped immediately. Power swing blocking (PSB) relay is used to block distance relay during power swing. But if any fault occurs during power swing, it needs to unblock the distance relay and trip the CB for clearing the fault. Our proposed method overcomes the shortcoming of the conventional method of unblocking distance relay during power swing when a fault occurs. On this paper a new method has been proposed to detect a fault during power swing using total harmonic distortion of voltage. To demonstrate the effectiveness of the proposed method here we conduct a simulation of a single machine infinite bus system in PSCAD/EMTDC. Various simulation studies has been studies have been performed on a SMIB system developed PSCAD/EMTDC.
{"title":"A Harmonic-Based Method of Fault Detection During Power Swing","authors":"Debanjan Dhara, B. K. Roy","doi":"10.1109/ISDCS49393.2020.9262973","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9262973","url":null,"abstract":"Distance relay detect fault and distance of fault in the transmission line. But during power swing malfunction occurs and it trips circuit breaker (CB) for which power swing increase again and causes another circuit breaker trip. This recurring process may cause power blackout if it is not stopped immediately. Power swing blocking (PSB) relay is used to block distance relay during power swing. But if any fault occurs during power swing, it needs to unblock the distance relay and trip the CB for clearing the fault. Our proposed method overcomes the shortcoming of the conventional method of unblocking distance relay during power swing when a fault occurs. On this paper a new method has been proposed to detect a fault during power swing using total harmonic distortion of voltage. To demonstrate the effectiveness of the proposed method here we conduct a simulation of a single machine infinite bus system in PSCAD/EMTDC. Various simulation studies has been studies have been performed on a SMIB system developed PSCAD/EMTDC.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117079024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-04DOI: 10.1109/ISDCS49393.2020.9263015
Subhajit Chatterjee, S. Roy, C. Giri, H. Rahaman
Three-dimensional integrated circuit (3D IC) is an emerging field with huge prospects. It provides significant benefits over conventional 2D IC. However, testing of 3D ICs is quite challenging compared to conventional 2D ICs due to constrained access to the cores and high power density. This work presents a test scheduling algorithm for 3D ICs to minimize test time. The peak power of the generated schedule is also considered and optimized to balance with test time using a weighted cost function. TSV limit is also considered to check test resource cost. The proposed algorithm applied on different ITC’02 benchmark circuits shows promising results.
{"title":"An Efficient Test Scheduling to Co-optimize Test Time and Peak Power for 3D ICs","authors":"Subhajit Chatterjee, S. Roy, C. Giri, H. Rahaman","doi":"10.1109/ISDCS49393.2020.9263015","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9263015","url":null,"abstract":"Three-dimensional integrated circuit (3D IC) is an emerging field with huge prospects. It provides significant benefits over conventional 2D IC. However, testing of 3D ICs is quite challenging compared to conventional 2D ICs due to constrained access to the cores and high power density. This work presents a test scheduling algorithm for 3D ICs to minimize test time. The peak power of the generated schedule is also considered and optimized to balance with test time using a weighted cost function. TSV limit is also considered to check test resource cost. The proposed algorithm applied on different ITC’02 benchmark circuits shows promising results.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117278786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-04DOI: 10.1109/isdcs49393.2020.9262989
{"title":"ISDCS 2020 Cover Page","authors":"","doi":"10.1109/isdcs49393.2020.9262989","DOIUrl":"https://doi.org/10.1109/isdcs49393.2020.9262989","url":null,"abstract":"","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124172801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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