Pub Date : 2020-03-04DOI: 10.1109/ISDCS49393.2020.9262985
Sagarika Choudhury, K. L. Baishnab, K. Guha
The proposed work incorporates advantage of hetero-stacked source and Selective Buried Oxide (SELBOX) structure in a single device. A comparative performance assessment of the presented structure with the existing structures has been done after analyzing critical parameters. The parameters such as drain current, sub-threshold swing, and capacitances are studied for the proposed structure. It has been observed that the structure improves the ION/IOFF ratio and Subthreshold Swing (SS). A current ratio of 1010 and Point subthreshold swing of 27 mV/dec and Average SS of 36 mV/dec is obtained. An On-current of 2.2 x 10-6A is also observed.
所提出的工作在单个器件中结合了异质堆叠源和选择性埋藏氧化物(SELBOX)结构的优点。通过对关键参数的分析，对所提出的结构与现有结构进行了性能对比评估。研究了漏极电流、亚阈值摆幅和电容等参数。观察到，该结构改善了离子/ off比和亚阈值摆幅(SS)。电流比为1010，点亚阈值摆幅为27 mV/dec，平均SS为36 mV/dec。也观察到2.2 x 10-6A的导通电流。
{"title":"An approach to improve performance of an SELBOX TFET using hetero-stacked source","authors":"Sagarika Choudhury, K. L. Baishnab, K. Guha","doi":"10.1109/ISDCS49393.2020.9262985","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9262985","url":null,"abstract":"The proposed work incorporates advantage of hetero-stacked source and Selective Buried Oxide (SELBOX) structure in a single device. A comparative performance assessment of the presented structure with the existing structures has been done after analyzing critical parameters. The parameters such as drain current, sub-threshold swing, and capacitances are studied for the proposed structure. It has been observed that the structure improves the ION/IOFF ratio and Subthreshold Swing (SS). A current ratio of 1010 and Point subthreshold swing of 27 mV/dec and Average SS of 36 mV/dec is obtained. An On-current of 2.2 x 10-6A is also observed.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127041971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-04DOI: 10.1109/ISDCS49393.2020.9262994
B. Chakraborty, D. De, C. Roychaudhuri
This paper demonstrates the effect of defect states on the biosensing performance of zinc oxide (ZnO) based thin-film transistor (TFT). The drain current variations of ZnO TFT after defect state incorporation have been studied using a simulation platform. The thickness variation of the sensing materials has also been studied in this work.
{"title":"Liquid Gated Biosensor Based on ZnO TFT","authors":"B. Chakraborty, D. De, C. Roychaudhuri","doi":"10.1109/ISDCS49393.2020.9262994","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9262994","url":null,"abstract":"This paper demonstrates the effect of defect states on the biosensing performance of zinc oxide (ZnO) based thin-film transistor (TFT). The drain current variations of ZnO TFT after defect state incorporation have been studied using a simulation platform. The thickness variation of the sensing materials has also been studied in this work.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115710100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-04DOI: 10.1109/ISDCS49393.2020.9263002
U. Sahu, A. Saha, P. Gupta, H. Rahaman
After silicon, semiconducting 2D transition metal dichalcogenide monolayers (TMDs) crystals are coming up as favorable candidate in ultra-thin channels material in the future generation of transistors. However, fabrication of these crystals as channel materials with acceptable performance is still challenging. Presence of direct bandgaps (1–2eV) in monolayer semiconducting TMDs, along with mobility improvement by dielectric engineering, It opens up a boundless scope in future electronic applications. In present work, we give a computational study on contribution of the second-lowest valley (Q valley about midway between K and Γ) of conduction band on device performance in monolayer TMD based MOSFETs (TMDFETs). From our calculation, we have found that the contribution of Q valley is not negligible, as the energy difference between conduction band minima (CBM) and second lowest valley (ΔEc) is very small and it is around 2kT. Q valley has valley degeneracy of 6, compared with valley degeneracy 2 for K Valley in the conduction band. So, we can say that the occupancy of ‘K’ valley and ‘Q’ valley is very close to each other. Hence two valleys are equally important for carrier transport. In our studies, we have found, the contribution of the second-lowest valley of all semiconducting monolayer TMDs in the current calculation is very significant.
{"title":"Valley Resolved Current Components Analysis of Monolayer TMDFETs","authors":"U. Sahu, A. Saha, P. Gupta, H. Rahaman","doi":"10.1109/ISDCS49393.2020.9263002","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9263002","url":null,"abstract":"After silicon, semiconducting 2D transition metal dichalcogenide monolayers (TMDs) crystals are coming up as favorable candidate in ultra-thin channels material in the future generation of transistors. However, fabrication of these crystals as channel materials with acceptable performance is still challenging. Presence of direct bandgaps (1–2eV) in monolayer semiconducting TMDs, along with mobility improvement by dielectric engineering, It opens up a boundless scope in future electronic applications. In present work, we give a computational study on contribution of the second-lowest valley (Q valley about midway between K and Γ) of conduction band on device performance in monolayer TMD based MOSFETs (TMDFETs). From our calculation, we have found that the contribution of Q valley is not negligible, as the energy difference between conduction band minima (CBM) and second lowest valley (ΔEc) is very small and it is around 2kT. Q valley has valley degeneracy of 6, compared with valley degeneracy 2 for K Valley in the conduction band. So, we can say that the occupancy of ‘K’ valley and ‘Q’ valley is very close to each other. Hence two valleys are equally important for carrier transport. In our studies, we have found, the contribution of the second-lowest valley of all semiconducting monolayer TMDs in the current calculation is very significant.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"1992 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125534318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-04DOI: 10.1109/ISDCS49393.2020.9262972
S. Jaiswal, Annapurna Mondal, S. Srimani, Subhajit Das, K. Ghosh, H. Rahaman
A Dynamic Comparator is an important part of the analog-to-digital converter (ADC). The performance and accuracy of ADC depends on the design of comparator. Moreover, comparator is the most power-hungry among all other parts of ADC. To satisfy speed and accuracy within a low power budget requirements, a PMOS based Double tail latch type Comparator circuit has been presented in this work. Detail analysis of offset voltage of the dynamic latched comparator has been carried out in this work. A Foreground calibration technique is used in this work to minimize the offset. The entire architecture is designed and simulated in CADENCE Virtuoso using UMC 180nm PDK with 1.8V power supply. Transient and statistical measurements have been carried out to test the performance of the circuit under the impact of process variations, temperature and mismatches. Post-layout simulation shows that the comparator achieves 200µV resolution with 13 bit precision at a frequency of 50 MHz while dissipating 6.68µW from 1.8V supply with 0.074mm2 area consumption.
{"title":"Design of a low power, high speed self calibrated dynamic latched comparator","authors":"S. Jaiswal, Annapurna Mondal, S. Srimani, Subhajit Das, K. Ghosh, H. Rahaman","doi":"10.1109/ISDCS49393.2020.9262972","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9262972","url":null,"abstract":"A Dynamic Comparator is an important part of the analog-to-digital converter (ADC). The performance and accuracy of ADC depends on the design of comparator. Moreover, comparator is the most power-hungry among all other parts of ADC. To satisfy speed and accuracy within a low power budget requirements, a PMOS based Double tail latch type Comparator circuit has been presented in this work. Detail analysis of offset voltage of the dynamic latched comparator has been carried out in this work. A Foreground calibration technique is used in this work to minimize the offset. The entire architecture is designed and simulated in CADENCE Virtuoso using UMC 180nm PDK with 1.8V power supply. Transient and statistical measurements have been carried out to test the performance of the circuit under the impact of process variations, temperature and mismatches. Post-layout simulation shows that the comparator achieves 200µV resolution with 13 bit precision at a frequency of 50 MHz while dissipating 6.68µW from 1.8V supply with 0.074mm2 area consumption.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121062702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-04DOI: 10.1109/ISDCS49393.2020.9263027
Salwa Yasmeen Neyaz, Itisha Saxena, N. Alam, Syed Atiqur Rahman
The multipliers find extensive use in today’s digital world and are even fundamental components in many signal processing applications. This paper presents the implementation and comparison of three types of 4-bit and 8-bit multipliers i.e. Array, Wallace and Baugh Wooley. The implementation is done on both the FPGA and ASIC to compare the designs. The FPGA implementation is done on NEXYS 4 DDR which is equipped with Xilinx Artix-7 FPGA. The ASIC implementation is done using Cadence and Standard Cell Library 90 nm gpdk (generic process design kit). The results indicate that the Baugh Wooley incurs the minimum delay in the FPGA implementation while as the Wallace tree incurs minimum Power Delay Product in the ASIC implementation. The Baugh Wooley is the least area consuming architecture for both the FPGA and the ASIC implementation.
{"title":"FPGA and ASIC Implementation and Comparison of Multipliers","authors":"Salwa Yasmeen Neyaz, Itisha Saxena, N. Alam, Syed Atiqur Rahman","doi":"10.1109/ISDCS49393.2020.9263027","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9263027","url":null,"abstract":"The multipliers find extensive use in today’s digital world and are even fundamental components in many signal processing applications. This paper presents the implementation and comparison of three types of 4-bit and 8-bit multipliers i.e. Array, Wallace and Baugh Wooley. The implementation is done on both the FPGA and ASIC to compare the designs. The FPGA implementation is done on NEXYS 4 DDR which is equipped with Xilinx Artix-7 FPGA. The ASIC implementation is done using Cadence and Standard Cell Library 90 nm gpdk (generic process design kit). The results indicate that the Baugh Wooley incurs the minimum delay in the FPGA implementation while as the Wallace tree incurs minimum Power Delay Product in the ASIC implementation. The Baugh Wooley is the least area consuming architecture for both the FPGA and the ASIC implementation.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127035409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-04DOI: 10.1109/ISDCS49393.2020.9262984
Biswapriyo Das, S. Mahapatra
We propose a generalized compact model for any two-dimensional material channel-based metal-oxide-semiconductor field-effect transistors. Unlike existing ones, the proposed model is first principles based and thus has ability to predict the circuit performance only using the crystallographic information of the channel material. It is ‘core’ in nature and developed following the industry-standard drift-diffusion formalism based ‘top-down’ hierarchy employing the Fermi-Dirac statistics. We also implement the model in professional circuit simulator and good convergence is observed in 15-stage ring oscillator simulation.
{"title":"First Principles Based Compact Model for 2D-Channel MOSFETs","authors":"Biswapriyo Das, S. Mahapatra","doi":"10.1109/ISDCS49393.2020.9262984","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9262984","url":null,"abstract":"We propose a generalized compact model for any two-dimensional material channel-based metal-oxide-semiconductor field-effect transistors. Unlike existing ones, the proposed model is first principles based and thus has ability to predict the circuit performance only using the crystallographic information of the channel material. It is ‘core’ in nature and developed following the industry-standard drift-diffusion formalism based ‘top-down’ hierarchy employing the Fermi-Dirac statistics. We also implement the model in professional circuit simulator and good convergence is observed in 15-stage ring oscillator simulation.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130470787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-04DOI: 10.1109/ISDCS49393.2020.9262975
Hillol Maity, Kaushik Khatua, S. Chattopadhyay, I. Sengupta, Girish Patankar, Parthajit Bhattacharya
During test mode, switching activity in scan-chain integrated circuits increase. As a result, the peak and average power dissipation in test mode often become higher than the normal mode. This can result in yield loss, heat damage to the circuit under test (CUT), and structural damage as well. In this paper, a new technique has been proposed that can efficiently reorder the test vectors targeting low switching activity in the scan chain. The technique has been verified with ISCAS’89 benchmark circuits. The achieved reduction in switching activity goes up to 12% when compared to the pattern order generated by an automatic test pattern generator (ATPG) tools like ATALANTA.
{"title":"A New Test Vector Reordering Technique for Low Power Combinational Circuit Testing","authors":"Hillol Maity, Kaushik Khatua, S. Chattopadhyay, I. Sengupta, Girish Patankar, Parthajit Bhattacharya","doi":"10.1109/ISDCS49393.2020.9262975","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9262975","url":null,"abstract":"During test mode, switching activity in scan-chain integrated circuits increase. As a result, the peak and average power dissipation in test mode often become higher than the normal mode. This can result in yield loss, heat damage to the circuit under test (CUT), and structural damage as well. In this paper, a new technique has been proposed that can efficiently reorder the test vectors targeting low switching activity in the scan chain. The technique has been verified with ISCAS’89 benchmark circuits. The achieved reduction in switching activity goes up to 12% when compared to the pattern order generated by an automatic test pattern generator (ATPG) tools like ATALANTA.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130573580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-04DOI: 10.1109/ISDCS49393.2020.9262996
S. P. Kaarmukilan, Anakhi Hazarika, K. AmalThomas, Soumyajit Poddar, H. Rahaman
Object detection and recognition in realtime is the key task in many computer vision applications such as security surveillance, medical diagnosis, automated vehicle systems, etc. Now-a-days many deep learning techniques, especially convolutional neural networks (CNN) is widely used for real-time image detection and classification. The development of CNN models boosts the accuracy of object detection. However, the complex and data-intensive processing slows down the performance while implemented on hardware. This paper presents a low-powered, portable prototype on Xilinx PYNQ Z2 board with Movidius neural compute stick (NCS) that accelerates the object detection in real-time. Also, the proposed prototype utilized You Only Look Once (YOLO) approach for object detection. Frames per second (FPS), computation time and the probability of object recognition are the parameters considered to evaluate the performance of the proposed prototype and outperform the existing models.
实时目标检测和识别是许多计算机视觉应用的关键任务，如安全监控、医疗诊断、自动车辆系统等。目前，许多深度学习技术，特别是卷积神经网络(CNN)被广泛用于实时图像检测和分类。CNN模型的发展提高了目标检测的精度。然而，在硬件上实现时，复杂的数据密集型处理会降低性能。本文提出了一种基于Xilinx PYNQ Z2板的低功耗便携式原型机，该原型机采用Movidius神经计算棒(NCS)来加速实时目标检测。此外，所提出的原型利用You Only Look Once (YOLO)方法进行目标检测。每秒帧数(FPS)、计算时间和目标识别概率是评估原型性能并优于现有模型的参数。
{"title":"An Accelerated Prototype with Movidius Neural Compute Stick for Real-Time Object Detection","authors":"S. P. Kaarmukilan, Anakhi Hazarika, K. AmalThomas, Soumyajit Poddar, H. Rahaman","doi":"10.1109/ISDCS49393.2020.9262996","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9262996","url":null,"abstract":"Object detection and recognition in realtime is the key task in many computer vision applications such as security surveillance, medical diagnosis, automated vehicle systems, etc. Now-a-days many deep learning techniques, especially convolutional neural networks (CNN) is widely used for real-time image detection and classification. The development of CNN models boosts the accuracy of object detection. However, the complex and data-intensive processing slows down the performance while implemented on hardware. This paper presents a low-powered, portable prototype on Xilinx PYNQ Z2 board with Movidius neural compute stick (NCS) that accelerates the object detection in real-time. Also, the proposed prototype utilized You Only Look Once (YOLO) approach for object detection. Frames per second (FPS), computation time and the probability of object recognition are the parameters considered to evaluate the performance of the proposed prototype and outperform the existing models.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134569414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-04DOI: 10.1109/ISDCS49393.2020.9262978
Subhashree Basu, Malay Kule
The continuous increase in the cost of chip fabrication compelled many organizations to out source the chip fabrication process to third-party companies. But this can be a serious threat to the reliability and the infalliability of the chip because malicious modifications can be made at any stage of the fabrication process. Changing the functionality of ICs or adding new hidden features to them is known as hardware Trojan. Hardware Trojan is very elusive to identification and as a result, the identification process becomes very tiresome and sometimes futile. Detecting multiple Trojans implanted into ICs becomes a colossal task and may impart the device useless. In this paper, we have incorporated different types of Trojans in memristor based NOR type Trenary CAM circuit and then the circuits are analyzed as to show how the circuits behave in presence of the Trojans. Then applying side-channel analysis different parameters are calculated and analyzed to identify the presence of the Trojan.
{"title":"Detection Of Hardware Trojan In Memristive Ternary CAM Circuits","authors":"Subhashree Basu, Malay Kule","doi":"10.1109/ISDCS49393.2020.9262978","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9262978","url":null,"abstract":"The continuous increase in the cost of chip fabrication compelled many organizations to out source the chip fabrication process to third-party companies. But this can be a serious threat to the reliability and the infalliability of the chip because malicious modifications can be made at any stage of the fabrication process. Changing the functionality of ICs or adding new hidden features to them is known as hardware Trojan. Hardware Trojan is very elusive to identification and as a result, the identification process becomes very tiresome and sometimes futile. Detecting multiple Trojans implanted into ICs becomes a colossal task and may impart the device useless. In this paper, we have incorporated different types of Trojans in memristor based NOR type Trenary CAM circuit and then the circuits are analyzed as to show how the circuits behave in presence of the Trojans. Then applying side-channel analysis different parameters are calculated and analyzed to identify the presence of the Trojan.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131046182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-04DOI: 10.1109/ISDCS49393.2020.9262999
S. Mandal, Subhrajit Sikdar, R. Saha, A. Karmakar, S. Chattopadhyay
In this paper, a high-quality crystalline Ge thin film (~10 nm) is grown on n-Si substrate by employing vapour-liquid-solid (VLS) method. The crystalline quality and the film thickness are measured by XRD and spectroscopic ellipsometry experiments, respectively. The current-voltage characteristics of the Ge/n-Si hetero-junction device are measured and the impact of growth time on the rectification properties is studied.
{"title":"Investigating the impact of growth time on the electrical performance of vapour-liquid-solid (VLS) grown Ge/n-Si hetero-junction","authors":"S. Mandal, Subhrajit Sikdar, R. Saha, A. Karmakar, S. Chattopadhyay","doi":"10.1109/ISDCS49393.2020.9262999","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9262999","url":null,"abstract":"In this paper, a high-quality crystalline Ge thin film (~10 nm) is grown on n-Si substrate by employing vapour-liquid-solid (VLS) method. The crystalline quality and the film thickness are measured by XRD and spectroscopic ellipsometry experiments, respectively. The current-voltage characteristics of the Ge/n-Si hetero-junction device are measured and the impact of growth time on the rectification properties is studied.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133209071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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