Pub Date : 1998-05-24DOI: 10.1109/CCECE.1998.685609
J. Mouine, A. B. Hamida, Z. Chtourou, N. Lakhoua, M. Samet
This paper describes the implementation of an FFT based stimulation algorithm. This one is used to stimulate properly the auditive nerve of a totally or profoundly deaf person. Unlike other similar algorithms, this one is endowed with a great flexibility to choose basic speech characteristics to be considered or to adapt special stimulation parameters to a specific patient. This was made possible owing to the flexibility of the cochlear prosthesis used.
{"title":"Implementation of an FFT based stimulation algorithm on a fully programmable cochlear prosthesis","authors":"J. Mouine, A. B. Hamida, Z. Chtourou, N. Lakhoua, M. Samet","doi":"10.1109/CCECE.1998.685609","DOIUrl":"https://doi.org/10.1109/CCECE.1998.685609","url":null,"abstract":"This paper describes the implementation of an FFT based stimulation algorithm. This one is used to stimulate properly the auditive nerve of a totally or profoundly deaf person. Unlike other similar algorithms, this one is endowed with a great flexibility to choose basic speech characteristics to be considered or to adapt special stimulation parameters to a specific patient. This was made possible owing to the flexibility of the cochlear prosthesis used.","PeriodicalId":177613,"journal":{"name":"Conference Proceedings. IEEE Canadian Conference on Electrical and Computer Engineering (Cat. No.98TH8341)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128823095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-05-24DOI: 10.1109/CCECE.1998.682733
M. Margala, N. G. Durdle, N.L. Rodnunsky
This paper presents a new logic design, bipolar double pass-transistor logic (BiDPL), and its implementation into a full-adder. At 1.2 V and output loads of 0.1 to 0.7 pF the new logic style has up to 2.9 times better power efficiency than previously reported low-voltage BiCMOS styles and uses between 16 to 32 % less switching power. Under optimal conditions (V/sub dd/=1.6 V), the new design has up to 18% higher power efficiency than conventional CMOS logic for loads of 0.55 to 1 pF and up to 117 % better power efficiency compared to BiCMOS styles for output loads of 0.1 to 0.68 pF. When used to implement a full adder, it is more power-efficient at very low power supply voltages (1.1 to 2 V) than a conventional CMOS adder design and the best low-voltage low-power adder reported in the literature. The proposed BiDPL adder outperforms in power efficiency both designs at 1.5 V by as much as 61 % and 535 % respectively.
{"title":"Low-voltage power-efficient BiDPL logic design and applications","authors":"M. Margala, N. G. Durdle, N.L. Rodnunsky","doi":"10.1109/CCECE.1998.682733","DOIUrl":"https://doi.org/10.1109/CCECE.1998.682733","url":null,"abstract":"This paper presents a new logic design, bipolar double pass-transistor logic (BiDPL), and its implementation into a full-adder. At 1.2 V and output loads of 0.1 to 0.7 pF the new logic style has up to 2.9 times better power efficiency than previously reported low-voltage BiCMOS styles and uses between 16 to 32 % less switching power. Under optimal conditions (V/sub dd/=1.6 V), the new design has up to 18% higher power efficiency than conventional CMOS logic for loads of 0.55 to 1 pF and up to 117 % better power efficiency compared to BiCMOS styles for output loads of 0.1 to 0.68 pF. When used to implement a full adder, it is more power-efficient at very low power supply voltages (1.1 to 2 V) than a conventional CMOS adder design and the best low-voltage low-power adder reported in the literature. The proposed BiDPL adder outperforms in power efficiency both designs at 1.5 V by as much as 61 % and 535 % respectively.","PeriodicalId":177613,"journal":{"name":"Conference Proceedings. IEEE Canadian Conference on Electrical and Computer Engineering (Cat. No.98TH8341)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126848231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-05-24DOI: 10.1109/CCECE.1998.682768
M. Leclere, J. Lambert, R. Lord, Y. Hebert
This paper describes a new adaptive algorithm which estimates the positive sequence voltage phasor in a series compensated network with a high precision. This measurement is used in a shunt reactor switching scheme which will control voltage profiles along the Hydro-Quebec transmission grid. The particular nature of the noise observed in the voltage wave forms is discussed. The noise particularities have been considered in the development of the algorithm. The real time implementation of the algorithm is briefly discussed.
{"title":"New adaptive algorithm for precise voltage phasor measurement in a series compensated network","authors":"M. Leclere, J. Lambert, R. Lord, Y. Hebert","doi":"10.1109/CCECE.1998.682768","DOIUrl":"https://doi.org/10.1109/CCECE.1998.682768","url":null,"abstract":"This paper describes a new adaptive algorithm which estimates the positive sequence voltage phasor in a series compensated network with a high precision. This measurement is used in a shunt reactor switching scheme which will control voltage profiles along the Hydro-Quebec transmission grid. The particular nature of the noise observed in the voltage wave forms is discussed. The noise particularities have been considered in the development of the algorithm. The real time implementation of the algorithm is briefly discussed.","PeriodicalId":177613,"journal":{"name":"Conference Proceedings. IEEE Canadian Conference on Electrical and Computer Engineering (Cat. No.98TH8341)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127065927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-05-24DOI: 10.1109/CCECE.1998.685638
K. Kwok, C. Selvakumar
We report the boron diffusion characteristics in Ge/sup +/-implanted Si with a peak Ge fraction of 12% and a B dose of 10/sup 12/ cm/sup -2/, annealed at 900/spl deg/C for 80 mins in a N/sub 2/ ambient. The boron diffusivity is four times lower than that in Si implanted with the same dose of B and annealed under identical conditions. TEM studies and SIMS results confirm the presence of extended defects in the surface region, end-of-range (EOR) defective region beyond the amorphous/crystalline interface (X/sub a/c/), and threading dislocations in between. The retardation is partially due to the trapping of B atoms and/or self-interstitials by extended defects remaining after the solid phase epitaxy. Future work is required if the dominant cause is to be determined.
{"title":"Boron diffusion in high-dose germanium-implanted silicon","authors":"K. Kwok, C. Selvakumar","doi":"10.1109/CCECE.1998.685638","DOIUrl":"https://doi.org/10.1109/CCECE.1998.685638","url":null,"abstract":"We report the boron diffusion characteristics in Ge/sup +/-implanted Si with a peak Ge fraction of 12% and a B dose of 10/sup 12/ cm/sup -2/, annealed at 900/spl deg/C for 80 mins in a N/sub 2/ ambient. The boron diffusivity is four times lower than that in Si implanted with the same dose of B and annealed under identical conditions. TEM studies and SIMS results confirm the presence of extended defects in the surface region, end-of-range (EOR) defective region beyond the amorphous/crystalline interface (X/sub a/c/), and threading dislocations in between. The retardation is partially due to the trapping of B atoms and/or self-interstitials by extended defects remaining after the solid phase epitaxy. Future work is required if the dominant cause is to be determined.","PeriodicalId":177613,"journal":{"name":"Conference Proceedings. IEEE Canadian Conference on Electrical and Computer Engineering (Cat. No.98TH8341)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121385848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-05-24DOI: 10.1109/CCECE.1998.685594
L.F. Johnson
It is difficult to study industrial programmer productivity because of the extreme variance seen among individual programmers and the difficulty of performing controlled experiments. As an alternative to studying individual programmers, we examine the group productivity of programmer teams. We postulate that there is such a thing as average programmer productivity, in a given context. By studying programmer teams, we can eventually obtain measures of the expected performance of an average programmer in a defined context. Differences in project productivity can then be attributed to process characteristics. Existing project data is examined to see how data could be collected to support the idea of a standard programmer.
{"title":"On measuring programmer team productivity","authors":"L.F. Johnson","doi":"10.1109/CCECE.1998.685594","DOIUrl":"https://doi.org/10.1109/CCECE.1998.685594","url":null,"abstract":"It is difficult to study industrial programmer productivity because of the extreme variance seen among individual programmers and the difficulty of performing controlled experiments. As an alternative to studying individual programmers, we examine the group productivity of programmer teams. We postulate that there is such a thing as average programmer productivity, in a given context. By studying programmer teams, we can eventually obtain measures of the expected performance of an average programmer in a defined context. Differences in project productivity can then be attributed to process characteristics. Existing project data is examined to see how data could be collected to support the idea of a standard programmer.","PeriodicalId":177613,"journal":{"name":"Conference Proceedings. IEEE Canadian Conference on Electrical and Computer Engineering (Cat. No.98TH8341)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121506103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-05-24DOI: 10.1109/CCECE.1998.685640
M. Boulmalf, G. Delisle
The finite-difference time-domain (FDTD) method is used to analyse and optimize the broadband characteristics of an electromagnetically coupled microstrip antenna using a short tuning stub in the microstrip feedline as the optimizing device. Frequency domain parameters are calculated over the entire frequency of interest and extended to fast Fourier transforms. The electromagnetically coupled microstrip antenna is treated using the FDTD method.
{"title":"Optimization of coupled microstrip antenna in the 2.4 GHz ISM band","authors":"M. Boulmalf, G. Delisle","doi":"10.1109/CCECE.1998.685640","DOIUrl":"https://doi.org/10.1109/CCECE.1998.685640","url":null,"abstract":"The finite-difference time-domain (FDTD) method is used to analyse and optimize the broadband characteristics of an electromagnetically coupled microstrip antenna using a short tuning stub in the microstrip feedline as the optimizing device. Frequency domain parameters are calculated over the entire frequency of interest and extended to fast Fourier transforms. The electromagnetically coupled microstrip antenna is treated using the FDTD method.","PeriodicalId":177613,"journal":{"name":"Conference Proceedings. IEEE Canadian Conference on Electrical and Computer Engineering (Cat. No.98TH8341)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128934939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-05-24DOI: 10.1109/CCECE.1998.685564
F. Mo, W. Kinsner
This paper presents a new power line fault classification scheme using a probabilistic neural network (PNN). One of the major features of PNN stems from its modular architecture design and can be easily extended to adapt to a changing environment by incremental learning. Another distinguishing advantage of PNN comes from its fast training speed as compared to backpropagation. An explicit confidence measure can also be obtained which directly supports the decision made by the PNN. Preliminary experimental classification results of various AC power system faults and transients indicate that the PNN is suitable for power line fault classification.
{"title":"Probabilistic neural networks for power line fault classification","authors":"F. Mo, W. Kinsner","doi":"10.1109/CCECE.1998.685564","DOIUrl":"https://doi.org/10.1109/CCECE.1998.685564","url":null,"abstract":"This paper presents a new power line fault classification scheme using a probabilistic neural network (PNN). One of the major features of PNN stems from its modular architecture design and can be easily extended to adapt to a changing environment by incremental learning. Another distinguishing advantage of PNN comes from its fast training speed as compared to backpropagation. An explicit confidence measure can also be obtained which directly supports the decision made by the PNN. Preliminary experimental classification results of various AC power system faults and transients indicate that the PNN is suitable for power line fault classification.","PeriodicalId":177613,"journal":{"name":"Conference Proceedings. IEEE Canadian Conference on Electrical and Computer Engineering (Cat. No.98TH8341)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130375681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-05-24DOI: 10.1109/CCECE.1998.682783
S. Wesolkowski, P. Bowman, David Tunnah
This paper describes a potential implementation of a high speed colour cheque image processing system. The description starts with the overall architecture of a colour image capture system. The system's image processing capabilities include gray balancing, colour space conversion, colour image binarization to segment the text from the background and could include in the future cheque amount recognition from the binary image. An original algorithm based on colour clustering is introduced to improve the image binarization process. To test various components of the system, a prototype colour image capture system was built. Initial results on image binarization are shown.
{"title":"A high speed colour cheque image capture and processing system","authors":"S. Wesolkowski, P. Bowman, David Tunnah","doi":"10.1109/CCECE.1998.682783","DOIUrl":"https://doi.org/10.1109/CCECE.1998.682783","url":null,"abstract":"This paper describes a potential implementation of a high speed colour cheque image processing system. The description starts with the overall architecture of a colour image capture system. The system's image processing capabilities include gray balancing, colour space conversion, colour image binarization to segment the text from the background and could include in the future cheque amount recognition from the binary image. An original algorithm based on colour clustering is introduced to improve the image binarization process. To test various components of the system, a prototype colour image capture system was built. Initial results on image binarization are shown.","PeriodicalId":177613,"journal":{"name":"Conference Proceedings. IEEE Canadian Conference on Electrical and Computer Engineering (Cat. No.98TH8341)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132592427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-05-24DOI: 10.1109/CCECE.1998.682552
G.D. Sugavanam, M. Morcos, N. Dillman
A twelve-phase battery charger for electric vehicles (EVs) is presented. A microprocessor controls the charging profile of the battery. A constant-current charging method is used. Thyristors control the output voltage of the charger through digital control of the firing angle. A motor-generator set is used to simulate the load to the charger for test conditions. The charger creates less harmonic distortion compared to a typical power supply.
{"title":"Performance of multiphase microprocessor-based battery charger for electric vehicles","authors":"G.D. Sugavanam, M. Morcos, N. Dillman","doi":"10.1109/CCECE.1998.682552","DOIUrl":"https://doi.org/10.1109/CCECE.1998.682552","url":null,"abstract":"A twelve-phase battery charger for electric vehicles (EVs) is presented. A microprocessor controls the charging profile of the battery. A constant-current charging method is used. Thyristors control the output voltage of the charger through digital control of the firing angle. A motor-generator set is used to simulate the load to the charger for test conditions. The charger creates less harmonic distortion compared to a typical power supply.","PeriodicalId":177613,"journal":{"name":"Conference Proceedings. IEEE Canadian Conference on Electrical and Computer Engineering (Cat. No.98TH8341)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121202686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-05-24DOI: 10.1109/CCECE.1998.685563
F. Mo, W. Kinsner
This paper presents a scheme for predicting and modelling of nonstationary signals possessing fractal characteristics, using a resource-allocating network (RAN). One significant feature of a RAN is its ability to allocate resources corresponding to the complexity of nonstationary signals, thus tracking and matching the complexity of nonstationary signals can be achieved. The experimental results of predicting chaotic time series and short-term power load have shown RAN is suitable for modelling and predicting such nonstationary signals with the fundamental advantage of complexity matching and tracking capability.
{"title":"Predicting and modelling of nonstationary temporal signals with fractal characteristics","authors":"F. Mo, W. Kinsner","doi":"10.1109/CCECE.1998.685563","DOIUrl":"https://doi.org/10.1109/CCECE.1998.685563","url":null,"abstract":"This paper presents a scheme for predicting and modelling of nonstationary signals possessing fractal characteristics, using a resource-allocating network (RAN). One significant feature of a RAN is its ability to allocate resources corresponding to the complexity of nonstationary signals, thus tracking and matching the complexity of nonstationary signals can be achieved. The experimental results of predicting chaotic time series and short-term power load have shown RAN is suitable for modelling and predicting such nonstationary signals with the fundamental advantage of complexity matching and tracking capability.","PeriodicalId":177613,"journal":{"name":"Conference Proceedings. IEEE Canadian Conference on Electrical and Computer Engineering (Cat. No.98TH8341)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117267746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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