Pub Date : 2017-11-01DOI: 10.1109/ICSESS.2017.8342925
Tin Ban, Zhiqiang Wei, Yun Gao, Z. Li, Changhe Du, Wenjuan Shi
Through analyses on performances of Web frontend, we can learn about the bottlenecks of Web performance, the load limit and connection limit of browser. In this paper, the optimization strategies were carried out to accommodate the bottlenecks and a new request scheduling algorithm with AQSM was proposed to resolve the two connection restrictions. Some optimization strategies were used to settle the frontend performance problems of some webpages, and the results were in good performances.
{"title":"Optimization strategies based on algorithm for queue scheduling model and applications of web frontend performance","authors":"Tin Ban, Zhiqiang Wei, Yun Gao, Z. Li, Changhe Du, Wenjuan Shi","doi":"10.1109/ICSESS.2017.8342925","DOIUrl":"https://doi.org/10.1109/ICSESS.2017.8342925","url":null,"abstract":"Through analyses on performances of Web frontend, we can learn about the bottlenecks of Web performance, the load limit and connection limit of browser. In this paper, the optimization strategies were carried out to accommodate the bottlenecks and a new request scheduling algorithm with AQSM was proposed to resolve the two connection restrictions. Some optimization strategies were used to settle the frontend performance problems of some webpages, and the results were in good performances.","PeriodicalId":179815,"journal":{"name":"2017 8th IEEE International Conference on Software Engineering and Service Science (ICSESS)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132338210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICSESS.2017.8342876
Chanchai Supaartagorn
A flowchart can be a graphic diagram representation of a programming logic. There are shapes and connectors that represent the different types of actions or steps in a process. A flowchart is a very important tool in the planning phase in a program development cycle. Programmers can use it to design and develop an algorithm of a program. Moreover, a flowchart is also very effective for visual learners to write and comprehend algorithms in computer programming courses. This paper aims to provide a tool which serves as an automatic code generator using a structured flowchart. The tool is composed of basic flowchart shapes to be combined into a structured flowchart that can be converted into source codes. In addition, the system's performance has been evaluated by two groups: 5 experts and 93 general users. The results showed the average values of the satisfaction levels were 4.48 and 4.27 with standard deviations at 0.59 and 0.64 for the experts and the general users respectively. It was found that the system performance of the tool reached an agree level. It was revealed that the developed system can be used precisely as intended in an effective manner.
{"title":"Web application for automatic code generator using a structured flowchart","authors":"Chanchai Supaartagorn","doi":"10.1109/ICSESS.2017.8342876","DOIUrl":"https://doi.org/10.1109/ICSESS.2017.8342876","url":null,"abstract":"A flowchart can be a graphic diagram representation of a programming logic. There are shapes and connectors that represent the different types of actions or steps in a process. A flowchart is a very important tool in the planning phase in a program development cycle. Programmers can use it to design and develop an algorithm of a program. Moreover, a flowchart is also very effective for visual learners to write and comprehend algorithms in computer programming courses. This paper aims to provide a tool which serves as an automatic code generator using a structured flowchart. The tool is composed of basic flowchart shapes to be combined into a structured flowchart that can be converted into source codes. In addition, the system's performance has been evaluated by two groups: 5 experts and 93 general users. The results showed the average values of the satisfaction levels were 4.48 and 4.27 with standard deviations at 0.59 and 0.64 for the experts and the general users respectively. It was found that the system performance of the tool reached an agree level. It was revealed that the developed system can be used precisely as intended in an effective manner.","PeriodicalId":179815,"journal":{"name":"2017 8th IEEE International Conference on Software Engineering and Service Science (ICSESS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133246683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICSESS.2017.8342883
Amr Megahed, Sondos M. Fadl, Q. Han, Qiong Li
Document forgery detection is a vitally important field because the forensic role is used in many types of crimes. Adding new text is the most common type of document forgery methods because it is easy to apply and hard to detect. In this paper, a novel method is proposed to detect the forgery in a text by detecting different ink using image processing instead of conventional methods. All documents are scanned as an image and segmented into objects. Then nine features are extracted from each object based on red, green and blue channels. Distance measurements between each nearby pairs of feature vectors are computed using root mean square error. Modified Thompson Tau test is applied to extract anomaly points. The tampered points are then obtained exactly from anomaly points. Modified Thompson Tau test has a high-efficiency detection and a low omission ratio but its precision is not ideal. Therefore, the second outlier detection has been used to help to make up the difference in precision. The experimental results show that our proposed method can not only detect but also localize tampered objects efficiently.
{"title":"Handwriting forgery detection based on ink colour features","authors":"Amr Megahed, Sondos M. Fadl, Q. Han, Qiong Li","doi":"10.1109/ICSESS.2017.8342883","DOIUrl":"https://doi.org/10.1109/ICSESS.2017.8342883","url":null,"abstract":"Document forgery detection is a vitally important field because the forensic role is used in many types of crimes. Adding new text is the most common type of document forgery methods because it is easy to apply and hard to detect. In this paper, a novel method is proposed to detect the forgery in a text by detecting different ink using image processing instead of conventional methods. All documents are scanned as an image and segmented into objects. Then nine features are extracted from each object based on red, green and blue channels. Distance measurements between each nearby pairs of feature vectors are computed using root mean square error. Modified Thompson Tau test is applied to extract anomaly points. The tampered points are then obtained exactly from anomaly points. Modified Thompson Tau test has a high-efficiency detection and a low omission ratio but its precision is not ideal. Therefore, the second outlier detection has been used to help to make up the difference in precision. The experimental results show that our proposed method can not only detect but also localize tampered objects efficiently.","PeriodicalId":179815,"journal":{"name":"2017 8th IEEE International Conference on Software Engineering and Service Science (ICSESS)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116365466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICSESS.2017.8342861
Chunjiang Yan, Chuang Wang, J. Du, Hualin Fang, Yixuan Wang, Xuezhi Xiang, Xinli Guo
A two-step method based on deep learning is proposed for the intrusion detection of engineering vehicles working under high power transmission lines. In the first step, intrusion detection algorithm is used to identify the potential target area. Then the results are supplied to a trained deep convolution neural network classifier. This way combining intrusion detection method with CNN, the invasion of the engineering vehicles under high power transmission lines can efficiently be detected up to an accuracy of 97.2 %.
{"title":"Intrusion detection for engineering vehicles under the transmission line based on deep learning","authors":"Chunjiang Yan, Chuang Wang, J. Du, Hualin Fang, Yixuan Wang, Xuezhi Xiang, Xinli Guo","doi":"10.1109/ICSESS.2017.8342861","DOIUrl":"https://doi.org/10.1109/ICSESS.2017.8342861","url":null,"abstract":"A two-step method based on deep learning is proposed for the intrusion detection of engineering vehicles working under high power transmission lines. In the first step, intrusion detection algorithm is used to identify the potential target area. Then the results are supplied to a trained deep convolution neural network classifier. This way combining intrusion detection method with CNN, the invasion of the engineering vehicles under high power transmission lines can efficiently be detected up to an accuracy of 97.2 %.","PeriodicalId":179815,"journal":{"name":"2017 8th IEEE International Conference on Software Engineering and Service Science (ICSESS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115469372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICSESS.2017.8342994
Xiang Wang, Bin Xu, Weike Wang, Lin Li, Pei Du, Cheng Zhou, Mingzhe Li, Tongsheng Xia
Most embedded systems contain a number of software vulnerabilities, such as program buffer overflow. The physical attacks in embedded systems are also becoming more and more common. This paper presents a fast, effective and reliable algorithm for tagging and validating what can be used in embedded systems. The compiler automatically collects the secure tags for each main memory segment at compile time. At run-time, the designed hardware observes the dynamic execution trace, and checks whether the trace conforms to the permissible behavior and triggers the appropriate response mechanisms according to the check result. This design does not change the compiler or the existing instruction set, with no restriction on the software developer. The design is implemented on an actual SOPC platform. Experimental analysis shows that the proposed techniques can eliminate a wide range of common software and physical attacks, with low performance penalties and minimal overheads.
{"title":"A novel security validation in embedded system","authors":"Xiang Wang, Bin Xu, Weike Wang, Lin Li, Pei Du, Cheng Zhou, Mingzhe Li, Tongsheng Xia","doi":"10.1109/ICSESS.2017.8342994","DOIUrl":"https://doi.org/10.1109/ICSESS.2017.8342994","url":null,"abstract":"Most embedded systems contain a number of software vulnerabilities, such as program buffer overflow. The physical attacks in embedded systems are also becoming more and more common. This paper presents a fast, effective and reliable algorithm for tagging and validating what can be used in embedded systems. The compiler automatically collects the secure tags for each main memory segment at compile time. At run-time, the designed hardware observes the dynamic execution trace, and checks whether the trace conforms to the permissible behavior and triggers the appropriate response mechanisms according to the check result. This design does not change the compiler or the existing instruction set, with no restriction on the software developer. The design is implemented on an actual SOPC platform. Experimental analysis shows that the proposed techniques can eliminate a wide range of common software and physical attacks, with low performance penalties and minimal overheads.","PeriodicalId":179815,"journal":{"name":"2017 8th IEEE International Conference on Software Engineering and Service Science (ICSESS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123886948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICSESS.2017.8343037
Yiwei Wu, Xiaoling Xia, Jiajing Le
Evaluating students' achievements which including many subjects is a great challenge. It seems not so accurate that simply adding these scores and ranking, because it is difficult to distinguish which one is a student good at and which one is not. Data mining is a good way to solve this problem. In this paper, students' achievements are appraised based on factor analysis and cluster analysis. First, common factors are extracted from scores of multitudinous subjects. Then factor scores and comprehensive scores can be computed. After that, all students can be segregated into several clusters by cluster analysis based on factor scores. The result shows objective synthetical evaluation of students, which will benefit education in the future.
{"title":"Evaluation of students' achievements based on factor analysis and cluster analysis","authors":"Yiwei Wu, Xiaoling Xia, Jiajing Le","doi":"10.1109/ICSESS.2017.8343037","DOIUrl":"https://doi.org/10.1109/ICSESS.2017.8343037","url":null,"abstract":"Evaluating students' achievements which including many subjects is a great challenge. It seems not so accurate that simply adding these scores and ranking, because it is difficult to distinguish which one is a student good at and which one is not. Data mining is a good way to solve this problem. In this paper, students' achievements are appraised based on factor analysis and cluster analysis. First, common factors are extracted from scores of multitudinous subjects. Then factor scores and comprehensive scores can be computed. After that, all students can be segregated into several clusters by cluster analysis based on factor scores. The result shows objective synthetical evaluation of students, which will benefit education in the future.","PeriodicalId":179815,"journal":{"name":"2017 8th IEEE International Conference on Software Engineering and Service Science (ICSESS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127923767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICSESS.2017.8342863
Oscar Karnalim
Despite the fact that plagiarizing source code is a trivial task for most CS students, detecting such unethical behavior requires a considerable amount of effort. Thus, several plagiarism detection systems were developed to handle such issue. This paper extends Karnalim's work, a low-level approach for detecting Java source code plagiarism, by incorporating abstract method linearization. Such extension is incorporated to enhance the accuracy of low-level approach in term of detecting plagiarism in object-oriented environment. According to our evaluation, which was conducted based on 23 design-pattern source code pairs, our extended low-level approach is more effective than state-of-the-art and Karnalim's approach. On the one hand, when compared to state-of-the-art approach, our approach can generate less coincidental similarities and provide more accurate result. On the other hand, when compared to Karnalim's approach, our approach, at some extent, can generate higher similarity when simple abstract method invocation is incorporated.
{"title":"An abstract method linearization for detecting source code plagiarism in object-oriented environment","authors":"Oscar Karnalim","doi":"10.1109/ICSESS.2017.8342863","DOIUrl":"https://doi.org/10.1109/ICSESS.2017.8342863","url":null,"abstract":"Despite the fact that plagiarizing source code is a trivial task for most CS students, detecting such unethical behavior requires a considerable amount of effort. Thus, several plagiarism detection systems were developed to handle such issue. This paper extends Karnalim's work, a low-level approach for detecting Java source code plagiarism, by incorporating abstract method linearization. Such extension is incorporated to enhance the accuracy of low-level approach in term of detecting plagiarism in object-oriented environment. According to our evaluation, which was conducted based on 23 design-pattern source code pairs, our extended low-level approach is more effective than state-of-the-art and Karnalim's approach. On the one hand, when compared to state-of-the-art approach, our approach can generate less coincidental similarities and provide more accurate result. On the other hand, when compared to Karnalim's approach, our approach, at some extent, can generate higher similarity when simple abstract method invocation is incorporated.","PeriodicalId":179815,"journal":{"name":"2017 8th IEEE International Conference on Software Engineering and Service Science (ICSESS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128184916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a reconfigurable high performance multiplier (RHPM) based on multi-granularity design and parallel acceleration. Capable of supporting multiple precisions for different processing requirements, the RHPM can perform one 32×32, two 16×16, or four 8×8 bit unsigned/signed multiplication, or one 16×16, or two 8×8 bit complex number multiplication. The structures of the partial product generator and the partial product accumulator are improved in the paper, so as to reuse most of the hardware resources. Compression can be completed automatically by means of recording the validity of every bit in the partial product array which accelerates the computation dramatically. The RHPM is implemented with TSMC 28nm technology, exhibiting a 0.68s of the critical path delay, while consuming only 0.6281mW in power. Results show its significant superiority in terms of performance and power efficiency compared with our previous work or other similar products.
{"title":"A reconfigurable high-performance multiplier based on multi-granularity design and parallel acceleration","authors":"Feng Jing, Zijun Liu, Xiaojun Ma, Guo Yang, Guo Peng, Donglin Wang","doi":"10.1109/ICSESS.2017.8342979","DOIUrl":"https://doi.org/10.1109/ICSESS.2017.8342979","url":null,"abstract":"This paper proposes a reconfigurable high performance multiplier (RHPM) based on multi-granularity design and parallel acceleration. Capable of supporting multiple precisions for different processing requirements, the RHPM can perform one 32×32, two 16×16, or four 8×8 bit unsigned/signed multiplication, or one 16×16, or two 8×8 bit complex number multiplication. The structures of the partial product generator and the partial product accumulator are improved in the paper, so as to reuse most of the hardware resources. Compression can be completed automatically by means of recording the validity of every bit in the partial product array which accelerates the computation dramatically. The RHPM is implemented with TSMC 28nm technology, exhibiting a 0.68s of the critical path delay, while consuming only 0.6281mW in power. Results show its significant superiority in terms of performance and power efficiency compared with our previous work or other similar products.","PeriodicalId":179815,"journal":{"name":"2017 8th IEEE International Conference on Software Engineering and Service Science (ICSESS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128007639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICSESS.2017.8342922
Tianyi Lan, Qing Han, Hongwei Fan, Julong Lan
While there has been a belief over the past few years that virtual network functions (VNFs) should be built on common servers, we argue that it can lead to limited performance and large up/down traffic. This paper proposes a new idea of shifting part of NFV functions from software packages to common hardware devices to promote overall performance. Then we present the design and implementation of PPAP, a Packets Processing Acceleration Platform for NFV. It offers high flexibility by allowing functions to control the processing flow of hardware. Dynamic match tables and virtualization techniques ensure isolation among VNF instances.
{"title":"FPGA-based packets processing acceleration platform for VNF","authors":"Tianyi Lan, Qing Han, Hongwei Fan, Julong Lan","doi":"10.1109/ICSESS.2017.8342922","DOIUrl":"https://doi.org/10.1109/ICSESS.2017.8342922","url":null,"abstract":"While there has been a belief over the past few years that virtual network functions (VNFs) should be built on common servers, we argue that it can lead to limited performance and large up/down traffic. This paper proposes a new idea of shifting part of NFV functions from software packages to common hardware devices to promote overall performance. Then we present the design and implementation of PPAP, a Packets Processing Acceleration Platform for NFV. It offers high flexibility by allowing functions to control the processing flow of hardware. Dynamic match tables and virtualization techniques ensure isolation among VNF instances.","PeriodicalId":179815,"journal":{"name":"2017 8th IEEE International Conference on Software Engineering and Service Science (ICSESS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130027180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICSESS.2017.8342907
Pinghua Zhang
In order to overcome the shortcomings of artificial bee colony algorithm induding slow convergence speed, easily falling into local optimum value, neglect of development and other issues, Mechanism of other bionic intelligent optimization algorithms, A new algorithm of Global Artificial Bee Colony algorithm based on crossover which can effectively improve the convergence rate, enhance the development of the algorithm and the global optimization ability is proposed, and the algorithm can effectively avoid the local optimum. Finally, the Seven standard test functions are selected to carry out the experiment and simulation. The results show that the convergence speed and accuracy of the proposed algorithm (CGABC) are significantly improved compared with other algorithms such as ABC algorithm, GABC algorithm and so on.
{"title":"Research on global artificial bee colony algorithm based on crossover","authors":"Pinghua Zhang","doi":"10.1109/ICSESS.2017.8342907","DOIUrl":"https://doi.org/10.1109/ICSESS.2017.8342907","url":null,"abstract":"In order to overcome the shortcomings of artificial bee colony algorithm induding slow convergence speed, easily falling into local optimum value, neglect of development and other issues, Mechanism of other bionic intelligent optimization algorithms, A new algorithm of Global Artificial Bee Colony algorithm based on crossover which can effectively improve the convergence rate, enhance the development of the algorithm and the global optimization ability is proposed, and the algorithm can effectively avoid the local optimum. Finally, the Seven standard test functions are selected to carry out the experiment and simulation. The results show that the convergence speed and accuracy of the proposed algorithm (CGABC) are significantly improved compared with other algorithms such as ABC algorithm, GABC algorithm and so on.","PeriodicalId":179815,"journal":{"name":"2017 8th IEEE International Conference on Software Engineering and Service Science (ICSESS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130985013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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