Semiconductor manufacturers aim at delivering new devices within shorter times in order to gain market shares. First silicon debug is an important issue in order to minimize the time-to-market. In this paper we propose an Infrastructure IP (I-IP) intended to be a companion for processor cores. The proposed I-IP is an efficient, low-cost and easy-to-adopt solution for supporting the silicon debug of microprocessor cores and of other cores in a SoC, as it reuses the hardware introduced for implementing processor software-based self test (SBST)
{"title":"Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores","authors":"P. Bernardi, M. Grosso, M. Rebaudengo, M. Reorda","doi":"10.1109/MTV.2005.11","DOIUrl":"https://doi.org/10.1109/MTV.2005.11","url":null,"abstract":"Semiconductor manufacturers aim at delivering new devices within shorter times in order to gain market shares. First silicon debug is an important issue in order to minimize the time-to-market. In this paper we propose an Infrastructure IP (I-IP) intended to be a companion for processor cores. The proposed I-IP is an efficient, low-cost and easy-to-adopt solution for supporting the silicon debug of microprocessor cores and of other cores in a SoC, as it reuses the hardware introduced for implementing processor software-based self test (SBST)","PeriodicalId":179953,"journal":{"name":"2005 Sixth International Workshop on Microprocessor Test and Verification","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125318781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Design verification by property checking is a mandatory task during circuit design. In this context, bounded model checking (BMC) has become popular for falsifying erroneous designs. Additionally, the analysis of partial designs, i.e., circuits that are not fully specified, has recently gained attraction. In this work we analyze how BMC can be applied to such partial designs. Our experiments show that even with the most simple modelling scheme, namely 01X-simulation, a relevant number of errors can be detected. Additionally, we propose a SAT-solver that directly can handle 01X-logic
{"title":"On SAT-based Bounded Invariant Checking of Blackbox Designs","authors":"Marc Herbstritt, B. Becker","doi":"10.1109/MTV.2005.16","DOIUrl":"https://doi.org/10.1109/MTV.2005.16","url":null,"abstract":"Design verification by property checking is a mandatory task during circuit design. In this context, bounded model checking (BMC) has become popular for falsifying erroneous designs. Additionally, the analysis of partial designs, i.e., circuits that are not fully specified, has recently gained attraction. In this work we analyze how BMC can be applied to such partial designs. Our experiments show that even with the most simple modelling scheme, namely 01X-simulation, a relevant number of errors can be detected. Additionally, we propose a SAT-solver that directly can handle 01X-logic","PeriodicalId":179953,"journal":{"name":"2005 Sixth International Workshop on Microprocessor Test and Verification","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130659486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper we describe PaMira, a powerful distributed SAT solver. PaMira is based on the highly optimized, sequential SAT engine Mira, incorporating all essential optimization techniques modern algorithms utilize to maximize performance. For the distributed execution an efficient work stealing method has been implemented. PaMira also employs the exchange of conflict clauses between the processes to guide the search more efficiently. We provide experimental results showing linear speedup on a multiprocessor environment with four AMD Opteron processors
{"title":"PaMira - A Parallel SAT Solver with Knowledge Sharing","authors":"Tobias Schubert, Matthew D. T. Lewis, B. Becker","doi":"10.1109/MTV.2005.17","DOIUrl":"https://doi.org/10.1109/MTV.2005.17","url":null,"abstract":"In this paper we describe PaMira, a powerful distributed SAT solver. PaMira is based on the highly optimized, sequential SAT engine Mira, incorporating all essential optimization techniques modern algorithms utilize to maximize performance. For the distributed execution an efficient work stealing method has been implemented. PaMira also employs the exchange of conflict clauses between the processes to guide the search more efficiently. We provide experimental results showing linear speedup on a multiprocessor environment with four AMD Opteron processors","PeriodicalId":179953,"journal":{"name":"2005 Sixth International Workshop on Microprocessor Test and Verification","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132350190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Embedded memories form a crucial part in the design of modern high performance microprocessors. The number of transistors in memories forms a majority of the transistors in a typical high performance microprocessor. Therefore, modeling embedded memories is an important challenge in high performance microprocessor design. A typical design process involves a multiplicity of interacting methodologies - simulation, formal verification, design for test, emulation etc. Memory models are needed for each of these methodologies. This complicates the process of modeling memories. The authors present a tool called MemGen that automates memory model generation for all methodologies. It has been used in-house in Motorola Inc. and then later in Freescale Semiconductor Inc. in all high performance design projects. The authors present result obtained by using MemGen-generated embedded memories in real life design projects of PowerPCreg G2 and G4 microprocessors
{"title":"Automatic Generation of High Performance Embedded Memory Models for PowerPC Microprocessors","authors":"J. Bhadra, M. Abadir, D. Burgess, E. Trofimova","doi":"10.1109/MTV.2005.9","DOIUrl":"https://doi.org/10.1109/MTV.2005.9","url":null,"abstract":"Embedded memories form a crucial part in the design of modern high performance microprocessors. The number of transistors in memories forms a majority of the transistors in a typical high performance microprocessor. Therefore, modeling embedded memories is an important challenge in high performance microprocessor design. A typical design process involves a multiplicity of interacting methodologies - simulation, formal verification, design for test, emulation etc. Memory models are needed for each of these methodologies. This complicates the process of modeling memories. The authors present a tool called MemGen that automates memory model generation for all methodologies. It has been used in-house in Motorola Inc. and then later in Freescale Semiconductor Inc. in all high performance design projects. The authors present result obtained by using MemGen-generated embedded memories in real life design projects of PowerPCreg G2 and G4 microprocessors","PeriodicalId":179953,"journal":{"name":"2005 Sixth International Workshop on Microprocessor Test and Verification","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122955494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The mutation based validation paradigm (MVP) is a validation environment for high-level microprocessor implementations. To be able to efficiently identify and analyze the architectural states (prospect states) that can possibly satisfy a set of constraints during MVP's test generation, the authors need to reduce the search space in the analysis process as early as possible. In this paper, the authors present some optimizations in the search space that speed up the overall test generation process
{"title":"Search-Space Optimizations for High-Level ATPG","authors":"J. Campos, H. Al-Asaad","doi":"10.1109/MTV.2005.23","DOIUrl":"https://doi.org/10.1109/MTV.2005.23","url":null,"abstract":"The mutation based validation paradigm (MVP) is a validation environment for high-level microprocessor implementations. To be able to efficiently identify and analyze the architectural states (prospect states) that can possibly satisfy a set of constraints during MVP's test generation, the authors need to reduce the search space in the analysis process as early as possible. In this paper, the authors present some optimizations in the search space that speed up the overall test generation process","PeriodicalId":179953,"journal":{"name":"2005 Sixth International Workshop on Microprocessor Test and Verification","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124767134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Today, the underlying hardware of embedded systems is often verified successfully. In this context formal verification techniques allow to prove the correctness. But in embedded system design the integration of software components becomes more and more important. In this paper the authors present an integrated approach for formal verification of hardware and software. The approach is demonstrated on a RISC CPU. The verification is based on bounded model checking. Besides correctness proofs of the underlying hardware the hardware/software interface and programs using this interface can be formally verified
{"title":"HW/SW Co-Verification of a RISC CPU using Bounded Model Checking","authors":"Daniel Große, U. Kühne, R. Drechsler","doi":"10.1109/MTV.2005.12","DOIUrl":"https://doi.org/10.1109/MTV.2005.12","url":null,"abstract":"Today, the underlying hardware of embedded systems is often verified successfully. In this context formal verification techniques allow to prove the correctness. But in embedded system design the integration of software components becomes more and more important. In this paper the authors present an integrated approach for formal verification of hardware and software. The approach is demonstrated on a RISC CPU. The verification is based on bounded model checking. Besides correctness proofs of the underlying hardware the hardware/software interface and programs using this interface can be formally verified","PeriodicalId":179953,"journal":{"name":"2005 Sixth International Workshop on Microprocessor Test and Verification","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117342107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
High performance designs must conform to stringent timing requirements. Designers frequently utilize low-level optimization techniques and develop many iterations of the same block in order to close a timing gap. Simulation with random stimulus is the traditional method for verifying that these changes do not introduce a change in the functional behavior of the block. For the development of a new high-performance core at Freescale Semiconductor the authors decided to instead research the possibility of using formal techniques, in the form of sequential equivalence checking, for this form of verification. Various equivalence checking tools were evaluated for this task. Initial results looked promising and the authors decided to integrate this capability into our design flow. This paper describes the experience and also addresses some of the problems that were exposed and how we plan to deal with them
{"title":"Retiming Verification Using Sequential Equivalence Checking","authors":"B. Kahne, M. Abadir","doi":"10.1109/MTV.2005.22","DOIUrl":"https://doi.org/10.1109/MTV.2005.22","url":null,"abstract":"High performance designs must conform to stringent timing requirements. Designers frequently utilize low-level optimization techniques and develop many iterations of the same block in order to close a timing gap. Simulation with random stimulus is the traditional method for verifying that these changes do not introduce a change in the functional behavior of the block. For the development of a new high-performance core at Freescale Semiconductor the authors decided to instead research the possibility of using formal techniques, in the form of sequential equivalence checking, for this form of verification. Various equivalence checking tools were evaluated for this task. Initial results looked promising and the authors decided to integrate this capability into our design flow. This paper describes the experience and also addresses some of the problems that were exposed and how we plan to deal with them","PeriodicalId":179953,"journal":{"name":"2005 Sixth International Workshop on Microprocessor Test and Verification","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124528242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As circuits scale to ever smaller feature sizes, the types of defects that occur become increasingly complex and difficult to model. They generally do not behave like the faults considered during test pattern generation and therefore must be fortuitously detected by the pattern set. This mismatch of faults and defects also poses significant problems for diagnosis. This presentation describes a preliminary investigation into the use of mandatory conditions for the detection of both faults and defects with applications to defect diagnosis. It will show that multiple site observations and good excitation balance are essential not only for adequate fortuitous defect detection-they are also necessary for the determination of the mandatory conditions and implications that accompany those detections, and thus enable the diagnosis of these fortuitously detected and unmodeled defects as well
{"title":"An Investigation of Excitation Balance and Additional Mandatory Conditions for the Diagnosis of Fortuitously Detected Defects","authors":"Jennifer Dworak","doi":"10.1109/MTV.2005.6","DOIUrl":"https://doi.org/10.1109/MTV.2005.6","url":null,"abstract":"As circuits scale to ever smaller feature sizes, the types of defects that occur become increasingly complex and difficult to model. They generally do not behave like the faults considered during test pattern generation and therefore must be fortuitously detected by the pattern set. This mismatch of faults and defects also poses significant problems for diagnosis. This presentation describes a preliminary investigation into the use of mandatory conditions for the detection of both faults and defects with applications to defect diagnosis. It will show that multiple site observations and good excitation balance are essential not only for adequate fortuitous defect detection-they are also necessary for the determination of the mandatory conditions and implications that accompany those detections, and thus enable the diagnosis of these fortuitously detected and unmodeled defects as well","PeriodicalId":179953,"journal":{"name":"2005 Sixth International Workshop on Microprocessor Test and Verification","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133902859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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