Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362427
A. Mukherjee, Rajsaktish Sankaranarayan
Today's densely packed deep sub micron (DSM) circuits operate at high frequencies, and draw large amounts of instantaneous currents. The simultaneous switching noise thus induced in the power and ground networks, reduces the circuit noise margins. This work presents a method to minimize the maximum simultaneous switching currents in sequential circuits by the seamless integration of the well known techniques of retiming and clock scheduling. We adopt a gradual relaxation based approach to find an efficient solution to our formulation. Experiments with MCNC benchmark circuits in the 0.18 micron technology show that, on average, our method reduces the maximum simultaneous switching current by 18% compared to unoptimized circuits designed using commercial tools. This improvement was obtained with no decrease in operating frequencies. With a reduction of 17% in power dissipation, on average, our method seems encouraging.
{"title":"Retiming and clock scheduling to minimize simultaneous switching","authors":"A. Mukherjee, Rajsaktish Sankaranarayan","doi":"10.1109/SOCC.2004.1362427","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362427","url":null,"abstract":"Today's densely packed deep sub micron (DSM) circuits operate at high frequencies, and draw large amounts of instantaneous currents. The simultaneous switching noise thus induced in the power and ground networks, reduces the circuit noise margins. This work presents a method to minimize the maximum simultaneous switching currents in sequential circuits by the seamless integration of the well known techniques of retiming and clock scheduling. We adopt a gradual relaxation based approach to find an efficient solution to our formulation. Experiments with MCNC benchmark circuits in the 0.18 micron technology show that, on average, our method reduces the maximum simultaneous switching current by 18% compared to unoptimized circuits designed using commercial tools. This improvement was obtained with no decrease in operating frequencies. With a reduction of 17% in power dissipation, on average, our method seems encouraging.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125989450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362443
G. Blakiewicz, M. Jeske, M. Chrzanowska-Jeske
We propose a new approach to substrate noise reduction in early design planning of mixed-signal system-on-chip (MS-SOC). As typical in floorplanning, we assume that no detailed layout information is known for analog and digital blocks. Based on the physics of substrate noise phenomena and extensive noise simulations we propose to represent noise coupling as coupling between large-area (digital) and small-area (analog) substrate noise ports. A separation-dependent noise model for a lightly-doped substrate (preferable for mixed-signal designs) is derived. Our floorplanner reduces the overall noise and the number of analog blocks exceeding their noise limit. Experimental results on examples created from MCNC floorplanning benchmarks are very encouraging.
{"title":"Substrate noise optimization in early floorplanning for mixed signal SOCs","authors":"G. Blakiewicz, M. Jeske, M. Chrzanowska-Jeske","doi":"10.1109/SOCC.2004.1362443","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362443","url":null,"abstract":"We propose a new approach to substrate noise reduction in early design planning of mixed-signal system-on-chip (MS-SOC). As typical in floorplanning, we assume that no detailed layout information is known for analog and digital blocks. Based on the physics of substrate noise phenomena and extensive noise simulations we propose to represent noise coupling as coupling between large-area (digital) and small-area (analog) substrate noise ports. A separation-dependent noise model for a lightly-doped substrate (preferable for mixed-signal designs) is derived. Our floorplanner reduces the overall noise and the number of analog blocks exceeding their noise limit. Experimental results on examples created from MCNC floorplanning benchmarks are very encouraging.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129397881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362338
Hassan Hassan, M. Anis, M. Elmasry
Multi-threshold MOS current mode logic (MTMCML) is a natural evolution for MCML that offers power saving through supply voltage reduction while retaining the same performance. In this work, analytical formulation based on the BSIM3v3 model is proposed for MTMCML with error within 10% compared to HSPICE. The formulation helps designers to efficiently design MTMCML circuits without undergoing the time-consuming HSPICE simulations. Furthermore, it provides design guidelines and aids for designers to fully understand the different tradeoffs in MTMCML design. In addition, the analysis is extended to study the impact of technology scaling and parameter variations on MTMCML. It is shown that the worst case variation in the minimum supply voltage of MTMCML is 1.16%, thus suggesting maximal power saving.
{"title":"Analysis and design of low-power multi-threshold MCML","authors":"Hassan Hassan, M. Anis, M. Elmasry","doi":"10.1109/SOCC.2004.1362338","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362338","url":null,"abstract":"Multi-threshold MOS current mode logic (MTMCML) is a natural evolution for MCML that offers power saving through supply voltage reduction while retaining the same performance. In this work, analytical formulation based on the BSIM3v3 model is proposed for MTMCML with error within 10% compared to HSPICE. The formulation helps designers to efficiently design MTMCML circuits without undergoing the time-consuming HSPICE simulations. Furthermore, it provides design guidelines and aids for designers to fully understand the different tradeoffs in MTMCML design. In addition, the analysis is extended to study the impact of technology scaling and parameter variations on MTMCML. It is shown that the worst case variation in the minimum supply voltage of MTMCML is 1.16%, thus suggesting maximal power saving.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116276649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362467
Xiaofeng Wu, V. Chouliaras, R. Goodall
This paper presents an application-specific processor architecture for real-time control applications. The processor is specially designed for 1-bit processing, which is a new technique in real-time control. The targeted processor is low-power, small and fast, and has been implemented as a hard macro in a high-performance silicon process.
{"title":"An application-specific processor hard macro for real-time control","authors":"Xiaofeng Wu, V. Chouliaras, R. Goodall","doi":"10.1109/SOCC.2004.1362467","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362467","url":null,"abstract":"This paper presents an application-specific processor architecture for real-time control applications. The processor is specially designed for 1-bit processing, which is a new technique in real-time control. The targeted processor is low-power, small and fast, and has been implemented as a hard macro in a high-performance silicon process.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"11 19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123696713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362395
Zemo Yang, S. Mourad
In this paper we focus on the analysis of crosstalk among the bit-lines during the read operation, especially when defect and parameter variations exist. We identify such faults as crosstalk reading (CTR) faults. An analytical study of these faults was done and we supported the study with extensive simulation results.
{"title":"Crosstalk induced fault analysis in DRAMs","authors":"Zemo Yang, S. Mourad","doi":"10.1109/SOCC.2004.1362395","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362395","url":null,"abstract":"In this paper we focus on the analysis of crosstalk among the bit-lines during the read operation, especially when defect and parameter variations exist. We identify such faults as crosstalk reading (CTR) faults. An analytical study of these faults was done and we supported the study with extensive simulation results.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126136671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362383
Yu-Hsiung Huang, Mely Chen Chi
This proposed algorithm includes coarsening, placement, and cell exchange phases. The objective is to generate a placement with low switching power. The positions of standard cells may be exchanged to balance power distribution. This program has been integrated into a commercial design flow. Experimental results are shown.
{"title":"Low-power driven standard-cell placement based on a multilevel force-directed algorithm","authors":"Yu-Hsiung Huang, Mely Chen Chi","doi":"10.1109/SOCC.2004.1362383","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362383","url":null,"abstract":"This proposed algorithm includes coarsening, placement, and cell exchange phases. The objective is to generate a placement with low switching power. The positions of standard cells may be exchanged to balance power distribution. This program has been integrated into a commercial design flow. Experimental results are shown.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"320 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124531942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362419
M. Ghoneima, Y. Ismail
This paper proposes a dynamic delayed line bus scheme (DDL) for low-power on-chip buses. This scheme dynamically introduces a delay to bus lines having a certain switching activity to create relative delay between opposite switching adjacent lines. The optimum relative delay introduced by this proposed scheme is shown to reduce the power dissipation by up to 16%.
{"title":"Low-power on-chip bus architecture using dynamic relative delays","authors":"M. Ghoneima, Y. Ismail","doi":"10.1109/SOCC.2004.1362419","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362419","url":null,"abstract":"This paper proposes a dynamic delayed line bus scheme (DDL) for low-power on-chip buses. This scheme dynamically introduces a delay to bus lines having a certain switching activity to create relative delay between opposite switching adjacent lines. The optimum relative delay introduced by this proposed scheme is shown to reduce the power dissipation by up to 16%.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128843834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362455
Guoqing Chen, E. Friedman
A repeater insertion methodology is presented for achieving the minimum power in an RC interconnect while satisfying delay and bandwidth constraints. With delay constraints, closed form solutions for the minimum power are developed which are within 10% of SPICE. With bandwidth constraints, the minimum power can be achieved with minimum sized repeaters.
{"title":"Low power repeaters driving RC interconnects with delay and bandwidth constraints","authors":"Guoqing Chen, E. Friedman","doi":"10.1109/SOCC.2004.1362455","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362455","url":null,"abstract":"A repeater insertion methodology is presented for achieving the minimum power in an RC interconnect while satisfying delay and bandwidth constraints. With delay constraints, closed form solutions for the minimum power are developed which are within 10% of SPICE. With bandwidth constraints, the minimum power can be achieved with minimum sized repeaters.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121126600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362402
G. Boudon, A. Wall, Joe Foster, Barry Wolford, John Fakiris
A PowerPC system-on-a-chip processor which integrates high speed state of the art 800 MHz PowerPC, DDRII-667 memory controller, RAID assist logic, and three PCI-X DDR266 interfaces with a rich mix of conventional peripherals is described. The PowerPC, with on-chip L2 cache enabled, executes up to 1600 DMIPS. The RAID assist logic is capable of transferring 2 Gbytes/sec. The state of the art PowerPC, the high bandwidth data pipes, and the RAID assist logic make the SOC an ideal solution for RAID controller applications. Active power consumption is as low as 6W with a 1.5 volt supply. The SOC has been implemented in a 0.13 /spl mu/m, 1.5 V nominal-supply, bulk CMOS process.
{"title":"A 800 MHz PowerPC SOC with PCI-X DDR266, DDRII-667, and RAID assist","authors":"G. Boudon, A. Wall, Joe Foster, Barry Wolford, John Fakiris","doi":"10.1109/SOCC.2004.1362402","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362402","url":null,"abstract":"A PowerPC system-on-a-chip processor which integrates high speed state of the art 800 MHz PowerPC, DDRII-667 memory controller, RAID assist logic, and three PCI-X DDR266 interfaces with a rich mix of conventional peripherals is described. The PowerPC, with on-chip L2 cache enabled, executes up to 1600 DMIPS. The RAID assist logic is capable of transferring 2 Gbytes/sec. The state of the art PowerPC, the high bandwidth data pipes, and the RAID assist logic make the SOC an ideal solution for RAID controller applications. Active power consumption is as low as 6W with a 1.5 volt supply. The SOC has been implemented in a 0.13 /spl mu/m, 1.5 V nominal-supply, bulk CMOS process.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126492101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362431
Colm McKillen, S. Sezer
This paper investigates a customized implementation for Xilinx Virtex Pro board of a weighted fair queuing (WFQ) tag scheduler that has the capacity to serve 8,000 individual sessions at over 100MHz. The implementation is actually capable of handling up to 64,000 different sessions requiring only the use of a minimal size FPGA. This represents an excellent hardware cost for a next generation terabit router.
{"title":"A weighted fair queuing finishing tag computation architecture and implementation","authors":"Colm McKillen, S. Sezer","doi":"10.1109/SOCC.2004.1362431","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362431","url":null,"abstract":"This paper investigates a customized implementation for Xilinx Virtex Pro board of a weighted fair queuing (WFQ) tag scheduler that has the capacity to serve 8,000 individual sessions at over 100MHz. The implementation is actually capable of handling up to 64,000 different sessions requiring only the use of a minimal size FPGA. This represents an excellent hardware cost for a next generation terabit router.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133715828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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