Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362450
J. Ryu, Bruce C. Kim
This paper presents a new low-cost built-in self-test (BIST) circuit for 5GHz low noise amplifier (LNA). The BIST circuit is designed for system-on-chip (SOC) transceiver environment. The proposed BIST circuit measures the LNA specifications such as input impedance, voltage gain, noise figure, and input return loss all in a single SoC environment.
{"title":"A new design for built-in self-test of 5GHz low noise amplifiers","authors":"J. Ryu, Bruce C. Kim","doi":"10.1109/SOCC.2004.1362450","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362450","url":null,"abstract":"This paper presents a new low-cost built-in self-test (BIST) circuit for 5GHz low noise amplifier (LNA). The BIST circuit is designed for system-on-chip (SOC) transceiver environment. The proposed BIST circuit measures the LNA specifications such as input impedance, voltage gain, noise figure, and input return loss all in a single SoC environment.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128692466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362463
Xiaomin Chen, S. Kiaei
The delay-hopped transmitted-reference (DHTR) ultra wideband (UWB) architecture was proposed by Hoctor and Tomlinson as a candidate for impulse UWB systems working in multipath fading channels. Compared to the RAKE transceiver, the DHTR transceiver does not require channel estimation, and the correlation can be performed in the analog domain. Since the analog-to-digital converters (ADCs) are now placed after the correlators, high sampling-rate, high-power ADCs are no longer required. As a result, the DHTR architecture is suitable for low-power, low-data-rate impulse UWB applications, such as RF tagging and sensoring. However, the proposed DHTR architecture will produce discrete spectral spikes in the transmitted signal, which are undesirable because the emissions of the UWB devices are limited by the FCC's regulations. This paper presents a solution to this issue while adding little to the transceiver complexity.
{"title":"An improved delay-hopped transmitted-reference ultra wideband architecture","authors":"Xiaomin Chen, S. Kiaei","doi":"10.1109/SOCC.2004.1362463","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362463","url":null,"abstract":"The delay-hopped transmitted-reference (DHTR) ultra wideband (UWB) architecture was proposed by Hoctor and Tomlinson as a candidate for impulse UWB systems working in multipath fading channels. Compared to the RAKE transceiver, the DHTR transceiver does not require channel estimation, and the correlation can be performed in the analog domain. Since the analog-to-digital converters (ADCs) are now placed after the correlators, high sampling-rate, high-power ADCs are no longer required. As a result, the DHTR architecture is suitable for low-power, low-data-rate impulse UWB applications, such as RF tagging and sensoring. However, the proposed DHTR architecture will produce discrete spectral spikes in the transmitted signal, which are undesirable because the emissions of the UWB devices are limited by the FCC's regulations. This paper presents a solution to this issue while adding little to the transceiver complexity.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128397342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362386
K. Lim, Z. Zilic
This paper presents a new method for multilevel clock recovery for high speed serial links. This all-digital implementation requires little overhead and no special encoding of data streams is required. A high speed 2-bit ADC is designed and presented for clock recovery purpose.
{"title":"A novel phase detector for PAM-4 clock recovery in high speed serial links","authors":"K. Lim, Z. Zilic","doi":"10.1109/SOCC.2004.1362386","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362386","url":null,"abstract":"This paper presents a new method for multilevel clock recovery for high speed serial links. This all-digital implementation requires little overhead and no special encoding of data streams is required. A high speed 2-bit ADC is designed and presented for clock recovery purpose.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126273408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362436
Minoru Watanabe, F. Kobayashi
This paper presents the design of a high-density optically differential reconfigurable gate array (ODRGA) using a 0.18/spl mu/m-5 metal CMOS process technology. ODRGA is a type of field programmable gate arrays (FPGAs). However, unlike conventional FPGAs, ODRGAs are reconfigured optically using an external optical system. Although ODRGAs have already been fabricated using a 0.35/spl mu/m-3 metal CMOS process technology, their gate-density remains unsatisfactory. For that reason, a new ODRGA-VLSI chip with four logic blocks, five switching matrices, and 16 I/O bits was fabricated on a 7.82mm/sup 2/ chip using more advanced process technology. This paper presents the detailed design of a fabricated ODRGA-VLSI chip, the optical reconfiguration circuit, the gate array structure, the CAD layout, and an ODRGA-VLSI chip mounted on an estimation board. This study also includes experimental results regarding the reconfiguration period.
{"title":"An optically differential reconfigurable gate array using a 0.18 /spl mu/m CMOS process","authors":"Minoru Watanabe, F. Kobayashi","doi":"10.1109/SOCC.2004.1362436","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362436","url":null,"abstract":"This paper presents the design of a high-density optically differential reconfigurable gate array (ODRGA) using a 0.18/spl mu/m-5 metal CMOS process technology. ODRGA is a type of field programmable gate arrays (FPGAs). However, unlike conventional FPGAs, ODRGAs are reconfigured optically using an external optical system. Although ODRGAs have already been fabricated using a 0.35/spl mu/m-3 metal CMOS process technology, their gate-density remains unsatisfactory. For that reason, a new ODRGA-VLSI chip with four logic blocks, five switching matrices, and 16 I/O bits was fabricated on a 7.82mm/sup 2/ chip using more advanced process technology. This paper presents the detailed design of a fabricated ODRGA-VLSI chip, the optical reconfiguration circuit, the gate array structure, the CAD layout, and an ODRGA-VLSI chip mounted on an estimation board. This study also includes experimental results regarding the reconfiguration period.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117169922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362444
Sanghun Lee, Chanho Lee, Hyuk-Jae Lee
We can integrate more IP blocks on the same silicon die as the development of fabrication technologies and EDA tools. Consequently, we can design complicated SoC architecture including multi-processor. However, most of existing SoC buses have bottleneck in on-chip communication because of a shared bus architecture, which results in the performance degradation of the system. In most cases, the performance of multi-processor systems is determined by efficient on-chip communication and the well-balanced distribution of computation rather than the performance of processors. We propose an efficient SoC network architecture (SNA) using crossbar router which provides a solution to ensure enough communication bandwidth. The SNA can significantly reduce the bottleneck of on-chip communication by providing multi-channels. According to the proposed architecture, we design components for the SNA and build a model system. The proposed architecture has a better efficiency by 40% than the AMBA AHB according to a simulation result.
{"title":"A new multi-channel on-chip-bus architecture for system-on-chips","authors":"Sanghun Lee, Chanho Lee, Hyuk-Jae Lee","doi":"10.1109/SOCC.2004.1362444","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362444","url":null,"abstract":"We can integrate more IP blocks on the same silicon die as the development of fabrication technologies and EDA tools. Consequently, we can design complicated SoC architecture including multi-processor. However, most of existing SoC buses have bottleneck in on-chip communication because of a shared bus architecture, which results in the performance degradation of the system. In most cases, the performance of multi-processor systems is determined by efficient on-chip communication and the well-balanced distribution of computation rather than the performance of processors. We propose an efficient SoC network architecture (SNA) using crossbar router which provides a solution to ensure enough communication bandwidth. The SNA can significantly reduce the bottleneck of on-chip communication by providing multi-channels. According to the proposed architecture, we design components for the SNA and build a model system. The proposed architecture has a better efficiency by 40% than the AMBA AHB according to a simulation result.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131305046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362368
Donghoon Han, A. Chatterjee
In this paper we propose a simulation-based analog circuit sizing method which is capable of significantly reducing the computational cost via adaptive response surface modeling. The proposed algorithm is based on the selective evaluation of a response surface model coupled with numerical circuit simulation and the adaptive update of the model for accuracy. An effective sampling scheme for modeling using two related criteria that are crucial for speedup and convergence towards an optimal solution is presented. One provides sufficient samples for model accuracy and convergence, whereas the other prevents oversampling of the design space after the model is saturated. Multivariate adaptive regression splines (MARS) are used to construct a model of the selected cost function. Results for several test functions and two test cases are discussed.
{"title":"Adaptive response surface modeling-based method for analog circuit sizing","authors":"Donghoon Han, A. Chatterjee","doi":"10.1109/SOCC.2004.1362368","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362368","url":null,"abstract":"In this paper we propose a simulation-based analog circuit sizing method which is capable of significantly reducing the computational cost via adaptive response surface modeling. The proposed algorithm is based on the selective evaluation of a response surface model coupled with numerical circuit simulation and the adaptive update of the model for accuracy. An effective sampling scheme for modeling using two related criteria that are crucial for speedup and convergence towards an optimal solution is presented. One provides sufficient samples for model accuracy and convergence, whereas the other prevents oversampling of the design space after the model is saturated. Multivariate adaptive regression splines (MARS) are used to construct a model of the selected cost function. Results for several test functions and two test cases are discussed.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127814670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362330
A. Kamalizad, Richard Plettner, Chengzhi Pan, N. Bagherzadeh
The Viterbi algorithm is used to decode convolutional codes (CC). Viterbi decoding is a computation/communication intensive algorithm. Recently, with the emerging of WLAN standards delivering high rates, performance requirements of Viterbi decoders have increased dramatically. So far, such decoders have only been implemented using fixed ASIC with the datapath designed specially for the Viterbi algorithm, sacrificing flexibility. In this paper, we introduce a reconfigurable DSP platform targeting wireless communication algorithms in general with specific accelerators for the Viterbi algorithm.
{"title":"Fast parallel soft Viterbi decoder mapping on a reconfigurable DSP platform","authors":"A. Kamalizad, Richard Plettner, Chengzhi Pan, N. Bagherzadeh","doi":"10.1109/SOCC.2004.1362330","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362330","url":null,"abstract":"The Viterbi algorithm is used to decode convolutional codes (CC). Viterbi decoding is a computation/communication intensive algorithm. Recently, with the emerging of WLAN standards delivering high rates, performance requirements of Viterbi decoders have increased dramatically. So far, such decoders have only been implemented using fixed ASIC with the datapath designed specially for the Viterbi algorithm, sacrificing flexibility. In this paper, we introduce a reconfigurable DSP platform targeting wireless communication algorithms in general with specific accelerators for the Viterbi algorithm.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129481794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362334
S. Mir, B. Charlot, L. Rufer, B. Courtois
System-on-chip (SoC) technologies are evolving towards the integration of highly heterogeneous devices, including hardware of a different nature, such as digital, analog and mixed-signal, together with software components. Embedding transducers, as predicted by technology roadmaps, is yet another step in this continuous search for higher levels of integration and miniaturisation. Embedded transducers fabricated with silicon/CMOS compatible technologies may have more limitations than transducers fabricated with fully dedicated technologies. However, they offer industry the possibility of providing low cost applications for very large market niches, while still keeping acceptable transducer sensitivity. This is the case, for example, for accelerometers, micromirrors display devices or CMOS imagers. Embedded transducers are analog components. But given the fact that they work with signals other than electrical, the test of these embedded parts poses new challenges. Test technology for SoC devices is rapidly maturing but many difficulties still remain, in particular for addressing the test of analog and mixed-signal parts. In this paper, we present our work in the field of MEMS (microelectromechanical systems) on-chip testing with a brief overview of the state-of-the-art.
{"title":"On-chip testing of embedded silicon transducers","authors":"S. Mir, B. Charlot, L. Rufer, B. Courtois","doi":"10.1109/SOCC.2004.1362334","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362334","url":null,"abstract":"System-on-chip (SoC) technologies are evolving towards the integration of highly heterogeneous devices, including hardware of a different nature, such as digital, analog and mixed-signal, together with software components. Embedding transducers, as predicted by technology roadmaps, is yet another step in this continuous search for higher levels of integration and miniaturisation. Embedded transducers fabricated with silicon/CMOS compatible technologies may have more limitations than transducers fabricated with fully dedicated technologies. However, they offer industry the possibility of providing low cost applications for very large market niches, while still keeping acceptable transducer sensitivity. This is the case, for example, for accelerometers, micromirrors display devices or CMOS imagers. Embedded transducers are analog components. But given the fact that they work with signals other than electrical, the test of these embedded parts poses new challenges. Test technology for SoC devices is rapidly maturing but many difficulties still remain, in particular for addressing the test of analog and mixed-signal parts. In this paper, we present our work in the field of MEMS (microelectromechanical systems) on-chip testing with a brief overview of the state-of-the-art.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127955795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362456
Yuantao Peng, Xun Liu
This paper investigates the problem of global interconnect optimization for intellectual property (IP) based system-on-chip designs. In contrast to previous research, which conducts repeater insertion for global interconnects after the system placement, our approach performs these two steps simultaneously by integrating an interconnect macromodel into the placement procedure. Our macro-model is able to estimate the power dissipation of global interconnects with optimal repeater insertion using the wire length, timing budget, repeater location deviation, and signal activity. Consequently, accurate power dissipation of global interconnects can be used to guide the placement procedure, resulting in high-quality designs. Experimental results have shown that our approach reduces the number of timing-violation paths by more than 80% and achieves up to 11.1% power reduction in comparison with placement schemes based on area or wirelength minimization.
{"title":"Global interconnect optimization with simultaneous macrocell placement and repeater insertion","authors":"Yuantao Peng, Xun Liu","doi":"10.1109/SOCC.2004.1362456","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362456","url":null,"abstract":"This paper investigates the problem of global interconnect optimization for intellectual property (IP) based system-on-chip designs. In contrast to previous research, which conducts repeater insertion for global interconnects after the system placement, our approach performs these two steps simultaneously by integrating an interconnect macromodel into the placement procedure. Our macro-model is able to estimate the power dissipation of global interconnects with optimal repeater insertion using the wire length, timing budget, repeater location deviation, and signal activity. Consequently, accurate power dissipation of global interconnects can be used to guide the placement procedure, resulting in high-quality designs. Experimental results have shown that our approach reduces the number of timing-violation paths by more than 80% and achieves up to 11.1% power reduction in comparison with placement schemes based on area or wirelength minimization.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126189272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362393
K. Folkesson, C. Svensson
A very flexible multiphase clock generation circuit is proposed. It is aimed for applications where very accurate phase shifts and low jitter is required, such as time-interleaved samplers and multistandard radio receivers. Robustness to supply voltage variation for phase shifts and jitter performance is demonstrated with simulations as well as measurements.
{"title":"Robust multi-phase clock generation with reduced jitter","authors":"K. Folkesson, C. Svensson","doi":"10.1109/SOCC.2004.1362393","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362393","url":null,"abstract":"A very flexible multiphase clock generation circuit is proposed. It is aimed for applications where very accurate phase shifts and low jitter is required, such as time-interleaved samplers and multistandard radio receivers. Robustness to supply voltage variation for phase shifts and jitter performance is demonstrated with simulations as well as measurements.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"211 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116175781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：