Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362390
C. Toal, S. Sezer
This paper presents the design and study of circuit architectures for gigabit GFP frame delineation and explores the trade-offs between the data-path (parallelism) and the corresponding hardware cost. The study targets the development of a SoC platform for the design of next generation network processing. Circuits with an 8-bit, 16-bit, 32-bit and a 64-bit data-path have been implemented and analysed in terms of, scalability, hardware cost, speed, and data throughput capabilities. The circuit analysis is based on performance results with the UMC 0.18 /spl mu/m standard cell libraries obtained using Synopsys physical compiler. Analysis shows that the 64-bit datapath architecture is able to achieve data rates beyond l0Gbps whereas the 8-bit data-path architecture is very compact and operates with a clock rate of close to 300MHz. Considering the throughput-rate versus silicon area cost as a measure of silicon area efficiency, then the 16-bit data-path architecture proves to be the most efficient.
{"title":"Exploration of GFP frame delineation architectures for network processing","authors":"C. Toal, S. Sezer","doi":"10.1109/SOCC.2004.1362390","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362390","url":null,"abstract":"This paper presents the design and study of circuit architectures for gigabit GFP frame delineation and explores the trade-offs between the data-path (parallelism) and the corresponding hardware cost. The study targets the development of a SoC platform for the design of next generation network processing. Circuits with an 8-bit, 16-bit, 32-bit and a 64-bit data-path have been implemented and analysed in terms of, scalability, hardware cost, speed, and data throughput capabilities. The circuit analysis is based on performance results with the UMC 0.18 /spl mu/m standard cell libraries obtained using Synopsys physical compiler. Analysis shows that the 64-bit datapath architecture is able to achieve data rates beyond l0Gbps whereas the 8-bit data-path architecture is very compact and operates with a clock rate of close to 300MHz. Considering the throughput-rate versus silicon area cost as a measure of silicon area efficiency, then the 16-bit data-path architecture proves to be the most efficient.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"40 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134004762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362421
A. Agarwal, K. Roy, R. Krishnamurthy
This paper describes a 256/spl times/64b 3-read, 3-write ported leakage tolerant low leakage register file. The local bitline shares a sleep transistor for aggressive bitline leakage reduction/tolerance to enable high fanin bitlines and uses low V/sub th/ transistors. The sleep transistor is turned on while accessing the local bitline and conditionally turned off, if the dynamic node should remain high. Simulation results shows that proposed technique achieves 9% improvement in performance with 14/spl times/ reduction in local bitline leakage (97/spl times/ reduction as compared to any previously proposed low V/sub th/, leakage tolerant register file) enabling 70% reduction in keeper size, while keeping the same noise robustness as optimized high performance conventional high V/sub th/ implementation.
{"title":"A leakage-tolerant low-leakage register file with conditional sleep transistor","authors":"A. Agarwal, K. Roy, R. Krishnamurthy","doi":"10.1109/SOCC.2004.1362421","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362421","url":null,"abstract":"This paper describes a 256/spl times/64b 3-read, 3-write ported leakage tolerant low leakage register file. The local bitline shares a sleep transistor for aggressive bitline leakage reduction/tolerance to enable high fanin bitlines and uses low V/sub th/ transistors. The sleep transistor is turned on while accessing the local bitline and conditionally turned off, if the dynamic node should remain high. Simulation results shows that proposed technique achieves 9% improvement in performance with 14/spl times/ reduction in local bitline leakage (97/spl times/ reduction as compared to any previously proposed low V/sub th/, leakage tolerant register file) enabling 70% reduction in keeper size, while keeping the same noise robustness as optimized high performance conventional high V/sub th/ implementation.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122846903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362426
M. Hsieh, G. Sobelman
This paper presents a new design of a simultaneous bidirectional PAM-4 wired transmission system that uses built-in self-test (BIST) to adjust the level of pre-emphasis that is applied. The BIST circuitry consists of a pattern generator and detector, a signal comparator and a high-pass filter. It outputs an error indicator that is used as a control signal in the adaptive pre-emphasis block. The feedback loop inherent in a simultaneous bidirectional link provides a natural opportunity to carry information about the channel characteristics without the need for an extra dedicated wire. The design has been verified using the Cadence SpectreRF and Verilog-A simulators and the channel loss characteristics are based on an FR-4 material model extracted from the Cadence Transmission Line Model Generator.
{"title":"Simultaneous bidirectional PAM-4 link with built-in self-test","authors":"M. Hsieh, G. Sobelman","doi":"10.1109/SOCC.2004.1362426","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362426","url":null,"abstract":"This paper presents a new design of a simultaneous bidirectional PAM-4 wired transmission system that uses built-in self-test (BIST) to adjust the level of pre-emphasis that is applied. The BIST circuitry consists of a pattern generator and detector, a signal comparator and a high-pass filter. It outputs an error indicator that is used as a control signal in the adaptive pre-emphasis block. The feedback loop inherent in a simultaneous bidirectional link provides a natural opportunity to carry information about the channel characteristics without the need for an extra dedicated wire. The design has been verified using the Cadence SpectreRF and Verilog-A simulators and the channel loss characteristics are based on an FR-4 material model extracted from the Cadence Transmission Line Model Generator.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127959062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362349
Jian Liu, Lirong Zheng, H. Tenhunen
This paper presents a circuit-switched network architecture for network-on-chip. It uses time-division-multiplexing (TDM) scheme to realize the circuits. The global routing (slot assignment) is done centrally, while the slot mapping is done locally by the switches. The switches support multicast operation, which enables multicast traffic. Furthermore, the delay in the network is predictable before a circuit is established and in-order data delivery is guaranteed.
{"title":"A circuit-switched network architecture for network-on-chip","authors":"Jian Liu, Lirong Zheng, H. Tenhunen","doi":"10.1109/SOCC.2004.1362349","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362349","url":null,"abstract":"This paper presents a circuit-switched network architecture for network-on-chip. It uses time-division-multiplexing (TDM) scheme to realize the circuits. The global routing (slot assignment) is done centrally, while the slot mapping is done locally by the switches. The switches support multicast operation, which enables multicast traffic. Furthermore, the delay in the network is predictable before a circuit is established and in-order data delivery is guaranteed.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128429674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362442
Marcus van Ierssel, Joyce Wong, A. Sheikholeslami
This paper presents a 4-PAM adaptive decision-feedback equalizer (DFE) for chip-to-chip signaling. The DFE adapts to the channel impulse response by observing a calibration sequence sent across the channel. Uninterrupted signaling is maintained across a parallel bus by providing an additional channel and using multiplexors to reroute the signals of the channel being calibrated. Using the intermittent calibration sequence instead of the conventional LMS adaptation technique removes the need to generate an error signal, eliminating the associated analog blocks. Also presented is a novel method of using the DFE adaptation circuits to extract the system's pulse response. The complete transceiver is implemented in a 0.18 /spl mu/m CMOS process.
{"title":"An adaptive 4-PAM decision-feedback equalizer for chip-to-chip signaling","authors":"Marcus van Ierssel, Joyce Wong, A. Sheikholeslami","doi":"10.1109/SOCC.2004.1362442","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362442","url":null,"abstract":"This paper presents a 4-PAM adaptive decision-feedback equalizer (DFE) for chip-to-chip signaling. The DFE adapts to the channel impulse response by observing a calibration sequence sent across the channel. Uninterrupted signaling is maintained across a parallel bus by providing an additional channel and using multiplexors to reroute the signals of the channel being calibrated. Using the intermittent calibration sequence instead of the conventional LMS adaptation technique removes the need to generate an error signal, eliminating the associated analog blocks. Also presented is a novel method of using the DFE adaptation circuits to extract the system's pulse response. The complete transceiver is implemented in a 0.18 /spl mu/m CMOS process.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127555649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362430
Xiaoning Nie, U. Nordqvist, L. Gazsi, Dake Liu
This paper outlines current research trends in the network processor area. It stresses the need for a special class of network processors, namely the network processor for access network (NP4AN) sometimes called access processor. It further describes main challenges and architectural choices involved when designing network processors dedicated for use in access network nodes such as DSLAMs (DSL Access Multiplexer). Among others the protocol processing engine, IOs and memory have been considered in more detail. This paper concludes that the main optimization goal for designing such class of network processors should be cost-efficiency.
{"title":"Network processors for access network (NP4AN): trends and challenges","authors":"Xiaoning Nie, U. Nordqvist, L. Gazsi, Dake Liu","doi":"10.1109/SOCC.2004.1362430","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362430","url":null,"abstract":"This paper outlines current research trends in the network processor area. It stresses the need for a special class of network processors, namely the network processor for access network (NP4AN) sometimes called access processor. It further describes main challenges and architectural choices involved when designing network processors dedicated for use in access network nodes such as DSLAMs (DSL Access Multiplexer). Among others the protocol processing engine, IOs and memory have been considered in more detail. This paper concludes that the main optimization goal for designing such class of network processors should be cost-efficiency.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123129493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362468
I. Janiszewski, H. Meuth, B. Hoppe
A hybrid architecture for digital phase-to-inphase/quadrature (I/Q) at constant-magnitude transformers is presented. The design may be efficiently implemented in FPGA. Starting from the well established co-ordinate rotation digital computer (CORDIC) algorithm, and from look-up table (LUT) schemes, optimum hybrid configurations are derived. Via fully synthesizable HDL models, portability and reusability are ensured. The hybrid LUT/CORDIC architecture allows design partitioning between logic and storage based FPGA resources and is suitable also for multi-phase implementations.
{"title":"FPGA-efficient phase-to-I/Q architecture","authors":"I. Janiszewski, H. Meuth, B. Hoppe","doi":"10.1109/SOCC.2004.1362468","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362468","url":null,"abstract":"A hybrid architecture for digital phase-to-inphase/quadrature (I/Q) at constant-magnitude transformers is presented. The design may be efficiently implemented in FPGA. Starting from the well established co-ordinate rotation digital computer (CORDIC) algorithm, and from look-up table (LUT) schemes, optimum hybrid configurations are derived. Via fully synthesizable HDL models, portability and reusability are ensured. The hybrid LUT/CORDIC architecture allows design partitioning between logic and storage based FPGA resources and is suitable also for multi-phase implementations.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129842037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362367
P. Birrer, T. Fiez, K. Mayaram
Silencer! is a new, fully automated, substrate noise coupling analysis tool that is integrated into the CADENCE DFII design environment. This tool seamlessly enables substrate noise coupling analysis in a standard mixed-signal design flow. IC designers can analyze substrate noise coupling at different levels of hierarchy - from the schematic level to the layout. Examples have been simulated and the results are accurate to within 10% of measured fabricated chips.
{"title":"Silencer!: a tool for substrate noise coupling analysis","authors":"P. Birrer, T. Fiez, K. Mayaram","doi":"10.1109/SOCC.2004.1362367","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362367","url":null,"abstract":"Silencer! is a new, fully automated, substrate noise coupling analysis tool that is integrated into the CADENCE DFII design environment. This tool seamlessly enables substrate noise coupling analysis in a standard mixed-signal design flow. IC designers can analyze substrate noise coupling at different levels of hierarchy - from the schematic level to the layout. Examples have been simulated and the results are accurate to within 10% of measured fabricated chips.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"411 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131661037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362369
B. Wan, P. Nikitin, C. Shi
The goal of this paper is to describe a methodology for circuit level modeling and simulation of mixed-technology systems, which fits into a standard electronic design flow and allows one to model and simulate such systems in a standard circuit simulator. The basis for the methodology is the use of the model compiler that allows one to compile models written in high-level behavioral description language and make them available to a standard circuit simulator. For demonstration purposes, we consider two mixed-technology examples: an optoelectronic example (a laser diode circuit) and a thermo-electronic example (thermally coupled MOS inverter). We use model compiler MCAST developed in our group to compile VHDL-AMS models and make them available to SPICE circuit simulator. Our results demonstrate that model compiler technology allows one to perform simulation of mixed-technology systems in a circuit simulator. The methodology described here is general and can be used with various model compilers and circuit simulators, as long as good mathematical models for mixed-technology devices are available.
{"title":"Circuit level modeling and simulation of mixed-technology systems","authors":"B. Wan, P. Nikitin, C. Shi","doi":"10.1109/SOCC.2004.1362369","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362369","url":null,"abstract":"The goal of this paper is to describe a methodology for circuit level modeling and simulation of mixed-technology systems, which fits into a standard electronic design flow and allows one to model and simulate such systems in a standard circuit simulator. The basis for the methodology is the use of the model compiler that allows one to compile models written in high-level behavioral description language and make them available to a standard circuit simulator. For demonstration purposes, we consider two mixed-technology examples: an optoelectronic example (a laser diode circuit) and a thermo-electronic example (thermally coupled MOS inverter). We use model compiler MCAST developed in our group to compile VHDL-AMS models and make them available to SPICE circuit simulator. Our results demonstrate that model compiler technology allows one to perform simulation of mixed-technology systems in a circuit simulator. The methodology described here is general and can be used with various model compilers and circuit simulators, as long as good mathematical models for mixed-technology devices are available.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130972605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362416
S. Krishnamohan, N. Mahapatra
Soft-errors are functional failures resulting from the latching of single-event transients (transient voltage fluctuations at a logic node or SETs) caused by electrical noise or high-energy particle strikes. Due to technology scaling and reduced supply voltages, they are expected to increase by several orders of magnitude in logic circuits in the near future. Existing circuit and architectural solutions are inadequate because they have appreciable area/cost, performance, and/or power overheads. We present a very efficient and systematic error-masking technique for static CMOS combinational circuits that prevents an SET pulse, with width, in the worst case, less than approximately half of the timing slack available in its propagation path, from latching and turning into a soft error. The SET is masked without additional delay and within the clock cycle time in an area-efficient manner, which makes this technique applicable to commodity as well as reliability-critical applications. Application of this technique to ISCAS85 benchmark circuits yields average soft-error rate reduction of 75.71% with average area overhead of only 18.14%.
{"title":"An efficient error-masking technique for improving the soft-error robustness of static CMOS circuits","authors":"S. Krishnamohan, N. Mahapatra","doi":"10.1109/SOCC.2004.1362416","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362416","url":null,"abstract":"Soft-errors are functional failures resulting from the latching of single-event transients (transient voltage fluctuations at a logic node or SETs) caused by electrical noise or high-energy particle strikes. Due to technology scaling and reduced supply voltages, they are expected to increase by several orders of magnitude in logic circuits in the near future. Existing circuit and architectural solutions are inadequate because they have appreciable area/cost, performance, and/or power overheads. We present a very efficient and systematic error-masking technique for static CMOS combinational circuits that prevents an SET pulse, with width, in the worst case, less than approximately half of the timing slack available in its propagation path, from latching and turning into a soft error. The SET is masked without additional delay and within the clock cycle time in an area-efficient manner, which makes this technique applicable to commodity as well as reliability-critical applications. Application of this technique to ISCAS85 benchmark circuits yields average soft-error rate reduction of 75.71% with average area overhead of only 18.14%.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133564867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：