Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362337
Wenxin Wang, M. Anis, S. Areibi
Technology scaling causes subthreshold leakage currents to increase exponentially. Therefore, effective leakage minimization techniques must be designed. In addition, for a true low-power solution in system-on-chip (SoC) design, it has to be tightly integrated into the main design environment. This paper presents two design techniques to effectively solve the sleep transistor sizing and distribution problem in MTCMOS circuits. The introduced first-fit and set-covering approaches achieve lower leakage at an order of magnitude reduction in CPU time compared with other techniques in the literature. In addition, an automatic MTCMOS design environment is developed and integrated into the Canadian Microelectronics Corporation (CMC) digital ASIC design flow.
{"title":"Fast techniques for standby leakage reduction in MTCMOS circuits","authors":"Wenxin Wang, M. Anis, S. Areibi","doi":"10.1109/SOCC.2004.1362337","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362337","url":null,"abstract":"Technology scaling causes subthreshold leakage currents to increase exponentially. Therefore, effective leakage minimization techniques must be designed. In addition, for a true low-power solution in system-on-chip (SoC) design, it has to be tightly integrated into the main design environment. This paper presents two design techniques to effectively solve the sleep transistor sizing and distribution problem in MTCMOS circuits. The introduced first-fit and set-covering approaches achieve lower leakage at an order of magnitude reduction in CPU time compared with other techniques in the literature. In addition, an automatic MTCMOS design environment is developed and integrated into the Canadian Microelectronics Corporation (CMC) digital ASIC design flow.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124898071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362362
Xiaohua Fan, E. Sánchez-Sinencio
This paper presents a 5-stage CMOS distributed single-balanced mixer (DMIXER). The on-chip transmission lines are used to connect the RF and LO parts of the mixer. The distributed mixer is designed in standard 0.18/spl mu/m CMOS technology. It achieves 3.8dB average conversion gain from 3GHz to 22GHz, operates from 1.2V power supply, dissipates 129.36mW, among which 36mW is consumed by distributed active balun, and occupies 3.02 mm/sup 2/ silicon areas.
{"title":"3-22GHz CMOS distributed single-balanced mixer","authors":"Xiaohua Fan, E. Sánchez-Sinencio","doi":"10.1109/SOCC.2004.1362362","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362362","url":null,"abstract":"This paper presents a 5-stage CMOS distributed single-balanced mixer (DMIXER). The on-chip transmission lines are used to connect the RF and LO parts of the mixer. The distributed mixer is designed in standard 0.18/spl mu/m CMOS technology. It achieves 3.8dB average conversion gain from 3GHz to 22GHz, operates from 1.2V power supply, dissipates 129.36mW, among which 36mW is consumed by distributed active balun, and occupies 3.02 mm/sup 2/ silicon areas.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128968598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362363
Hassan Hassan, M. Anis, M. Elmasry
Inspired by the huge improvement in the RF properties of CMOS, RF designers are invading the wireless market with all-CMOS RF transceivers and system-on-chip implementations. In this work, the impact of technology scaling on the RF properties of the CMOS; frequency properties, noise performance, linearity, stability, and non-quasi static effects, is investigated to provide RF designers with an insight to the capabilities of future CMOS technologies. Using the BSIM4 model it is found that future CMOS technologies have high prospects in the RF industry.
{"title":"Impact of technology scaling on RF CMOS","authors":"Hassan Hassan, M. Anis, M. Elmasry","doi":"10.1109/SOCC.2004.1362363","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362363","url":null,"abstract":"Inspired by the huge improvement in the RF properties of CMOS, RF designers are invading the wireless market with all-CMOS RF transceivers and system-on-chip implementations. In this work, the impact of technology scaling on the RF properties of the CMOS; frequency properties, noise performance, linearity, stability, and non-quasi static effects, is investigated to provide RF designers with an insight to the capabilities of future CMOS technologies. Using the BSIM4 model it is found that future CMOS technologies have high prospects in the RF industry.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129861493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362380
C. Charayaphan, F. Sattar
Blind source separation (BSS) of independent sources from their convolutive mixtures is a common problem in many real world multi-sensor applications. We present a low-cost real-time FPGA (field programmable gate array) implementation of an improved BSS algorithm for audio signals based on ICA (independent component analysis) technique. The separation is performed by implementing noncausal filters instead of causal filters within the feedback network. This reduces the required length of the unmixing filters as well as provides better separation and faster convergence. The result of testing the designed FPGA in real-time is reported.
{"title":"System-level design of low-cost FPGA hardware for real-time ICA-based blind source separation","authors":"C. Charayaphan, F. Sattar","doi":"10.1109/SOCC.2004.1362380","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362380","url":null,"abstract":"Blind source separation (BSS) of independent sources from their convolutive mixtures is a common problem in many real world multi-sensor applications. We present a low-cost real-time FPGA (field programmable gate array) implementation of an improved BSS algorithm for audio signals based on ICA (independent component analysis) technique. The separation is performed by implementing noncausal filters instead of causal filters within the feedback network. This reduces the required length of the unmixing filters as well as provides better separation and faster convergence. The result of testing the designed FPGA in real-time is reported.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"1099 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127901101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362345
S. Ren, R. Siferd, R. Blumgold
Many system on chip (SOC) architectures are pushing the analog to digital interface into the RF/IF region. A critical component for such architectures is a band pass analog to digital converter (BPADC). A parallel time interleaved (PTI) delta sigma BPADC is presented which supports RF/IF center frequencies for SOC applications. Three low pass delta sigma modulators sampling at 1 GHz are time interleaved to obtain a BPADC with center frequencies of 1 or 2 GHz in 0.18/spl mu/m CMOS technology. Resolution depends on bandwidth with 8 bits achievable for a 100 MHz bandwidth and 1 GHz sampling frequencies for the modulators. The BPADC center frequencies, resolution, and bandwidth can be modified by changing the sampling frequency of the modulators or the number of modulators that are time interleaved.
{"title":"Parallel time interleaved delta sigma band pass analog to digital converter for SOC applications","authors":"S. Ren, R. Siferd, R. Blumgold","doi":"10.1109/SOCC.2004.1362345","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362345","url":null,"abstract":"Many system on chip (SOC) architectures are pushing the analog to digital interface into the RF/IF region. A critical component for such architectures is a band pass analog to digital converter (BPADC). A parallel time interleaved (PTI) delta sigma BPADC is presented which supports RF/IF center frequencies for SOC applications. Three low pass delta sigma modulators sampling at 1 GHz are time interleaved to obtain a BPADC with center frequencies of 1 or 2 GHz in 0.18/spl mu/m CMOS technology. Resolution depends on bandwidth with 8 bits achievable for a 100 MHz bandwidth and 1 GHz sampling frequencies for the modulators. The BPADC center frequencies, resolution, and bandwidth can be modified by changing the sampling frequency of the modulators or the number of modulators that are time interleaved.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121073322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362424
Hassan Hassan, M. Anis, M. Elmasry
An automated optimization-based design strategy for 2-level MOS current mode logic (MCML) circuits is proposed to overcome the complexities of the design process. The methodology minimizes the power dissipation while satisfying the performance criteria. Moreover, environmental and process variations modeling are included in the design strategy. The impact of these variations on MCML performance as technology scales is also presented. In addition, design tips based on analytic formulation are presented for MCML designers. The proposed methodology is tested on several benchmarks belonging to optical communication and high-speed microprocessor applications built in a CMOS 0.18/spl mu/m process, at which the average error is within 7% between our formulation and HSPICE.
{"title":"MOS current mode logic: design, optimization, and variability","authors":"Hassan Hassan, M. Anis, M. Elmasry","doi":"10.1109/SOCC.2004.1362424","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362424","url":null,"abstract":"An automated optimization-based design strategy for 2-level MOS current mode logic (MCML) circuits is proposed to overcome the complexities of the design process. The methodology minimizes the power dissipation while satisfying the performance criteria. Moreover, environmental and process variations modeling are included in the design strategy. The impact of these variations on MCML performance as technology scales is also presented. In addition, design tips based on analytic formulation are presented for MCML designers. The proposed methodology is tested on several benchmarks belonging to optical communication and high-speed microprocessor applications built in a CMOS 0.18/spl mu/m process, at which the average error is within 7% between our formulation and HSPICE.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"292 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122303849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362477
Mrinmoy Ghosh, Wei-qi Shi, H. Lee
This paper describes CoolPression, a hybrid hardware-based significance compression technique for reducing energy in caches. The scheme exploits data compression opportunities at bit granularity by employing two compression schemes: a significance compression scheme that counts leading ones and zeros, and a dynamic zero compression technique. Based on actual data, the more energy-efficient scheme is selected dynamically to minimize bitline drives needed for each cache access. Using SPECint2000 benchmark, our experiments show that the CoolPression improves dynamic energy consumption by more than 35% against a baseline cache, while having a saving ranged from 5 to 15% compared to each scheme applied alone.
{"title":"CoolPression - a hybrid significance compression technique for reducing energy in caches","authors":"Mrinmoy Ghosh, Wei-qi Shi, H. Lee","doi":"10.1109/SOCC.2004.1362477","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362477","url":null,"abstract":"This paper describes CoolPression, a hybrid hardware-based significance compression technique for reducing energy in caches. The scheme exploits data compression opportunities at bit granularity by employing two compression schemes: a significance compression scheme that counts leading ones and zeros, and a dynamic zero compression technique. Based on actual data, the more energy-efficient scheme is selected dynamically to minimize bitline drives needed for each cache access. Using SPECint2000 benchmark, our experiments show that the CoolPression improves dynamic energy consumption by more than 35% against a baseline cache, while having a saving ranged from 5 to 15% compared to each scheme applied alone.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131318715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362425
M. Wieckowski, M. Margala
The proposed design demonstrates a new high-speed, low-power methodology in a 32 Kb SRAM cache. A fast cycle time of up to 3 GHz is accomplished by using pipelined asynchronous decoders along with a parallel local/global decoding scheme. Power consumption is minimized by using current mode reads and writes throughout the design. The resulting cache operates with an average power dissipation of 390mW at 2GHz in 1.8V, 0.18/spl mu/m bulk CMOS technology.
{"title":"A 32Kb SRAM cache using current mode operation and asynchronous wave-pipelined decoders","authors":"M. Wieckowski, M. Margala","doi":"10.1109/SOCC.2004.1362425","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362425","url":null,"abstract":"The proposed design demonstrates a new high-speed, low-power methodology in a 32 Kb SRAM cache. A fast cycle time of up to 3 GHz is accomplished by using pipelined asynchronous decoders along with a parallel local/global decoding scheme. Power consumption is minimized by using current mode reads and writes throughout the design. The resulting cache operates with an average power dissipation of 390mW at 2GHz in 1.8V, 0.18/spl mu/m bulk CMOS technology.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133430072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362388
Kyounghoi Koo, Jin-Ho Seo, Myeonglyong Ko, Jae-Whui Kim
A level shifter aimed at ultra low core voltage and wide range I/O voltage is designed using a 90nm CMOS process. Proposed level shifter uses analog circuit techniques and zero-Vt transistor with no extra process step, no static power and stable duty ratio make this level shifter suitable for ultra low core voltage and wide range I/O voltage applications. These techniques work even 0.6V core voltage, 1.65-3.6V I/O voltage within 45:55 duty ratio up to 200MHz.
{"title":"A new level shifter in ultra deep sub-micron for low to wide range voltage applications","authors":"Kyounghoi Koo, Jin-Ho Seo, Myeonglyong Ko, Jae-Whui Kim","doi":"10.1109/SOCC.2004.1362388","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362388","url":null,"abstract":"A level shifter aimed at ultra low core voltage and wide range I/O voltage is designed using a 90nm CMOS process. Proposed level shifter uses analog circuit techniques and zero-Vt transistor with no extra process step, no static power and stable duty ratio make this level shifter suitable for ultra low core voltage and wide range I/O voltage applications. These techniques work even 0.6V core voltage, 1.65-3.6V I/O voltage within 45:55 duty ratio up to 200MHz.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130810960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362348
Makoto Saen, Motohiro Nakagawa, J. Nishimoto, Tomoyuki Kodama, F. Arakawa
An on-chip analysis technique for SOC, which enables system performance to be improved, was developed. The key to this technique is the synchronized analysis of the whole SOC. This is made possible by a circuit structure in which small circuits for analysis are distributed at points on the SOC to be analyzed, and these circuits operate in synchronization through a special network. Benchmarks for multimedia operations (including MPEG encoding) show that this analysis enables us to improve system performance by 17% with minimum trial-and-error. In addition, it was confirmed that the negative impact on chip area when applying this technique is very small. And it is concluded that SOC design time can be shortened during the system-development stage by using this technique.
{"title":"Transparent SOC: on-chip analyzing techniques and implementation for embedded processor","authors":"Makoto Saen, Motohiro Nakagawa, J. Nishimoto, Tomoyuki Kodama, F. Arakawa","doi":"10.1109/SOCC.2004.1362348","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362348","url":null,"abstract":"An on-chip analysis technique for SOC, which enables system performance to be improved, was developed. The key to this technique is the synchronized analysis of the whole SOC. This is made possible by a circuit structure in which small circuits for analysis are distributed at points on the SOC to be analyzed, and these circuits operate in synchronization through a special network. Benchmarks for multimedia operations (including MPEG encoding) show that this analysis enables us to improve system performance by 17% with minimum trial-and-error. In addition, it was confirmed that the negative impact on chip area when applying this technique is very small. And it is concluded that SOC design time can be shortened during the system-development stage by using this technique.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131379698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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