Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425780
Woonghee Lee, N. Akahane, S. Adachi, K. Mizobuchi, S. Sugawa
We discuss results of the design and operations of a CMOS image sensor with high S/N ratio while keeping wide dynamic range. Readout gains and input-referred noises of the image sensor are improved by actively using a pixel source follower feedback operation. A 1/4-inch 5.6 mum times 5.6 mum pixel VGA color CMOS image sensor with a lateral overflow integration capacitor in pixel in a 0.18 mum 2P3M CMOS process achieves about 1.7 times the gain compared with the case where the feedback operation is not positively used, resulting in a high input-referred conversion gain exceeded 200 muV/e-, a low input-referred noise below 2 e- without column amplifier and a high full well capacity of about 1.3 times 105 e-.
讨论了高信噪比、宽动态范围CMOS图像传感器的设计和工作结果。通过主动采用像素源从动器反馈操作，提高了图像传感器的读出增益和输入参考噪声。1/4英寸5.6 μ m × 5.6 μ m像素VGA彩色CMOS图像传感器在0.18 μ m 2P3M CMOS工艺中具有横向溢出集成电容，与不积极使用反馈操作的情况相比，其增益约为1.7倍，从而获得超过200 μ v /e-的高输入参考转换增益，低于2 μ v /e-的低输入参考噪声，以及约1.3倍105 μ e-的高满阱容量。
{"title":"A high S/N ratio and high full well capacity CMOS image sensor with active pixel readout feedback operation","authors":"Woonghee Lee, N. Akahane, S. Adachi, K. Mizobuchi, S. Sugawa","doi":"10.1109/ASSCC.2007.4425780","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425780","url":null,"abstract":"We discuss results of the design and operations of a CMOS image sensor with high S/N ratio while keeping wide dynamic range. Readout gains and input-referred noises of the image sensor are improved by actively using a pixel source follower feedback operation. A 1/4-inch 5.6 mum times 5.6 mum pixel VGA color CMOS image sensor with a lateral overflow integration capacitor in pixel in a 0.18 mum 2P3M CMOS process achieves about 1.7 times the gain compared with the case where the feedback operation is not positively used, resulting in a high input-referred conversion gain exceeded 200 muV/e-, a low input-referred noise below 2 e- without column amplifier and a high full well capacity of about 1.3 times 105 e-.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122728926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425784
Varghese George, Sanjeev Jahagirdar, Chao Tong, K. Smits, Satish Damaraju, S. Siers, Ves A. Naydenov, T. Khondker, Sanjib Sarkar, Puneet Singh
This paper describes Penryn (codename), Intel–s next generation family of processors implemented in a 45nm High-k metal gate silicon process technology and designed to meet a wide range of power envelopes and market segments. It is a dual-core, 64-bit CPU based on the Core™ microarchitecture with a unified 24-way L2 cache of 6MB. Key new features in Penryn include a Fast Radix- 16 Divider, an SSE4 instruction set, a radically new Power Management state (Deep Power Down) and Enhanced Dynamic Acceleration Technology (EDAT). Active and leakage power reduction techniques are used throughout the design to reduce power consumption while not compromising the scalability requirements. The chip is offered in various package technologies including a MCP version for the Quad-core products.
{"title":"Penryn: 45-nm next generation Intel® core™ 2 processor","authors":"Varghese George, Sanjeev Jahagirdar, Chao Tong, K. Smits, Satish Damaraju, S. Siers, Ves A. Naydenov, T. Khondker, Sanjib Sarkar, Puneet Singh","doi":"10.1109/ASSCC.2007.4425784","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425784","url":null,"abstract":"This paper describes Penryn (codename), Intel–s next generation family of processors implemented in a 45nm High-k metal gate silicon process technology and designed to meet a wide range of power envelopes and market segments. It is a dual-core, 64-bit CPU based on the Core™ microarchitecture with a unified 24-way L2 cache of 6MB. Key new features in Penryn include a Fast Radix- 16 Divider, an SSE4 instruction set, a radically new Power Management state (Deep Power Down) and Enhanced Dynamic Acceleration Technology (EDAT). Active and leakage power reduction techniques are used throughout the design to reduce power consumption while not compromising the scalability requirements. The chip is offered in various package technologies including a MCP version for the Quad-core products.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"236 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126044117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425758
Junghyun Cho, Jikon Kim, Jaewhan Kim, Kyungil Lee, Kwang-Duk Aim, Shiho Kim
A single chip NFC transceiver supporting not only NFC active and passive mode but also 13.56 MHz RFID reader and tag mode was designed and fabricated. The proposed NFC transceiver can operate as a RFID tag even without external power supply thanks to a dual antenna structure for initiator and target. The area increment due to additional target antenna is negligible because the target antenna is constructed by using a shielding layer of initiator antenna.
{"title":"An NFC transceiver with RF-powered RFID transponder mode","authors":"Junghyun Cho, Jikon Kim, Jaewhan Kim, Kyungil Lee, Kwang-Duk Aim, Shiho Kim","doi":"10.1109/ASSCC.2007.4425758","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425758","url":null,"abstract":"A single chip NFC transceiver supporting not only NFC active and passive mode but also 13.56 MHz RFID reader and tag mode was designed and fabricated. The proposed NFC transceiver can operate as a RFID tag even without external power supply thanks to a dual antenna structure for initiator and target. The area increment due to additional target antenna is negligible because the target antenna is constructed by using a shielding layer of initiator antenna.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130031635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425765
Dajiang Zhou, Peilin Liu, Ji Kong, Yunfei Zhang, Bin He, Ning Deng
In this paper, we presented an SoC based HW/SW co-design architecture for multi-standard audio decoding. It is developed to support the audio standards of AAC LC profile, Dolby AC3, Ogg Vorbis, MPEG-1 Layer 3 (MP3) and Windows Media Audio (WMA). A VLSI reconfigurable filterbank based on CORDIC algorithm is developed to accelerate the multi-standard decoding process. We designed and implemented an SoC platform to verify the interbank as an IP core. Experimental result shows that the architecture is able to perform real-time audio decoding at low frequency (typically 10.6MHz for AAC and 11.3 MHz for MP3) and the implementation cost is low (44.3k gates, 34k bytes RAM and 45k bytes data ROM for 5 audio standards). The architecture is also flexible for extending support of new formats and standards.
{"title":"An SoC based HW/SW co-design architecture for multi-standard audio decoding","authors":"Dajiang Zhou, Peilin Liu, Ji Kong, Yunfei Zhang, Bin He, Ning Deng","doi":"10.1109/ASSCC.2007.4425765","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425765","url":null,"abstract":"In this paper, we presented an SoC based HW/SW co-design architecture for multi-standard audio decoding. It is developed to support the audio standards of AAC LC profile, Dolby AC3, Ogg Vorbis, MPEG-1 Layer 3 (MP3) and Windows Media Audio (WMA). A VLSI reconfigurable filterbank based on CORDIC algorithm is developed to accelerate the multi-standard decoding process. We designed and implemented an SoC platform to verify the interbank as an IP core. Experimental result shows that the architecture is able to perform real-time audio decoding at low frequency (typically 10.6MHz for AAC and 11.3 MHz for MP3) and the implementation cost is low (44.3k gates, 34k bytes RAM and 45k bytes data ROM for 5 audio standards). The architecture is also flexible for extending support of new formats and standards.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129403924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425746
K. Kotani, T. Ito
High efficiency CMOS rectifier circuit for UHF RFID applications has been developed. The rectifier utilizes self Vth cancellation (SVC) scheme in which threshold voltage of MOSFETs is cancelled by applying gate bias voltage generated by output voltage of the rectifier itself. Very simple circuit configuration and no power dissipation feature of the scheme enable excellent power conversion efficiency (PCE) especially in small RF input power conditions. At higher RF input power conditions, PCE of the rectifier automatically decreases. This is the built-in self-power-regulation function. Proposed SVC CMOS rectifier has been fabricated with 0.35 mum CMOS process and the measured performance has been compared with other types of rectifiers. The SVC CMOS rectifier achieves 29% PCE at -9.9 dBm RF input power condition. This PCE is larger than ever reported rectifiers under the condition.
开发了用于超高频RFID应用的高效CMOS整流电路。整流器采用自v值抵消(SVC)方案，通过施加整流器自身输出电压产生的栅极偏置电压来抵消mosfet的阈值电压。该方案电路结构简单，无功耗特性，尤其在射频输入功率小的情况下具有优异的功率转换效率(PCE)。在较高的射频输入功率条件下，整流器的PCE会自动降低。这是内置的自调节功率功能。采用0.35 μ m CMOS工艺制备了SVC整流器，并与其他整流器进行了性能测试。SVC CMOS整流器在-9.9 dBm射频输入功率条件下实现29% PCE。这种PCE比以往任何报道的整流器都要大。
{"title":"High efficiency CMOS rectifier circuit with self-Vth-cancellation and power regulation functions for UHF RFIDs","authors":"K. Kotani, T. Ito","doi":"10.1109/ASSCC.2007.4425746","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425746","url":null,"abstract":"High efficiency CMOS rectifier circuit for UHF RFID applications has been developed. The rectifier utilizes self Vth cancellation (SVC) scheme in which threshold voltage of MOSFETs is cancelled by applying gate bias voltage generated by output voltage of the rectifier itself. Very simple circuit configuration and no power dissipation feature of the scheme enable excellent power conversion efficiency (PCE) especially in small RF input power conditions. At higher RF input power conditions, PCE of the rectifier automatically decreases. This is the built-in self-power-regulation function. Proposed SVC CMOS rectifier has been fabricated with 0.35 mum CMOS process and the measured performance has been compared with other types of rectifiers. The SVC CMOS rectifier achieves 29% PCE at -9.9 dBm RF input power condition. This PCE is larger than ever reported rectifiers under the condition.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116340397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425688
Chi-Chie Chang, Chi-Hong Su, Jen-Ming Wu
This paper presents the VLSI design and implementation of the baseband inner receiver for IEEE 802.16-2004 (i.e. the fixed WiMAX) OFDM mode. The design consists of low power packet detection, low complexity CORDIC-based carrier frequency compensation, recursive FFT and channel compensation. In the packet detection and carrier frequency compensation, we use sign-bit method, sliding mapping correlator, and the multiplier mapping function to achieve low complexity design. In the FFT design, we use the radix-8 memory-based recursive FFT to achieve small area design. Fabricated in TSMC 0.18 mum technology, the chip occupies 2.4 x 2.4 mm2 area and consumes about 114 mW under 1.8V power supply.1
本文介绍了ieee802.16 -2004(即固定WiMAX) OFDM模式下基带内接收机的VLSI设计与实现。该设计包括低功耗数据包检测、低复杂度cordic载波频率补偿、递归FFT和信道补偿。在包检测和载波频率补偿中，我们使用了符号位法、滑动映射相关器和乘法器映射函数来实现低复杂度的设计。在FFT设计中，我们采用基于基数8内存的递归FFT实现小面积设计。该芯片采用台积电0.18 mum工艺制造，面积为2.4 x 2.4 mm2，在1.8V电源下功耗约为114 mW
{"title":"A low power baseband OFDM receiver IC for fixed WiMAX communication","authors":"Chi-Chie Chang, Chi-Hong Su, Jen-Ming Wu","doi":"10.1109/ASSCC.2007.4425688","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425688","url":null,"abstract":"This paper presents the VLSI design and implementation of the baseband inner receiver for IEEE 802.16-2004 (i.e. the fixed WiMAX) OFDM mode. The design consists of low power packet detection, low complexity CORDIC-based carrier frequency compensation, recursive FFT and channel compensation. In the packet detection and carrier frequency compensation, we use sign-bit method, sliding mapping correlator, and the multiplier mapping function to achieve low complexity design. In the FFT design, we use the radix-8 memory-based recursive FFT to achieve small area design. Fabricated in TSMC 0.18 mum technology, the chip occupies 2.4 x 2.4 mm2 area and consumes about 114 mW under 1.8V power supply.1","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127803635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425745
Yuan Yuxiang, Y. Yoshida, T. Kuroda
This paper presents design and implementation of an inductive coupling power delivery system between stacked chips in 0.18-mum CMOS process. Two conventional high-power rectifier structures are compared, and a new topology is proposed. With a pair of fully optimized 700 mum times 700 mum on-chip inductors, the test chip achieves 10% peak efficiency and 36 mW power transmission. Compared with previous published chip-to-chip wireless power transmission systems, the received power is 13 times larger.
本文介绍了一种0.18 μ m CMOS工艺中堆叠芯片间电感耦合功率传输系统的设计与实现。比较了两种传统的大功率整流器结构，提出了一种新的拓扑结构。采用一对完全优化的700 μ m × 700 μ m片上电感，测试芯片达到10%的峰值效率和36 mW的功率传输。与之前发布的片对片无线电力传输系统相比，接收功率提高了13倍。
{"title":"Non-contact 10% efficient 36mW power delivery using on-chip inductor in 0.18-μm CMOS","authors":"Yuan Yuxiang, Y. Yoshida, T. Kuroda","doi":"10.1109/ASSCC.2007.4425745","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425745","url":null,"abstract":"This paper presents design and implementation of an inductive coupling power delivery system between stacked chips in 0.18-mum CMOS process. Two conventional high-power rectifier structures are compared, and a new topology is proposed. With a pair of fully optimized 700 mum times 700 mum on-chip inductors, the test chip achieves 10% peak efficiency and 36 mW power transmission. Compared with previous published chip-to-chip wireless power transmission systems, the received power is 13 times larger.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133636138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425726
P. Crombez, J. Craninckx, M. Steyaert
A fully reconfigurable gm-C biquadratic low-pass filter is presented with a bandwidth tunable over more than two orders of magnitude starting from 100 kHz up to 20 MHz able to cover all common wireless standards. Furthermore, power and performance can be traded thanks to a new switching technique inside Nauta's transconductor that allows changing its transconductance and input capacitance independently. Bandwidth, quality factor, noise level, linearity and common mode suppression arc all programmable over a very wide range. The circuit is realized in a 0.13 mum CMOS technology and consumes between 103 muA (100 kHz) and 11.85 mA (20 MHz) from a 1.2 V supply for a low integrated noise setting around 25 to 35 muVrms and an IIP3 of 10 dBVp giving an SFDR of 68 dB. Extra power can be saved when higher noise levels are allowed. Measurement results confirm flexibility, noise-power scaling and linearity behavior of the biquad architecture.
{"title":"A 100kHz – 20MHz reconfigurable nauta gm-C biquad low-pass filter in 0.13µm CMOS","authors":"P. Crombez, J. Craninckx, M. Steyaert","doi":"10.1109/ASSCC.2007.4425726","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425726","url":null,"abstract":"A fully reconfigurable gm-C biquadratic low-pass filter is presented with a bandwidth tunable over more than two orders of magnitude starting from 100 kHz up to 20 MHz able to cover all common wireless standards. Furthermore, power and performance can be traded thanks to a new switching technique inside Nauta's transconductor that allows changing its transconductance and input capacitance independently. Bandwidth, quality factor, noise level, linearity and common mode suppression arc all programmable over a very wide range. The circuit is realized in a 0.13 mum CMOS technology and consumes between 103 muA (100 kHz) and 11.85 mA (20 MHz) from a 1.2 V supply for a low integrated noise setting around 25 to 35 muVrms and an IIP3 of 10 dBVp giving an SFDR of 68 dB. Extra power can be saved when higher noise levels are allowed. Measurement results confirm flexibility, noise-power scaling and linearity behavior of the biquad architecture.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116610921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425777
Kilhwan Kim, Unsun Cho, Yunho Jung, Jaeseok Kim
In this paper, a biomedical processor was developed for implantable cardioverter defibrillators (ICDs), which delivers appropriate prescriptions for atrial tachycardia and fibrillation to a pacing module of ICD. The diagnosis of heart conditions is determined based on atrial electrograms (EGMs) as sensed from within the heart. The biomedical processor is implemented into a single chip including analog circuit elements. The chip is fabricated in a 0.35 mum CMOS technology, and the chip area is 3.8 times 2.7 mm2.
本文开发了一种用于植入式心律转复除颤器(ICD)的生物医学处理器，该处理器可将房性心动过速和房颤的适当处方传递给ICD的起搏模块。心脏疾病的诊断是根据心房电图(EGMs)确定的，因为从心脏内部感觉到。该生物医学处理器被实现在包含模拟电路元件的单个芯片中。该芯片采用0.35 μ m CMOS技术制造，芯片面积为3.8 × 2.7 mm2。
{"title":"Design and implementation of biomedical SoC for implantable cardioverter defibrillators","authors":"Kilhwan Kim, Unsun Cho, Yunho Jung, Jaeseok Kim","doi":"10.1109/ASSCC.2007.4425777","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425777","url":null,"abstract":"In this paper, a biomedical processor was developed for implantable cardioverter defibrillators (ICDs), which delivers appropriate prescriptions for atrial tachycardia and fibrillation to a pacing module of ICD. The diagnosis of heart conditions is determined based on atrial electrograms (EGMs) as sensed from within the heart. The biomedical processor is implemented into a single chip including analog circuit elements. The chip is fabricated in a 0.35 mum CMOS technology, and the chip area is 3.8 times 2.7 mm2.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133238062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425720
Yuan Yao, Xuefeng Yu, Dayu Yang, F. Dai, J. Irwin, R. Jaeger
A 3-bit analog-to-digital converter (ADC) for software defined radio applications that can work at a sampling rate of 20 GS/s is presented in this paper. In order to operate at Ku-band, two flash current mode logic (CML) ADCs are time-interleaved to achieve a 20 GHz sampling rate. A 3-bit current-steering digital-to-analog converter (DAC) is also designed for testing the high-speed ADC. The ADC-DAC RFIC is implemented in a 0.12 mum SiGe technology and occupies an area of 1.5 times 1.7 mm2. The total power consumption for the entire ADC-DAC chip is 2.36 W with a 4.2 V power supply. The ADC-DAC RFIC is packaged in a 44-pin CLLC package and achieves a peak spurious free dynamic range (SFDR) of 30.5 dBc and a peak effective number of bits (ENOB) of 2.8 bits at a 20 GS/s sampling rate.
{"title":"A 3-bit 20GS/s interleaved flash analog-to-digital converter in SiGe technology","authors":"Yuan Yao, Xuefeng Yu, Dayu Yang, F. Dai, J. Irwin, R. Jaeger","doi":"10.1109/ASSCC.2007.4425720","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425720","url":null,"abstract":"A 3-bit analog-to-digital converter (ADC) for software defined radio applications that can work at a sampling rate of 20 GS/s is presented in this paper. In order to operate at Ku-band, two flash current mode logic (CML) ADCs are time-interleaved to achieve a 20 GHz sampling rate. A 3-bit current-steering digital-to-analog converter (DAC) is also designed for testing the high-speed ADC. The ADC-DAC RFIC is implemented in a 0.12 mum SiGe technology and occupies an area of 1.5 times 1.7 mm2. The total power consumption for the entire ADC-DAC chip is 2.36 W with a 4.2 V power supply. The ADC-DAC RFIC is packaged in a 44-pin CLLC package and achieves a peak spurious free dynamic range (SFDR) of 30.5 dBc and a peak effective number of bits (ENOB) of 2.8 bits at a 20 GS/s sampling rate.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132974181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：