Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425779
W. Jang, O. Kwon, J. Lee, Jun‐Bo Yoon
Microelectromechanical (MEM) switch and MEM switch-based inverter was proposed and fabricated using a CMOS-compatible poly-Si surface micromachining process. The key concept is developed that the MEM switch-based inverter with the same implementation as CMOS inverter has a high noise immunity and low power dissipation because the MEM switch can clearly eliminate the leakage current when the device is off. The fabricated MEM switch showed ideal on/off characteristics with a sub-threshold swing of 4 m V/decade, an essentially zero off current, and a very high on/off current ratio over 10 s and also the MEM switch-based inverter showed ideal voltage transfer characteristics.
采用兼容cmos的多晶硅表面微加工工艺，提出并制作了微机电开关和基于微机电开关的逆变器。提出了基于MEM开关的逆变器的关键概念，其实现与CMOS逆变器相同，由于MEM开关可以在器件关闭时清晰地消除漏电流，因此具有高抗噪性和低功耗。所制备的MEM开关具有理想的开/关特性，其亚阈值摆幅为4 m V/ 10年，关断电流基本为零，在10 s内具有很高的开/关电流比，并且基于MEM开关的逆变器具有理想的电压转移特性。
{"title":"Microelectromechanical (MEM) switch and inverter for digital IC applications","authors":"W. Jang, O. Kwon, J. Lee, Jun‐Bo Yoon","doi":"10.1109/ASSCC.2007.4425779","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425779","url":null,"abstract":"Microelectromechanical (MEM) switch and MEM switch-based inverter was proposed and fabricated using a CMOS-compatible poly-Si surface micromachining process. The key concept is developed that the MEM switch-based inverter with the same implementation as CMOS inverter has a high noise immunity and low power dissipation because the MEM switch can clearly eliminate the leakage current when the device is off. The fabricated MEM switch showed ideal on/off characteristics with a sub-threshold swing of 4 m V/decade, an essentially zero off current, and a very high on/off current ratio over 10 s and also the MEM switch-based inverter showed ideal voltage transfer characteristics.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128425203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425756
Y. Eo, H. Yu, S. Song, Younghwoon Ko, Jae Young Kim
A fully integrated 2.4 GHz RF transceiver compliant with the low-power ZigBee (IEEE 802.15.4) standard is presented. The RF transceiver adopts low IF receiver and direct up-conversion transmitter. It consumes 18 mA in receive mode and 17 mA in transmit mode with 1.8-V power supply. The receiver chain IIP3 is -13.S dBm and BBA poly phase filter can reject the ACI/AACI interferers. The achieved transmitter's maximum power is 4.7 dBm and its EVM is 8.4% at 0.5 dBm output. The LO generation is achieved using frequency mixing method and thus it can prevent the VCO pulling. The die area is 2.5 mm times 2.6 mm.
{"title":"A fully integrated 2.4GHz low IF CMOS transceiver for 802.15.4 ZigBee applications","authors":"Y. Eo, H. Yu, S. Song, Younghwoon Ko, Jae Young Kim","doi":"10.1109/ASSCC.2007.4425756","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425756","url":null,"abstract":"A fully integrated 2.4 GHz RF transceiver compliant with the low-power ZigBee (IEEE 802.15.4) standard is presented. The RF transceiver adopts low IF receiver and direct up-conversion transmitter. It consumes 18 mA in receive mode and 17 mA in transmit mode with 1.8-V power supply. The receiver chain IIP3 is -13.S dBm and BBA poly phase filter can reject the ACI/AACI interferers. The achieved transmitter's maximum power is 4.7 dBm and its EVM is 8.4% at 0.5 dBm output. The LO generation is achieved using frequency mixing method and thus it can prevent the VCO pulling. The die area is 2.5 mm times 2.6 mm.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132677528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425774
J. Carnes, Gil-Cho Ahn, Un-Ku Moon
The fully differential Opamp Reset Switching Technique (ORST) for low voltage applications is presented. The technique is demonstrated in a 1V, 10-bit, 60MS/s pipelined ADC where a hybrid ORST/Switched-RC topology is adopted for improved accuracy at low voltage supplies and achieves 50dB SNDR in 0.18µm CMOS while dissipating 34mW. The architecture also uses a passive input track-and-reset to save power and has an input bandwidth greater than 90MHz.
{"title":"A 1V 10b 60MS/s Hybrid Opamp-Reset/Switched-RC pipelined ADC","authors":"J. Carnes, Gil-Cho Ahn, Un-Ku Moon","doi":"10.1109/ASSCC.2007.4425774","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425774","url":null,"abstract":"The fully differential Opamp Reset Switching Technique (ORST) for low voltage applications is presented. The technique is demonstrated in a 1V, 10-bit, 60MS/s pipelined ADC where a hybrid ORST/Switched-RC topology is adopted for improved accuracy at low voltage supplies and achieves 50dB SNDR in 0.18µm CMOS while dissipating 34mW. The architecture also uses a passive input track-and-reset to save power and has an input bandwidth greater than 90MHz.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"45 14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115406667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425701
Chi-Hsueh Wang, Chung-Chun Chen, Ming-Fong Lei, Mei-Chen Chuang, Huei Wang
This paper demonstrates a CMOS injection-locked frequency divider (ILFD) operating at 66 GHz with low dc power. The divide-by-3 ILFD is realized using 0.13-mum CMOS technology with an injection locking range of 1.5 GHz at high core current mode and a locking range of 6.3 GHz at low core current mode. To the authors' knowledge, the ILFD is the highest frequency demonstration, the widest locking range and the lowest dc power consumption of a divide-by-3 injection-locked frequency divider reported to date.
本文演示了一种低直流功率、工作频率为66 GHz的CMOS注入锁定分频器(ILFD)。该除以3的ILFD采用0.13 μ m CMOS技术实现，高核电流模式下的注入锁定范围为1.5 GHz，低核电流模式下的锁定范围为6.3 GHz。据作者所知，ILFD是迄今为止报道的频率最高、锁定范围最宽、直流功耗最低的除以3注入锁定分频器。
{"title":"A 66–72 GHz divide-by-3 injection-locked frequency divider in 0.13-μm CMOS technology","authors":"Chi-Hsueh Wang, Chung-Chun Chen, Ming-Fong Lei, Mei-Chen Chuang, Huei Wang","doi":"10.1109/ASSCC.2007.4425701","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425701","url":null,"abstract":"This paper demonstrates a CMOS injection-locked frequency divider (ILFD) operating at 66 GHz with low dc power. The divide-by-3 ILFD is realized using 0.13-mum CMOS technology with an injection locking range of 1.5 GHz at high core current mode and a locking range of 6.3 GHz at low core current mode. To the authors' knowledge, the ILFD is the highest frequency demonstration, the widest locking range and the lowest dc power consumption of a divide-by-3 injection-locked frequency divider reported to date.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115666099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425750
Shiho Kim, Junghyun Cho, Hyun-Sik Kim, Haksoo Kim, Hee-Bok Kang, Suk-Kyung Hong
A fully integrated passive and battery powered semi-active UHF RFID transponder chip supporting EPC Gen 2 protocol is presented. The proposed transponder works as a passive RFID tag when the generated RF-power is sufficient to operate, otherwise it operates in semi-active mode using battery power. The chip has re-writeable non-volatile memory bank formed by FeRAM and on-chip temperature sensor. The memory consists of EPC memory bank for EPC functionality and temperature bank for storing sensed data. The standby current in semi-active is about 0.5 muA, the lifetime in semi-active mode is in excess of 2 year with a 10 mA-hr thin film battery.
{"title":"An EPC Gen 2 compatible passive/semi-active UHF RFID transponder with embedded FeRAM and temperature sensor","authors":"Shiho Kim, Junghyun Cho, Hyun-Sik Kim, Haksoo Kim, Hee-Bok Kang, Suk-Kyung Hong","doi":"10.1109/ASSCC.2007.4425750","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425750","url":null,"abstract":"A fully integrated passive and battery powered semi-active UHF RFID transponder chip supporting EPC Gen 2 protocol is presented. The proposed transponder works as a passive RFID tag when the generated RF-power is sufficient to operate, otherwise it operates in semi-active mode using battery power. The chip has re-writeable non-volatile memory bank formed by FeRAM and on-chip temperature sensor. The memory consists of EPC memory bank for EPC functionality and temperature bank for storing sensed data. The standby current in semi-active is about 0.5 muA, the lifetime in semi-active mode is in excess of 2 year with a 10 mA-hr thin film battery.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"285 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116105050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425709
Byeong-Gyu Nam, H. Yoo
A low-power, high-performance 4-way 32-bit floating-point multifunction unit is developed for handheld 3D graphics processors. It uses logarithmic arithmetic to unify matrix, vector, and elementary functions into a single arithmetic unit. The optimal designs of logarithmic and antilogarithmic converters are presented. An adaptive number conversion scheme is proposed and it reduces total area by 15%. With this scheme, the matrix-vector multiplication (MAT), cross-product, lerp, and logarithm (logx y with 2 variables) are newly unified with the other operations. The unit achieves 2-cycle throughput for the MAT and single-cycle throughput for all other operations. It takes 451 K transistors and achieves 2.8 GFLOPS at 200 MHz with 28.5 mW power consumption.
{"title":"A 28.5mW 2.8GFLOPS floating-point multifunction unit for handheld 3D graphics processors","authors":"Byeong-Gyu Nam, H. Yoo","doi":"10.1109/ASSCC.2007.4425709","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425709","url":null,"abstract":"A low-power, high-performance 4-way 32-bit floating-point multifunction unit is developed for handheld 3D graphics processors. It uses logarithmic arithmetic to unify matrix, vector, and elementary functions into a single arithmetic unit. The optimal designs of logarithmic and antilogarithmic converters are presented. An adaptive number conversion scheme is proposed and it reduces total area by 15%. With this scheme, the matrix-vector multiplication (MAT), cross-product, lerp, and logarithm (logx y with 2 variables) are newly unified with the other operations. The unit achieves 2-cycle throughput for the MAT and single-cycle throughput for all other operations. It takes 451 K transistors and achieves 2.8 GFLOPS at 200 MHz with 28.5 mW power consumption.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116209950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425680
J. Baek, M. Sunwoo
This paper proposes a new simplified degree computationless modified Euclid's algorithm (S-DCME) and its architecture for Reed-Solomon decoders. The proposed S-DCME algorithm reformulates the existing modified Euclid's (ME) algorithm and uses new initial conditions to remove unnecessary hardware components and to use simple data paths. Thus, it requires two less multipliers and t + 2 less multiplexers compared with the reformulated inversionless Berlekamp-Massey (RiBM) algorithm which has shown the best performance so far. The critical path delay of S-DCME is 7.92 ns, i.e., TMul + TADD + TMUX, that is equal to that of RiBM. The gate count of the implemented chip using the MagnaChip HSI 0.25 mum standard cell library is 17,800.
{"title":"Low hardware complexity key equation solver chip for Reed-Solomon decoders","authors":"J. Baek, M. Sunwoo","doi":"10.1109/ASSCC.2007.4425680","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425680","url":null,"abstract":"This paper proposes a new simplified degree computationless modified Euclid's algorithm (S-DCME) and its architecture for Reed-Solomon decoders. The proposed S-DCME algorithm reformulates the existing modified Euclid's (ME) algorithm and uses new initial conditions to remove unnecessary hardware components and to use simple data paths. Thus, it requires two less multipliers and t + 2 less multiplexers compared with the reformulated inversionless Berlekamp-Massey (RiBM) algorithm which has shown the best performance so far. The critical path delay of S-DCME is 7.92 ns, i.e., TMul + TADD + TMUX, that is equal to that of RiBM. The gate count of the implemented chip using the MagnaChip HSI 0.25 mum standard cell library is 17,800.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124680519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425718
Chao Wang, Chao-Shiun Wang, Chorng-Kuang Wang
This paper presents a low power and wideband transimpedancc amplifier (TIA) design for 10 Gb/s optical receiver. Using a 0.18-mum CMOS technology, this TIA adopts a two-stage topology with inductive shunt-peaking and series-peaking techniques to optimize the power consumption and bandwidth performance. The measured -3-dB bandwidth is 8.6 GHz in the presence of a 0.15-pF photodiode capacitance. The transimpedance gain is 59 dB Omega with only 18 mW power consumption from a 1.8-V supply. The measured input referred noise current is less than 25 pA / V Hz up to 9 GHz.
提出了一种用于10gb /s光接收机的低功耗宽带跨阻放大器的设计方案。该TIA采用0.18 μ m CMOS技术，采用两级拓扑结构，采用电感并联峰值和串联峰值技术，以优化功耗和带宽性能。在0.15-pF光电二极管电容存在的情况下，测量到的-3-dB带宽为8.6 GHz。跨阻增益为59 dB ω， 1.8 v电源功耗仅为18 mW。测量输入参考噪声电流小于25 pA / V Hz，最高可达9 GHz。
{"title":"An 18-mW two-stage CMOS transimpedance amplifier for 10 Gb/s optical application","authors":"Chao Wang, Chao-Shiun Wang, Chorng-Kuang Wang","doi":"10.1109/ASSCC.2007.4425718","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425718","url":null,"abstract":"This paper presents a low power and wideband transimpedancc amplifier (TIA) design for 10 Gb/s optical receiver. Using a 0.18-mum CMOS technology, this TIA adopts a two-stage topology with inductive shunt-peaking and series-peaking techniques to optimize the power consumption and bandwidth performance. The measured -3-dB bandwidth is 8.6 GHz in the presence of a 0.15-pF photodiode capacitance. The transimpedance gain is 59 dB Omega with only 18 mW power consumption from a 1.8-V supply. The measured input referred noise current is less than 25 pA / V Hz up to 9 GHz.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128828580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425724
Chan Tat Fu, H. Luong
A new concept for quadrature coupling of LC oscillators is introduced and demonstrated in a 4.5-GHz CMOS quadrature voltage-controlled oscillator (QVCO). By employing cupacitivc coupling of second harmonic components, quadrature outputs can be obtained at a low supply voltage without extra power consumption. Fabricated in a 0.13 mum CMOS process and operated at 0.8-V supply, the proposed QVCO measures phase noise of-112dBc/Hz at 1M offset from -1.91GHz while drawing a total current of 4mA, which corresponds to a FOM of 181 dB. The core area is 0.278mm2.
介绍了LC振荡器正交耦合的新概念，并在4.5 ghz CMOS正交压控振荡器(QVCO)上进行了演示。利用二次谐波分量的空间耦合，可以在低电源电压下获得正交输出，而不需要额外的功耗。该QVCO采用0.13 μ m CMOS工艺，工作电压为0.8 v，在-1.91GHz的1M偏移处测量相位噪声为112dbc /Hz，总电流为4mA，对应于FOM为181 dB。核心面积0.278mm2。
{"title":"A 0.8-V CMOS quadrature LC VCO using capacitive coupling","authors":"Chan Tat Fu, H. Luong","doi":"10.1109/ASSCC.2007.4425724","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425724","url":null,"abstract":"A new concept for quadrature coupling of LC oscillators is introduced and demonstrated in a 4.5-GHz CMOS quadrature voltage-controlled oscillator (QVCO). By employing cupacitivc coupling of second harmonic components, quadrature outputs can be obtained at a low supply voltage without extra power consumption. Fabricated in a 0.13 mum CMOS process and operated at 0.8-V supply, the proposed QVCO measures phase noise of-112dBc/Hz at 1M offset from -1.91GHz while drawing a total current of 4mA, which corresponds to a FOM of 181 dB. The core area is 0.278mm2.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117159758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425697
Sujiang Rong, H. Luong
A transformer-feedback injection-locked divide-by-3 frequency divider (ILFD) is proposed. Employing a transformer feedback, the divider can achieve high performance in terms of low voltage, high frequency, and low power consumption. Fabricated in a 0.13-mum CMOS process and operated at a 1-V supply voltage, the divider prototype measures an input frequency range from 22.7 GHz to 25.1 GHz with 2nd and 3rd harmonic tones of -45 dBc and -40 dBc respectively. With quadrature outputs, the divider achieves a sideband rejection ratio of 40 dB while consuming 1.7 mW and occupying an active area of 0.23 mm2.
{"title":"A 1V 1.7mW 25GHz transformer-feedback divide-by-3 frequency divider with quadrature outputs","authors":"Sujiang Rong, H. Luong","doi":"10.1109/ASSCC.2007.4425697","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425697","url":null,"abstract":"A transformer-feedback injection-locked divide-by-3 frequency divider (ILFD) is proposed. Employing a transformer feedback, the divider can achieve high performance in terms of low voltage, high frequency, and low power consumption. Fabricated in a 0.13-mum CMOS process and operated at a 1-V supply voltage, the divider prototype measures an input frequency range from 22.7 GHz to 25.1 GHz with 2nd and 3rd harmonic tones of -45 dBc and -40 dBc respectively. With quadrature outputs, the divider achieves a sideband rejection ratio of 40 dB while consuming 1.7 mW and occupying an active area of 0.23 mm2.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134125562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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