Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425734
Y. Komatsu, T. Ebuchi, Takashi Hirata, T. Yoshikawa
We propose a method of reducing a quantization noise and a spectrum peak utilizing an adaptive spread spectrum clocking PLL (SSC-PLL) circuit for bi-directional and AC coupled interface. To realize a high speed, wide range, bi-directional and long cable transceiver, we designed a test chip that contained an Equalizer, CDR, and differential transceiver for long cable, and also an SSC-PLL for reducing spectrum peak with jitter optimization by adaptive bandwidth setting. Utilize this interface, it can be realized up to 810 Mbps and 20-m bi-directional transceiver system with high ESD protection, and spectrum peak reduction about -23 dB effectively with an optimum bandwidth.
{"title":"Bi-directional AC coupled interface with adaptive spread spectrum clock generator","authors":"Y. Komatsu, T. Ebuchi, Takashi Hirata, T. Yoshikawa","doi":"10.1109/ASSCC.2007.4425734","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425734","url":null,"abstract":"We propose a method of reducing a quantization noise and a spectrum peak utilizing an adaptive spread spectrum clocking PLL (SSC-PLL) circuit for bi-directional and AC coupled interface. To realize a high speed, wide range, bi-directional and long cable transceiver, we designed a test chip that contained an Equalizer, CDR, and differential transceiver for long cable, and also an SSC-PLL for reducing spectrum peak with jitter optimization by adaptive bandwidth setting. Utilize this interface, it can be realized up to 810 Mbps and 20-m bi-directional transceiver system with high ESD protection, and spectrum peak reduction about -23 dB effectively with an optimum bandwidth.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127915999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425771
Y. Kuramochi, A. Matsuzawa, M. Kawabata
We present a 10-bit 1-MS/s successive approximation analog-to-digital converter core including a charge redistribution digital-to-analog converter and a comparator. A new linearity calibration technique enables use of a nearly minimum capacitor limited by kT/C noise. The ADC core without digital blocks has been fabricated in a 0.18-mum CMOS process and consumes 110muW at 1.8 V power supply. With the calibration it achieves 9.0-dB improvement of SNDR and 23.3dB improvement of SFDR. The measured SNDR and SFDR are 51.1 dB and 69.8 dB respectively.
我们提出了一个10位1-MS/s连续近似模数转换器核心，包括电荷再分配数模转换器和比较器。一种新的线性校准技术可以使用受kT/C噪声限制的几乎最小的电容器。无数字模块的ADC核心已在0.18 μ m CMOS工艺中制造，在1.8 V电源下消耗110muW。经过标定，SNDR提高9.0 db, SFDR提高23.3dB。测量的SNDR和SFDR分别为51.1 dB和69.8 dB。
{"title":"A 0.05-mm2 110-μW 10-b self-calibrating successive approximation ADC core in 0.18-μm CMOS","authors":"Y. Kuramochi, A. Matsuzawa, M. Kawabata","doi":"10.1109/ASSCC.2007.4425771","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425771","url":null,"abstract":"We present a 10-bit 1-MS/s successive approximation analog-to-digital converter core including a charge redistribution digital-to-analog converter and a comparator. A new linearity calibration technique enables use of a nearly minimum capacitor limited by kT/C noise. The ADC core without digital blocks has been fabricated in a 0.18-mum CMOS process and consumes 110muW at 1.8 V power supply. With the calibration it achieves 9.0-dB improvement of SNDR and 23.3dB improvement of SFDR. The measured SNDR and SFDR are 51.1 dB and 69.8 dB respectively.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128836621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425736
Paritosh Bhoraskar, Y. Chiu
A 0.13-mum CMOS dual-loop digital DLL for multiphase clock generation and synchronization is presented. Ten clock phases are produced and locked to a first reference clock by the inner loop, while the outer loop further aligns all phases simultaneously to a second reference clock at a higher frequency. Unlike usual dual-loop DLLs, the proposed architecture has one loop completely enclosed inside the other, resulting in a second-order behavior. A window-based phase detection technique is exploited to minimize the circuit complexity and power with uncompromised jitter performance. The false-lock-free DLL operates over a wide frequency range of 0.2-1.2 GHz, measures a 4.6-ps rms jitter, and consumes 6.1 mW at 1.2 GHz.
提出了一种用于多相时钟产生和同步的0.13 μ m CMOS双环数字DLL。十个时钟相位由内环产生并锁定到第一个参考时钟，而外环进一步以更高的频率将所有相位同时对准第二个参考时钟。与通常的双循环dll不同，所建议的体系结构将一个循环完全封闭在另一个循环中，从而导致二阶行为。利用基于窗口的相位检测技术，在不影响抖动性能的前提下，最大限度地降低了电路的复杂度和功耗。无假锁DLL工作在0.2-1.2 GHz的宽频率范围内，测量4.6 ps有效值抖动，在1.2 GHz时消耗6.1 mW。
{"title":"A 6.1-mW dual-loop digital DLL with 4.6-ps RMS jitter using window-based phase detector","authors":"Paritosh Bhoraskar, Y. Chiu","doi":"10.1109/ASSCC.2007.4425736","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425736","url":null,"abstract":"A 0.13-mum CMOS dual-loop digital DLL for multiphase clock generation and synchronization is presented. Ten clock phases are produced and locked to a first reference clock by the inner loop, while the outer loop further aligns all phases simultaneously to a second reference clock at a higher frequency. Unlike usual dual-loop DLLs, the proposed architecture has one loop completely enclosed inside the other, resulting in a second-order behavior. A window-based phase detection technique is exploited to minimize the circuit complexity and power with uncompromised jitter performance. The false-lock-free DLL operates over a wide frequency range of 0.2-1.2 GHz, measures a 4.6-ps rms jitter, and consumes 6.1 mW at 1.2 GHz.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115952187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425683
Chi Zhang, E. Ofner
This paper describes a decimation processor for a dual-mode sigma-delta ADC for GSM and UMTS mobile standards. Partly contradictory requirements like high dynamic range and low bandwidth for GSM and vice versa for UMTS need decimation factors of M=144 (GSM) and M=8 (UMTS). A multi-rate filter architecture, which allows best hardware re-use for both mobile standards, is selected. Since the ADC is to be integrated into the power management component of the mobile terminal utilizing a 0.35 mum CMOS technology, special attention has been given to silicon area and power consumption of the component, while maintaining a standard design flow for the implementation. The processor covers 1.13 mm2 of silicon and consumes 4.72 mW in GSM and 5.54 mW in UMTS mode, both at Vdd=2.5 V.
{"title":"A 2.5V, 5mW UMTS and GSM dual mode decimation filter for sigma delta ADC","authors":"Chi Zhang, E. Ofner","doi":"10.1109/ASSCC.2007.4425683","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425683","url":null,"abstract":"This paper describes a decimation processor for a dual-mode sigma-delta ADC for GSM and UMTS mobile standards. Partly contradictory requirements like high dynamic range and low bandwidth for GSM and vice versa for UMTS need decimation factors of M=144 (GSM) and M=8 (UMTS). A multi-rate filter architecture, which allows best hardware re-use for both mobile standards, is selected. Since the ADC is to be integrated into the power management component of the mobile terminal utilizing a 0.35 mum CMOS technology, special attention has been given to silicon area and power consumption of the component, while maintaining a standard design flow for the implementation. The processor covers 1.13 mm2 of silicon and consumes 4.72 mW in GSM and 5.54 mW in UMTS mode, both at Vdd=2.5 V.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114774318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425752
Jeong-Kyoum Kim, Jaeha Kim, Sangyoon Lee, Suhwan Kim, D. Jeong
This paper presents a frequency divider with a wide operating frequency range and a high bandwidth CML buffer intended for an 80-Gb/s serial link system. The proposed divider uses a pulsed-latch architecture that replaces the slave latch in a flip-flop-based divider with a buffer. The CML buffer employs both shunt-and-double-series inductive peaking and active feedback. Implemented in a 0.13-mum CMOS process with fT of only 82 GHz, the divider operates over a wide range of 26.5-37.S GHz with an input sensitivity of 1 Vpp, diff and produces a nominal output swing of 1 Vpp, diff. The CML buffer achieves a -3 dB bandwidth of 73.5 GHz in simulation, which is high enough to buffer an 80-Gb/s NRZ data stream. The fabricated frequency divider and clock buffers dissipate 22.5 mW and 72 mW, respectively, from a 1.8-V supply.
本文提出了一种适用于80gb /s串行链路系统的宽工作频率范围和高带宽CML缓冲的分频器。所提出的分频器采用脉冲锁存器架构，用缓冲器取代基于触发器的分频器中的从锁存器。CML缓冲器采用并联和双串联感应峰值和有源反馈。在0.13 μ m CMOS工艺中实现，fT仅为82 GHz，分频器在26.5-37的宽范围内工作。CML缓冲器的输入灵敏度为1 Vpp, diff，输出摆幅为1 Vpp, diff。仿真结果表明，CML缓冲器的-3 dB带宽为73.5 GHz，足以缓冲80 gb / S NRZ数据流。制造的分频器和时钟缓冲器分别从1.8 v电源耗散22.5 mW和72 mW。
{"title":"A 26.5–37.5 GHz frequency divider and a 73-GHz-BW CML buffer in 0.13μm CMOS","authors":"Jeong-Kyoum Kim, Jaeha Kim, Sangyoon Lee, Suhwan Kim, D. Jeong","doi":"10.1109/ASSCC.2007.4425752","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425752","url":null,"abstract":"This paper presents a frequency divider with a wide operating frequency range and a high bandwidth CML buffer intended for an 80-Gb/s serial link system. The proposed divider uses a pulsed-latch architecture that replaces the slave latch in a flip-flop-based divider with a buffer. The CML buffer employs both shunt-and-double-series inductive peaking and active feedback. Implemented in a 0.13-mum CMOS process with fT of only 82 GHz, the divider operates over a wide range of 26.5-37.S GHz with an input sensitivity of 1 Vpp, diff and produces a nominal output swing of 1 Vpp, diff. The CML buffer achieves a -3 dB bandwidth of 73.5 GHz in simulation, which is high enough to buffer an 80-Gb/s NRZ data stream. The fabricated frequency divider and clock buffers dissipate 22.5 mW and 72 mW, respectively, from a 1.8-V supply.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128066472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425692
Gil-Su Kim, Chulwoo Kim, Soo-Won Kim
A 60 MHz to 1.8 GHz frequency-to-voltage converter (FVC)-based clock generator is fabricated in a 0.18-mum CMOS process for portable SoC processors. The clock generator employs the FVC and a VCO to reduce power and jitter simultaneously, which achieves spurious tone of -54.1 dBc, rms jitter of 1.497 ps and peak-to-peak jitter of 14.4 mW at 1.8 V supply.
基于频率电压转换器(FVC)的60 MHz至1.8 GHz时钟发生器采用0.18 μ m CMOS工艺制造，用于便携式SoC处理器。时钟发生器采用FVC和VCO同时降低功率和抖动，在1.8 V电源下实现了-54.1 dBc的杂散音、1.497 ps的有效值抖动和14.4 mW的峰对峰抖动。
{"title":"A low spurious 14.4mW 1.8GHz CMOS FVC-based clock generator for portable SoC processors","authors":"Gil-Su Kim, Chulwoo Kim, Soo-Won Kim","doi":"10.1109/ASSCC.2007.4425692","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425692","url":null,"abstract":"A 60 MHz to 1.8 GHz frequency-to-voltage converter (FVC)-based clock generator is fabricated in a 0.18-mum CMOS process for portable SoC processors. The clock generator employs the FVC and a VCO to reduce power and jitter simultaneously, which achieves spurious tone of -54.1 dBc, rms jitter of 1.497 ps and peak-to-peak jitter of 14.4 mW at 1.8 V supply.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127304894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425739
Youchun Liao, Zhangwen Tang, Hao Min
A differential high linearity low-noise amplifier (LNA) based on a capacitor-cross-coupled topology is presented in this paper. An off-chip balun is used for providing DC-bias and canceling the channel thermal noise of the transconductance MOS transistors. The LNA uses NMOS load and provides an extra signal feed-forward and noise-canceling path. Analysis shows that the noise contribution of the transconductance MOST is only gamma/20 and the noise figure (NF) of the proposed LNA is 1 + 0.2gamma. The chip is implemented in a 0.18-mum MMRF CMOS process. Measured results show that in 50 M-860 MHz frequency range, the LNA achieved 15 dB gain, 2.5 dB NF, 8.3 dBm IIP3 and consumes only 4 mA current from a 1.8-V supply.
提出了一种基于电容交叉耦合拓扑结构的差分高线性低噪声放大器。片外平衡器用于提供直流偏置和消除跨导MOS晶体管的通道热噪声。LNA采用NMOS负载，并提供额外的信号前馈和消噪路径。分析表明，跨导MOST的噪声贡献仅为gamma/20，所提LNA的噪声系数(NF)为1 + 0.2gamma。该芯片采用0.18 μ m MMRF CMOS工艺实现。测量结果表明，在50 m - 860mhz频率范围内，LNA可实现15 dB增益，2.5 dB NF, 8.3 dBm IIP3，并且仅消耗来自1.8 v电源的4 mA电流。
{"title":"A CMOS wide-band low-noise amplifier with balun-based noise-canceling technique","authors":"Youchun Liao, Zhangwen Tang, Hao Min","doi":"10.1109/ASSCC.2007.4425739","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425739","url":null,"abstract":"A differential high linearity low-noise amplifier (LNA) based on a capacitor-cross-coupled topology is presented in this paper. An off-chip balun is used for providing DC-bias and canceling the channel thermal noise of the transconductance MOS transistors. The LNA uses NMOS load and provides an extra signal feed-forward and noise-canceling path. Analysis shows that the noise contribution of the transconductance MOST is only gamma/20 and the noise figure (NF) of the proposed LNA is 1 + 0.2gamma. The chip is implemented in a 0.18-mum MMRF CMOS process. Measured results show that in 50 M-860 MHz frequency range, the LNA achieved 15 dB gain, 2.5 dB NF, 8.3 dBm IIP3 and consumes only 4 mA current from a 1.8-V supply.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124238619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425772
You-Kuang Chang, Chao-Shiun Wang, Chorng-Kuang Wang
This paper presents a successive approximation register analog-to-digital converter (SAR ADC) design for bio-medical applications. An energy-saving switching sequence technique is proposed to achieve low power consumption. The average switching energy of the capacitor array can be reduced by 56% compared to a conventional switching method. The measured signal-to-noise-and-distortion ratios of the ADC is 46.92 dB at 500 KS/s sampling rate with an ultra-low power consumption of only 7.75-muW from a 1-V supply voltage. The ADC is fabricated in a 0.18-mum CMOS technology.
提出了一种用于生物医学应用的逐次逼近寄存器模数转换器(SAR ADC)设计。为了实现低功耗，提出了一种节能开关顺序技术。与传统的开关方法相比，该电容器阵列的平均开关能量可降低56%。在500 KS/s采样率下，ADC的信噪比和失真比为46.92 dB，在1 v电源电压下，功耗仅为7.75 muw。该ADC采用0.18 μ m CMOS技术制造。
{"title":"A 8-bit 500-KS/s low power SAR ADC for bio-medical applications","authors":"You-Kuang Chang, Chao-Shiun Wang, Chorng-Kuang Wang","doi":"10.1109/ASSCC.2007.4425772","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425772","url":null,"abstract":"This paper presents a successive approximation register analog-to-digital converter (SAR ADC) design for bio-medical applications. An energy-saving switching sequence technique is proposed to achieve low power consumption. The average switching energy of the capacitor array can be reduced by 56% compared to a conventional switching method. The measured signal-to-noise-and-distortion ratios of the ADC is 46.92 dB at 500 KS/s sampling rate with an ultra-low power consumption of only 7.75-muW from a 1-V supply voltage. The ADC is fabricated in a 0.18-mum CMOS technology.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131538073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425678
M. Takada, S. Shibahara, K. Hayase, T. Kamei, Y. Yoshida, K. Takada, N. Irie, O. Nishii, T. Hattori
We have developed an embedded processor that supports asymmetric multiple processor (AQMP), symmetric multiple processor (SMP), and an AMP/SMP hybrid system. It contains four SH-X3 cores used to support cache coherency from that obtained using an SH-X2 core. In this paper, we evaluate the following three techniques to improve the processing performance and reduce the power consumption in parallel processing in the processor. The first technique is snoop controller (SiNC) to improve cache coherency performance. The performance overhead by snoop is decreased up to 0.1% when SPLASH-2 is executed. The second technique is detection and resolution of synonym problems so that we may not use the page coloring for page table management. The processes handling time in Linux is reduced by 29.4% compared with the case solved the problem with software. The third technique is the individual core clock frequency and the light sleep mode which is used to maintain the cache coherency even when the cores are stopped, to reduce the power consumption. The energy is decreased by 5.2% and 4.5%, respectively. As a result, the SH-X3 core achieved a performance that has scalability proportional to 0.72-0.93 times the number of cores and a power saving of 4.5-44.0% without increasing the execution time.
{"title":"Performance and power evaluation of SH-X3 multicore system","authors":"M. Takada, S. Shibahara, K. Hayase, T. Kamei, Y. Yoshida, K. Takada, N. Irie, O. Nishii, T. Hattori","doi":"10.1109/ASSCC.2007.4425678","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425678","url":null,"abstract":"We have developed an embedded processor that supports asymmetric multiple processor (AQMP), symmetric multiple processor (SMP), and an AMP/SMP hybrid system. It contains four SH-X3 cores used to support cache coherency from that obtained using an SH-X2 core. In this paper, we evaluate the following three techniques to improve the processing performance and reduce the power consumption in parallel processing in the processor. The first technique is snoop controller (SiNC) to improve cache coherency performance. The performance overhead by snoop is decreased up to 0.1% when SPLASH-2 is executed. The second technique is detection and resolution of synonym problems so that we may not use the page coloring for page table management. The processes handling time in Linux is reduced by 29.4% compared with the case solved the problem with software. The third technique is the individual core clock frequency and the light sleep mode which is used to maintain the cache coherency even when the cores are stopped, to reduce the power consumption. The energy is decreased by 5.2% and 4.5%, respectively. As a result, the SH-X3 core achieved a performance that has scalability proportional to 0.72-0.93 times the number of cores and a power saving of 4.5-44.0% without increasing the execution time.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131565290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425730
Poki Chen, Shi-Wei Chen, Juan-Shan Lai
A duty cycle corrector based on pulse shrinking/ stretching mechanism is presented. The proposed DCC has been rubricated in a TSMC 0.35mum standard CMOS process. An input duty cycle range of 30%~70% is achieved. The duty cycle error is within plusmn1.0% for the widest frequency operation range of 3MHz~60MHz ever fulfilled which makes the circuit best suited for ultra wide band applications. The chip area is merely 0.3 x 0.2 mm2 and the power consumption is 1. 1mW at 550 MHz.
{"title":"A low power wide tange duty cycle corrector based on pulse shrinking/stretching mechanism","authors":"Poki Chen, Shi-Wei Chen, Juan-Shan Lai","doi":"10.1109/ASSCC.2007.4425730","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425730","url":null,"abstract":"A duty cycle corrector based on pulse shrinking/ stretching mechanism is presented. The proposed DCC has been rubricated in a TSMC 0.35mum standard CMOS process. An input duty cycle range of 30%~70% is achieved. The duty cycle error is within plusmn1.0% for the widest frequency operation range of 3MHz~60MHz ever fulfilled which makes the circuit best suited for ultra wide band applications. The chip area is merely 0.3 x 0.2 mm2 and the power consumption is 1. 1mW at 550 MHz.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133971184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：