2017 Intl Conf on Advanced Control Circuits Systems (ACCS) Systems & 2017 Intl Conf on New Paradigms in Electronics & Information Technology (PEIT)最新文献
Pub Date : 2017-11-01DOI: 10.1109/ACCS-PEIT.2017.8303056
M. Salem, Yousry Atia, O. Mahgoub
Charging batteries with constant-current/constant-voltage (CCCV) scheme prolongs the battery life and improve the charging efficiency. In battery charging applications, using ultra-sparse matrix rectifier (USMR) has many advantages over the bridge rectifier circuits as it has minimum number of switches, it possesses sinusoidal input currents with controllable displacement angle by proper switching strategy. So, a unity power factor can be achieved. This paper presents the use of USMR in battery charging applications using of space vector modulation (SVM) to provide sinusoidal input currents for USMR. Also controlling of output current or voltage facilitates charging control during charging scheme to preserve the battery life. The three modes of CCCV charging scheme are trickle mode, constant current mode, and constant voltage mode. The output dc voltage of the rectifier is controlled by controlling the modulation index m for the rectifier, hence the output dc current is consequently controlled. The input side LC low-pass power filter is designed to filter out the harmonics in the input currents due to switching frequency. This type of charger is candidated for high power high charging voltage systems to improve the charging efficiency. The simulation results show that the proposed control scheme achieves sinusoidal input current with a unity power factor. Also, the total harmonic distortion in the input line current decreases as the charging current increases.
{"title":"Ultra sparse matrix rectifier for battery charging application","authors":"M. Salem, Yousry Atia, O. Mahgoub","doi":"10.1109/ACCS-PEIT.2017.8303056","DOIUrl":"https://doi.org/10.1109/ACCS-PEIT.2017.8303056","url":null,"abstract":"Charging batteries with constant-current/constant-voltage (CCCV) scheme prolongs the battery life and improve the charging efficiency. In battery charging applications, using ultra-sparse matrix rectifier (USMR) has many advantages over the bridge rectifier circuits as it has minimum number of switches, it possesses sinusoidal input currents with controllable displacement angle by proper switching strategy. So, a unity power factor can be achieved. This paper presents the use of USMR in battery charging applications using of space vector modulation (SVM) to provide sinusoidal input currents for USMR. Also controlling of output current or voltage facilitates charging control during charging scheme to preserve the battery life. The three modes of CCCV charging scheme are trickle mode, constant current mode, and constant voltage mode. The output dc voltage of the rectifier is controlled by controlling the modulation index m for the rectifier, hence the output dc current is consequently controlled. The input side LC low-pass power filter is designed to filter out the harmonics in the input currents due to switching frequency. This type of charger is candidated for high power high charging voltage systems to improve the charging efficiency. The simulation results show that the proposed control scheme achieves sinusoidal input current with a unity power factor. Also, the total harmonic distortion in the input line current decreases as the charging current increases.","PeriodicalId":187395,"journal":{"name":"2017 Intl Conf on Advanced Control Circuits Systems (ACCS) Systems & 2017 Intl Conf on New Paradigms in Electronics & Information Technology (PEIT)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127147138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/accs-peit.2017.8303062
A.I. Madi, M. Hamad, R. Hamdy, I. El-Arabawy
This paper presents a hybrid power filter compensating the harmonics of three-phase controlled converter harmonics. The HPF is composed of three-phase single-tuned passive power filter for the elimination of 5th harmonic frequency and active power filter based on modular multilevel converter. A MATLAB/Simulink simulation model is constructed to examine HPF filtering performance and its effective compensation of the controlled converter leading to better power quality.
{"title":"MMC-based HPF migitating the mediumvoltage motor harmonic currents","authors":"A.I. Madi, M. Hamad, R. Hamdy, I. El-Arabawy","doi":"10.1109/accs-peit.2017.8303062","DOIUrl":"https://doi.org/10.1109/accs-peit.2017.8303062","url":null,"abstract":"This paper presents a hybrid power filter compensating the harmonics of three-phase controlled converter harmonics. The HPF is composed of three-phase single-tuned passive power filter for the elimination of 5th harmonic frequency and active power filter based on modular multilevel converter. A MATLAB/Simulink simulation model is constructed to examine HPF filtering performance and its effective compensation of the controlled converter leading to better power quality.","PeriodicalId":187395,"journal":{"name":"2017 Intl Conf on Advanced Control Circuits Systems (ACCS) Systems & 2017 Intl Conf on New Paradigms in Electronics & Information Technology (PEIT)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125596085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ACCS-PEIT.2017.8303035
N. E. Elashkar, G. H. Ibrahim, H. Fahmy, M. Aboudina, A. Khalil
In this paper, the sensitivity of memristors on incoming periodic signal phase is studied analytically adopting linear dopant drift model and carrying transient circuit simulation. Sinusoidal, square and triangular periodic signals are considered. Some medical applications of the proved dependence of average memristance on the incoming signal phase are also proposed.
{"title":"A study on the effect of square and triangle signals phase on memristance and its applications","authors":"N. E. Elashkar, G. H. Ibrahim, H. Fahmy, M. Aboudina, A. Khalil","doi":"10.1109/ACCS-PEIT.2017.8303035","DOIUrl":"https://doi.org/10.1109/ACCS-PEIT.2017.8303035","url":null,"abstract":"In this paper, the sensitivity of memristors on incoming periodic signal phase is studied analytically adopting linear dopant drift model and carrying transient circuit simulation. Sinusoidal, square and triangular periodic signals are considered. Some medical applications of the proved dependence of average memristance on the incoming signal phase are also proposed.","PeriodicalId":187395,"journal":{"name":"2017 Intl Conf on Advanced Control Circuits Systems (ACCS) Systems & 2017 Intl Conf on New Paradigms in Electronics & Information Technology (PEIT)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122587345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ACCS-PEIT.2017.8302992
M. Elmala, A. Omar, A. Metawea, A. Ismail, A. Elmallah, A. Saeed, A. Elsayed, M. BenSaleh, A. Obeid, A. Alghofaili, I. Alzahem, S. Alshaibani, M. Alnahdi, N. ALjehani, A. Bhybha, Syed Manzoor Qasim
An electronic interface system for MEMS accelerometer is implemented in 0.18μm HVCMOS technology. The ASIC uses 7.5/12.5V to increase the net actuation force and increases the input acceleration range. The measured ASIC sensitivity is 35fF/g. Maximum measured error is 0.38% of full scale, for 0 to 5g input acceleration. This ASIC interface includes on-chip reference generation, decimation, and temperature compensation
{"title":"Electronic interface system with 7.5/12.5V actuation for MEMS accelerometer","authors":"M. Elmala, A. Omar, A. Metawea, A. Ismail, A. Elmallah, A. Saeed, A. Elsayed, M. BenSaleh, A. Obeid, A. Alghofaili, I. Alzahem, S. Alshaibani, M. Alnahdi, N. ALjehani, A. Bhybha, Syed Manzoor Qasim","doi":"10.1109/ACCS-PEIT.2017.8302992","DOIUrl":"https://doi.org/10.1109/ACCS-PEIT.2017.8302992","url":null,"abstract":"An electronic interface system for MEMS accelerometer is implemented in 0.18μm HVCMOS technology. The ASIC uses 7.5/12.5V to increase the net actuation force and increases the input acceleration range. The measured ASIC sensitivity is 35fF/g. Maximum measured error is 0.38% of full scale, for 0 to 5g input acceleration. This ASIC interface includes on-chip reference generation, decimation, and temperature compensation","PeriodicalId":187395,"journal":{"name":"2017 Intl Conf on Advanced Control Circuits Systems (ACCS) Systems & 2017 Intl Conf on New Paradigms in Electronics & Information Technology (PEIT)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121143629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ACCS-PEIT.2017.8303037
M. Eid, M. A. Mohamed
The rising attention of terrorism violations approve that applicable and accurate systems is more needed. The saved or transmitted templates increase the chance of compromise the privacy or identity breach. Due to the high accuracy level of iris identifier and the convenience and passive recognition properties of face modality, the proposed fuzzy logic fusion strategy could allow an efficient and accurate identification procedure for high-security critical applications. Towards a secure transmission and saving, a secure sketch of biometric data will be rescinded and reissued at diverse attacks points. Dissimilar to the classical systems, the introduced chaotic biometric protection system based on Henon and 2D Logistic maps could offer an imperious and speedy ciphering procedure against typical algorithms. Moreover, it could present good key sensitive properties with large key space and more robust to statistical and differential attacks. Also, being not invasive to the identification procedure, the fuzzy logic decision which taken at the matching score and the decision levels after normalization of both iris and face scores using the min-max rule introduced false accept rate of 0.0345%, and false reject rate 0.001% respectively for matching the decrypted templates.
{"title":"A secure multimodal authentication system based on chaos cryptography and fuzzy fusion of iris and face","authors":"M. Eid, M. A. Mohamed","doi":"10.1109/ACCS-PEIT.2017.8303037","DOIUrl":"https://doi.org/10.1109/ACCS-PEIT.2017.8303037","url":null,"abstract":"The rising attention of terrorism violations approve that applicable and accurate systems is more needed. The saved or transmitted templates increase the chance of compromise the privacy or identity breach. Due to the high accuracy level of iris identifier and the convenience and passive recognition properties of face modality, the proposed fuzzy logic fusion strategy could allow an efficient and accurate identification procedure for high-security critical applications. Towards a secure transmission and saving, a secure sketch of biometric data will be rescinded and reissued at diverse attacks points. Dissimilar to the classical systems, the introduced chaotic biometric protection system based on Henon and 2D Logistic maps could offer an imperious and speedy ciphering procedure against typical algorithms. Moreover, it could present good key sensitive properties with large key space and more robust to statistical and differential attacks. Also, being not invasive to the identification procedure, the fuzzy logic decision which taken at the matching score and the decision levels after normalization of both iris and face scores using the min-max rule introduced false accept rate of 0.0345%, and false reject rate 0.001% respectively for matching the decrypted templates.","PeriodicalId":187395,"journal":{"name":"2017 Intl Conf on Advanced Control Circuits Systems (ACCS) Systems & 2017 Intl Conf on New Paradigms in Electronics & Information Technology (PEIT)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131811450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ACCS-PEIT.2017.8303060
M. E. Karar
Finding volunteer patients and/or getting ethical approval for experimental studies on human participants are generally serious problems in the field of biomedical engineering. Therefore, this paper presents a new microcontroller-based phonocardiogram (PCG) signals simulator. The developed simulator generates graphical representations of normal and three diseased heart sounds; namely mitral valve insufficiency, aortic stenosis, and ventricular septal defect. Discrete wavelet transform has been used to pre-process four heart sounds datasets, in order to denoise and decompose these PCG signals to the third approximated level. The developed PCG simulator was implemented using the Arduino Due® microcontroller. The simulated PCG signals are nearly equal to the real heart signals. Therefore, they are accepted to represent different scenarios of the heart sounds with disorders clinically. Graphical microcontroller-based heart sounds simulator has been successfully developed to support biomedical engineering education and research studies in the field of physiological signals analysis.
{"title":"Practical microcontroller-based simulator of graphical heart sounds with disorders","authors":"M. E. Karar","doi":"10.1109/ACCS-PEIT.2017.8303060","DOIUrl":"https://doi.org/10.1109/ACCS-PEIT.2017.8303060","url":null,"abstract":"Finding volunteer patients and/or getting ethical approval for experimental studies on human participants are generally serious problems in the field of biomedical engineering. Therefore, this paper presents a new microcontroller-based phonocardiogram (PCG) signals simulator. The developed simulator generates graphical representations of normal and three diseased heart sounds; namely mitral valve insufficiency, aortic stenosis, and ventricular septal defect. Discrete wavelet transform has been used to pre-process four heart sounds datasets, in order to denoise and decompose these PCG signals to the third approximated level. The developed PCG simulator was implemented using the Arduino Due® microcontroller. The simulated PCG signals are nearly equal to the real heart signals. Therefore, they are accepted to represent different scenarios of the heart sounds with disorders clinically. Graphical microcontroller-based heart sounds simulator has been successfully developed to support biomedical engineering education and research studies in the field of physiological signals analysis.","PeriodicalId":187395,"journal":{"name":"2017 Intl Conf on Advanced Control Circuits Systems (ACCS) Systems & 2017 Intl Conf on New Paradigms in Electronics & Information Technology (PEIT)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115806846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ACCS-PEIT.2017.8303029
A. Omar, F. Khater, A. Shaltout
This paper presents per unit modeling of variable speed wind energy conversion system utilizing Permanent Magnet Synchronous Generator (PMSG). The per unit representation enables comparison of different sizes of the system independent on system size. The PMSG is integrated to the grid via a full scale back-to-back converter to suit the grid frequency and voltage also to control the reactive power compensation. This paper compares 1 kW and 2 MW wind turbine systems performance at different operating conditions to verify the presented model.
{"title":"Per unit modeling of wind energy conversion system based on PMSG","authors":"A. Omar, F. Khater, A. Shaltout","doi":"10.1109/ACCS-PEIT.2017.8303029","DOIUrl":"https://doi.org/10.1109/ACCS-PEIT.2017.8303029","url":null,"abstract":"This paper presents per unit modeling of variable speed wind energy conversion system utilizing Permanent Magnet Synchronous Generator (PMSG). The per unit representation enables comparison of different sizes of the system independent on system size. The PMSG is integrated to the grid via a full scale back-to-back converter to suit the grid frequency and voltage also to control the reactive power compensation. This paper compares 1 kW and 2 MW wind turbine systems performance at different operating conditions to verify the presented model.","PeriodicalId":187395,"journal":{"name":"2017 Intl Conf on Advanced Control Circuits Systems (ACCS) Systems & 2017 Intl Conf on New Paradigms in Electronics & Information Technology (PEIT)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124231606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ACCS-PEIT.2017.8302995
Muhammad Jawad Ikram, O. Abulnaja, M. Saleh, M. Al-Hashimi
Graphics processing units (GPUs) are becoming im-peccable choice for the upcoming exascale computing because of improvements in performance and power efficiency. In this paper, we propose an experimental methodology for evaluating power and energy consumption of programs executing on NVIDIA Kepler GPUs. NVIDIA Tesla K40c GPU is used in the experiments as a test platform. We applied our methodology on two commonly used high-performance computing (HPC) programs, Bitonic Mergesort (a parallel sorting program), and a matrix multiplication program. Using our methodology, power profile of any program executing on NVIDIA Kepler GPUs can be obtained to measure its peak power, average power, energy, and kernel runtime.
由于性能和功率效率的提高，图形处理单元(gpu)正在成为即将到来的百亿亿次计算的最佳选择。在本文中，我们提出了一种实验方法来评估在NVIDIA Kepler gpu上执行的程序的功耗和能耗。实验采用NVIDIA Tesla K40c GPU作为测试平台。我们将我们的方法应用于两个常用的高性能计算(HPC)程序，Bitonic归并排序(并行排序程序)和矩阵乘法程序。使用我们的方法，可以获得在NVIDIA Kepler gpu上执行的任何程序的功率概况，以测量其峰值功率，平均功率，能量和内核运行时间。
{"title":"Measuring power and energy consumption of programs running on kepler GPUs","authors":"Muhammad Jawad Ikram, O. Abulnaja, M. Saleh, M. Al-Hashimi","doi":"10.1109/ACCS-PEIT.2017.8302995","DOIUrl":"https://doi.org/10.1109/ACCS-PEIT.2017.8302995","url":null,"abstract":"Graphics processing units (GPUs) are becoming im-peccable choice for the upcoming exascale computing because of improvements in performance and power efficiency. In this paper, we propose an experimental methodology for evaluating power and energy consumption of programs executing on NVIDIA Kepler GPUs. NVIDIA Tesla K40c GPU is used in the experiments as a test platform. We applied our methodology on two commonly used high-performance computing (HPC) programs, Bitonic Mergesort (a parallel sorting program), and a matrix multiplication program. Using our methodology, power profile of any program executing on NVIDIA Kepler GPUs can be obtained to measure its peak power, average power, energy, and kernel runtime.","PeriodicalId":187395,"journal":{"name":"2017 Intl Conf on Advanced Control Circuits Systems (ACCS) Systems & 2017 Intl Conf on New Paradigms in Electronics & Information Technology (PEIT)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121220710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ACCS-PEIT.2017.8303059
Ahmed Prince, A. Abdalla, H. Dahshan, A. Rohiem
Cooperative relaying emerged as an effective method to combat the negative effects which are resulted from multipath fading, shadowing effects and path loss. Bit Error Rate (BER) has been analyzed and simulated for two different cooperative relaying, Amplify and Forward (AF) and Decode and Forward (DF), using MATLAB assuming Rayleigh flat fading channel. Practical implementation of the multihop DF cooperative relaying is built using software defined radio (SDR) platform consists of GNU Radio, Universal Software Radio Peripheral (USRP) and Single Board Computer “ODROID”. BER analysis is done to verify the proposed system performance. Based on the results of this work (simulation and practical implementation), BER of cooperative relaying communication is better than that of direct communication.
{"title":"Performance evaluation of multihop decode and forward cooperative relaying","authors":"Ahmed Prince, A. Abdalla, H. Dahshan, A. Rohiem","doi":"10.1109/ACCS-PEIT.2017.8303059","DOIUrl":"https://doi.org/10.1109/ACCS-PEIT.2017.8303059","url":null,"abstract":"Cooperative relaying emerged as an effective method to combat the negative effects which are resulted from multipath fading, shadowing effects and path loss. Bit Error Rate (BER) has been analyzed and simulated for two different cooperative relaying, Amplify and Forward (AF) and Decode and Forward (DF), using MATLAB assuming Rayleigh flat fading channel. Practical implementation of the multihop DF cooperative relaying is built using software defined radio (SDR) platform consists of GNU Radio, Universal Software Radio Peripheral (USRP) and Single Board Computer “ODROID”. BER analysis is done to verify the proposed system performance. Based on the results of this work (simulation and practical implementation), BER of cooperative relaying communication is better than that of direct communication.","PeriodicalId":187395,"journal":{"name":"2017 Intl Conf on Advanced Control Circuits Systems (ACCS) Systems & 2017 Intl Conf on New Paradigms in Electronics & Information Technology (PEIT)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131530922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ACCS-PEIT.2017.8303034
Dina M. Ellaithy, M. El-Moursy, G. Hamdy, Amal Zaki, A. Zekry
A wider range of applications are represented by logarithmic number system (LNS). For 3D graphics, large savings in power is achieved by using LNS to perform complex operations. Saving in power and size of logarithmic and antilogarithmic converters are achieved in this paper. Based on non-uniform sub-segments and piecewise straight line approximation, novel group of logarithmic and antilogarithmic converters are presented. The proposed converters attain good pattern of precision and power dissipation as compared to different latest techniques. Synthesis results for 90-nm CMOS technology are also presented. High precision with less non-uniform sub-segments are obtained. The proposed converters reduce the power dissipation and area by more than 20%, and 23%, respectively, with up to 26% cutting in relative error.
{"title":"Efficient piecewise non-uniform approximation logarithmic and antilogarithmic converters","authors":"Dina M. Ellaithy, M. El-Moursy, G. Hamdy, Amal Zaki, A. Zekry","doi":"10.1109/ACCS-PEIT.2017.8303034","DOIUrl":"https://doi.org/10.1109/ACCS-PEIT.2017.8303034","url":null,"abstract":"A wider range of applications are represented by logarithmic number system (LNS). For 3D graphics, large savings in power is achieved by using LNS to perform complex operations. Saving in power and size of logarithmic and antilogarithmic converters are achieved in this paper. Based on non-uniform sub-segments and piecewise straight line approximation, novel group of logarithmic and antilogarithmic converters are presented. The proposed converters attain good pattern of precision and power dissipation as compared to different latest techniques. Synthesis results for 90-nm CMOS technology are also presented. High precision with less non-uniform sub-segments are obtained. The proposed converters reduce the power dissipation and area by more than 20%, and 23%, respectively, with up to 26% cutting in relative error.","PeriodicalId":187395,"journal":{"name":"2017 Intl Conf on Advanced Control Circuits Systems (ACCS) Systems & 2017 Intl Conf on New Paradigms in Electronics & Information Technology (PEIT)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131576248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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