Pub Date : 2009-11-06DOI: 10.1109/AUTEST.2009.5314059
Ping-Chuan Lu, D. Glaser, G. Uygur, Susanne Weichslgartner, K. Helmreich, A. Lechner
Virtual Test (VT) is a promising technique that facilitates test development and cuts time-to-market especially for analog/mixed-signal/RF devices. While the concept has been around for more than a decade and its benefits are widely acknowledged, to date it has not become a standard technique in the day-to-day business of test development. The major difficulties are: weak integration between test environment and simulation environment, lack of flexible and sophisticated simulation library for test resource and insufficient simulation efficiency. The paper discusses solutions for addressing the gaps and presents a platform independent - yet easy integrateable Virtual Test Environment (VTE). It is achieved by following steps: first, OSA-compliance - using industry standards with wide acceptance including data format, service API and protocols to pave the way for easy integration. Second, achieving interaction with the test program by modeling test resources with software control interface, this allows simulation models to be dynamically assembled together and exchanging information with the test program during run-time. At last, modeling optimization - the models of test resources in our VTE have different abstraction levels supporting both static and dynamic assembly during dynamic test program execution. Analysis is performed with respect to accuracy vs. efficiency during model assembling phase to cut computational burden. In the end, a seamless integration of VT approach into test development flow is explained.
{"title":"Bridge the gap between simulation and test: An OSA-compliant Virtual Test Environment","authors":"Ping-Chuan Lu, D. Glaser, G. Uygur, Susanne Weichslgartner, K. Helmreich, A. Lechner","doi":"10.1109/AUTEST.2009.5314059","DOIUrl":"https://doi.org/10.1109/AUTEST.2009.5314059","url":null,"abstract":"Virtual Test (VT) is a promising technique that facilitates test development and cuts time-to-market especially for analog/mixed-signal/RF devices. While the concept has been around for more than a decade and its benefits are widely acknowledged, to date it has not become a standard technique in the day-to-day business of test development. The major difficulties are: weak integration between test environment and simulation environment, lack of flexible and sophisticated simulation library for test resource and insufficient simulation efficiency. The paper discusses solutions for addressing the gaps and presents a platform independent - yet easy integrateable Virtual Test Environment (VTE). It is achieved by following steps: first, OSA-compliance - using industry standards with wide acceptance including data format, service API and protocols to pave the way for easy integration. Second, achieving interaction with the test program by modeling test resources with software control interface, this allows simulation models to be dynamically assembled together and exchanging information with the test program during run-time. At last, modeling optimization - the models of test resources in our VTE have different abstraction levels supporting both static and dynamic assembly during dynamic test program execution. Analysis is performed with respect to accuracy vs. efficiency during model assembling phase to cut computational burden. In the end, a seamless integration of VT approach into test development flow is explained.","PeriodicalId":187421,"journal":{"name":"2009 IEEE AUTOTESTCON","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130851937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-01DOI: 10.1109/AUTEST.2009.5314061
M. Stora, S. Mann
The IEEE-P1693, Modular Integration Packaging Scaleable System (MIPSS) standard as illustrated in Figure 1, defines the electrical and mechanical specifications of a modular interconnect packaging system design for Automatic Test System (ATS). It specifically describes a building block approach based upon the integration of three elements: (1) the outer enclosure and the inner Eurocard standard mechanical chassis that forms the mechanical structure of the building block with alignment features to mate with other enclosures [building blocks]; (2) a hopeful revision of the VME eXtensions for Instrumentation (VXI) chassis and component designs, that includes consideration of an IEEE-1155 backplane modification by the VXI Consortium Technical Committee [1], to add VME VXS 41.4 PCI Express serial bus control, with protocol enhancement under 2eSST, while the IEEE-P1693 working group continues to specify a new pluggable virtual power source, and mechanical extension that couples the VXI module directly to a transition panel that connects to an UUT or test interface choice emulating DOD Interface Standards [2]; and (3) the integration of the instrument modules and UUT personalty modules into a pluggable subassembly that interfaces with the basic enclosure building block.All of which is directly applicable to current DOD ATS (Fig.1).
{"title":"Modular Interconnect Packaging for Scalable Systems (MIPSS) for ATE - IEEE-P1693 standard","authors":"M. Stora, S. Mann","doi":"10.1109/AUTEST.2009.5314061","DOIUrl":"https://doi.org/10.1109/AUTEST.2009.5314061","url":null,"abstract":"The IEEE-P1693, Modular Integration Packaging Scaleable System (MIPSS) standard as illustrated in Figure 1, defines the electrical and mechanical specifications of a modular interconnect packaging system design for Automatic Test System (ATS). It specifically describes a building block approach based upon the integration of three elements: (1) the outer enclosure and the inner Eurocard standard mechanical chassis that forms the mechanical structure of the building block with alignment features to mate with other enclosures [building blocks]; (2) a hopeful revision of the VME eXtensions for Instrumentation (VXI) chassis and component designs, that includes consideration of an IEEE-1155 backplane modification by the VXI Consortium Technical Committee [1], to add VME VXS 41.4 PCI Express serial bus control, with protocol enhancement under 2eSST, while the IEEE-P1693 working group continues to specify a new pluggable virtual power source, and mechanical extension that couples the VXI module directly to a transition panel that connects to an UUT or test interface choice emulating DOD Interface Standards [2]; and (3) the integration of the instrument modules and UUT personalty modules into a pluggable subassembly that interfaces with the basic enclosure building block.All of which is directly applicable to current DOD ATS (Fig.1).","PeriodicalId":187421,"journal":{"name":"2009 IEEE AUTOTESTCON","volume":"506 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116199419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-01DOI: 10.1109/autest.2009.5314020
C. Gorringe, I. Neag, Ron Taylor
With the many successes and benefits realized through the ATML Phase I Demo, the demo team has decided to embark on a second phase of the ATML Demo to further advance the ATML standards and to show further applications of these standards to solve real world problems. The purpose of the demonstrations is to validate the performance of the collection of ATML standards while providing key evidence showing how the ATML family of standards can advance industry and DoD objectives. The demonstration provides detailed implementations of the standards which reveal areas where enhancements could be made to the standards to facilitate their adoption on actual programs.
{"title":"ATML demonstration","authors":"C. Gorringe, I. Neag, Ron Taylor","doi":"10.1109/autest.2009.5314020","DOIUrl":"https://doi.org/10.1109/autest.2009.5314020","url":null,"abstract":"With the many successes and benefits realized through the ATML Phase I Demo, the demo team has decided to embark on a second phase of the ATML Demo to further advance the ATML standards and to show further applications of these standards to solve real world problems. The purpose of the demonstrations is to validate the performance of the collection of ATML standards while providing key evidence showing how the ATML family of standards can advance industry and DoD objectives. The demonstration provides detailed implementations of the standards which reveal areas where enhancements could be made to the standards to facilitate their adoption on actual programs.","PeriodicalId":187421,"journal":{"name":"2009 IEEE AUTOTESTCON","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131611813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-01DOI: 10.1109/autest.2009.5314082
T. Lopes, Y. Eracar
This paper describes a digital runtime environment designed to support both ATLAS and non-ATLAS control of a digital instrument. The paper provides a brief overview of the architecture and tools integrated into the runtime to assist in re-hosting and debugging
{"title":"Digital runtime","authors":"T. Lopes, Y. Eracar","doi":"10.1109/autest.2009.5314082","DOIUrl":"https://doi.org/10.1109/autest.2009.5314082","url":null,"abstract":"This paper describes a digital runtime environment designed to support both ATLAS and non-ATLAS control of a digital instrument. The paper provides a brief overview of the architecture and tools integrated into the runtime to assist in re-hosting and debugging","PeriodicalId":187421,"journal":{"name":"2009 IEEE AUTOTESTCON","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130192208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-01DOI: 10.1109/AUTEST.2009.5314004
A. Estrada
As anyone that has tried to use RF in VXI or PXI platforms can tell you, the process is not as simple as bolting various modules together, loading software, and turning on the switch. Unlike the rack and stack legacy systems, a SI (Synthetic Instrument) requires a degree of preplanning for best system performance. Although there are many variables to consider, some companies have figured out how to obtain excellent RF performance in these platforms.
{"title":"Proper frequency planning in a Synthetic Instrument RF system","authors":"A. Estrada","doi":"10.1109/AUTEST.2009.5314004","DOIUrl":"https://doi.org/10.1109/AUTEST.2009.5314004","url":null,"abstract":"As anyone that has tried to use RF in VXI or PXI platforms can tell you, the process is not as simple as bolting various modules together, loading software, and turning on the switch. Unlike the rack and stack legacy systems, a SI (Synthetic Instrument) requires a degree of preplanning for best system performance. Although there are many variables to consider, some companies have figured out how to obtain excellent RF performance in these platforms.","PeriodicalId":187421,"journal":{"name":"2009 IEEE AUTOTESTCON","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133889208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-01DOI: 10.1109/AUTEST.2009.5314084
H. Tijink, B. Schultheiss
The Royal Netherlands Air Force (RNLAF) operates several weapon systems, such as Chinook and Apache helicopters, F-16 fighters and C-130 Hercules transport aircrafts. For these weapon systems the Dutch National Aerospace Laboratory NLR performs several loads and usage monitoring programs. For these programs masses of flight and administrative data are collected and stored in multiple, heterogeneous weapon system specific databases. This paper presents the design, usage and benefits of a data integration layer that provides a uniform view on all weapon system databases.
{"title":"Reporting, visualisation and analysis of fleet life management information","authors":"H. Tijink, B. Schultheiss","doi":"10.1109/AUTEST.2009.5314084","DOIUrl":"https://doi.org/10.1109/AUTEST.2009.5314084","url":null,"abstract":"The Royal Netherlands Air Force (RNLAF) operates several weapon systems, such as Chinook and Apache helicopters, F-16 fighters and C-130 Hercules transport aircrafts. For these weapon systems the Dutch National Aerospace Laboratory NLR performs several loads and usage monitoring programs. For these programs masses of flight and administrative data are collected and stored in multiple, heterogeneous weapon system specific databases. This paper presents the design, usage and benefits of a data integration layer that provides a uniform view on all weapon system databases.","PeriodicalId":187421,"journal":{"name":"2009 IEEE AUTOTESTCON","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132147217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/autest.2009.5314057
Dale Johnson
The use of generic digital test instruments for emulating common serial bus protocols can provide benefits over dedicated bus test products, and often presents a trade-off between functionality, flexibility and cost. For example, a dedicated test instrument solution can offer more extensive test capabilities such as protocol support for controlling and analyzing traffic between a bus controller and a device under test. However, a more general-purpose solution that utilizes a digital test instrument can offer the flexibility to adapt to non-standard line rates and timing as well as supporting other digital test needs. Ultimately, the goal is to identify those instances where the clever or novel application of a general-purpose digital test tool is appropriate and provides tangible benefits. This paper presents an overview of how a general-purpose digital I/O instrument can used to support three widely used serial bus interfaces. By using a general-purpose digital I/O solution, users can potentially realize a lower cost test solution, a more compact test system footprint, multi-site test capability, a common user control interface and expandability for future requirements.
{"title":"Implementing serial bus interfaces with general purpose digital instrumentation","authors":"Dale Johnson","doi":"10.1109/autest.2009.5314057","DOIUrl":"https://doi.org/10.1109/autest.2009.5314057","url":null,"abstract":"The use of generic digital test instruments for emulating common serial bus protocols can provide benefits over dedicated bus test products, and often presents a trade-off between functionality, flexibility and cost. For example, a dedicated test instrument solution can offer more extensive test capabilities such as protocol support for controlling and analyzing traffic between a bus controller and a device under test. However, a more general-purpose solution that utilizes a digital test instrument can offer the flexibility to adapt to non-standard line rates and timing as well as supporting other digital test needs. Ultimately, the goal is to identify those instances where the clever or novel application of a general-purpose digital test tool is appropriate and provides tangible benefits. This paper presents an overview of how a general-purpose digital I/O instrument can used to support three widely used serial bus interfaces. By using a general-purpose digital I/O solution, users can potentially realize a lower cost test solution, a more compact test system footprint, multi-site test capability, a common user control interface and expandability for future requirements.","PeriodicalId":187421,"journal":{"name":"2009 IEEE AUTOTESTCON","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114077897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/autest.2009.5314005
A. Bhatia, J. Hofmeister, D. Goodman, J. Judkins
Ball Grid Array (BGA) packages have gained wide acceptance for use with FPGAs and the devices are used extensively for digital electronic designs. While these packages provide high interconnect densities, they rely upon an array of closely-spaced solder balls that are subject to cracking, oxidation and eventual failure. These solder joints can contribute to costly intermittencies that drive “No Fault Found” types of situations higher in the service depots. To overcome these intermittency problems, this paper presents a novel, stand-alone Integrated Circuit (IC) to be applied in systems for detection and isolation of intermittency faults in FPGAs. Because the detected faults are isolated before the FPGA begins to exhibit an intermittent failure, this provides more comprehensive approaches to supporting condition-based maintenance (CBM) and Enterprise Health Management (EHM) objectives for critical military/aerospace applications. Categories and Subject Description: 14 [Testing] 14.4 FPGA Testing
{"title":"Advanced testing and prognostics of Ball Grid Array (BGA) components with a stand-alone monitor IC","authors":"A. Bhatia, J. Hofmeister, D. Goodman, J. Judkins","doi":"10.1109/autest.2009.5314005","DOIUrl":"https://doi.org/10.1109/autest.2009.5314005","url":null,"abstract":"Ball Grid Array (BGA) packages have gained wide acceptance for use with FPGAs and the devices are used extensively for digital electronic designs. While these packages provide high interconnect densities, they rely upon an array of closely-spaced solder balls that are subject to cracking, oxidation and eventual failure. These solder joints can contribute to costly intermittencies that drive “No Fault Found” types of situations higher in the service depots. To overcome these intermittency problems, this paper presents a novel, stand-alone Integrated Circuit (IC) to be applied in systems for detection and isolation of intermittency faults in FPGAs. Because the detected faults are isolated before the FPGA begins to exhibit an intermittent failure, this provides more comprehensive approaches to supporting condition-based maintenance (CBM) and Enterprise Health Management (EHM) objectives for critical military/aerospace applications. Categories and Subject Description: 14 [Testing] 14.4 FPGA Testing","PeriodicalId":187421,"journal":{"name":"2009 IEEE AUTOTESTCON","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124481727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/autest.2005.1609202
R. Yazma
Test applications often require the integration of many different software technologies. This paper provides an overview of how several Windows-based technologies can be incorporated into a single application by employing a common software framework and architecture.
{"title":"Integration of software technologies into a test system","authors":"R. Yazma","doi":"10.1109/autest.2005.1609202","DOIUrl":"https://doi.org/10.1109/autest.2005.1609202","url":null,"abstract":"Test applications often require the integration of many different software technologies. This paper provides an overview of how several Windows-based technologies can be incorporated into a single application by employing a common software framework and architecture.","PeriodicalId":187421,"journal":{"name":"2009 IEEE AUTOTESTCON","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115484004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：