Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208490
M. Bernat, Z. Piotrowski
The authors developed the software tool with user's interface for designing the complete processing steps of ECG signal: from the filtering, through transformation and decision-making logic up to RR intervals analysis. The algorithm configuration function is replaced by the verification mechanism for R waves recognition efficiency. The program enables to download and process (in one or two-channel system) the signals recorded in the data files, e.g. as MAT-File formats from the test bases and signals from the real equipment (VENTUS system). The project assumption was to create the tool for the optimization of ECG signal preparation process, selection and analysis of R waves, which was achieved. Moreover, the article gives the results of the implemented algorithm efficiency as for the recognition of R waves in the ECG biological signal.
{"title":"Software tool for the analysis of components characteristic for ECG signal","authors":"M. Bernat, Z. Piotrowski","doi":"10.1109/MIXDES.2015.7208490","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208490","url":null,"abstract":"The authors developed the software tool with user's interface for designing the complete processing steps of ECG signal: from the filtering, through transformation and decision-making logic up to RR intervals analysis. The algorithm configuration function is replaced by the verification mechanism for R waves recognition efficiency. The program enables to download and process (in one or two-channel system) the signals recorded in the data files, e.g. as MAT-File formats from the test bases and signals from the real equipment (VENTUS system). The project assumption was to create the tool for the optimization of ECG signal preparation process, selection and analysis of R waves, which was achieved. Moreover, the article gives the results of the implemented algorithm efficiency as for the recognition of R waves in the ECG biological signal.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127101598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208508
M. Paun
In this paper a gradual investigation of a particular Hall sensor in SOI (“Silicon-On-Insulator”) technology is presented. The most important parameters of a specific Hall cell, based on SOI structure, are evaluated through three-dimensional physical simulations. The fact that the depth of the active silicon layer in SOI integration process is much smaller than in a regular CMOS is immediately reflected in both increased sensitivity and increased input resistance. The Hall shape is modeled after an XFAB SOI XI10 integration process. The magnetic sensors in this particular non-fully depleted SOI technology are highly suitable for high temperature applications. In order to verify its behaviour, the Hall voltage and absolute sensitivity were obtained through simulations. The temperature influence was also investigated for the considered SOI Hall cell.
本文介绍了一种特殊的霍尔传感器在SOI(“绝缘体上硅”)技术中的逐步研究。基于SOI结构的特定霍尔电池的最重要参数通过三维物理模拟进行了评估。SOI集成过程中有源硅层的深度比常规CMOS小得多，这一事实立即反映在灵敏度和输入电阻的增加上。霍尔形状是根据XFAB SOI XI10集成过程建模的。这种特殊的非完全耗尽SOI技术的磁传感器非常适合高温应用。为了验证其性能，通过仿真得到了霍尔电压和绝对灵敏度。温度对所考虑的SOI霍尔电池的影响也进行了研究。
{"title":"On the modelisation of the main characteristics of SOI Hall cells by three-dimensional physical simulations","authors":"M. Paun","doi":"10.1109/MIXDES.2015.7208508","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208508","url":null,"abstract":"In this paper a gradual investigation of a particular Hall sensor in SOI (“Silicon-On-Insulator”) technology is presented. The most important parameters of a specific Hall cell, based on SOI structure, are evaluated through three-dimensional physical simulations. The fact that the depth of the active silicon layer in SOI integration process is much smaller than in a regular CMOS is immediately reflected in both increased sensitivity and increased input resistance. The Hall shape is modeled after an XFAB SOI XI10 integration process. The magnetic sensors in this particular non-fully depleted SOI technology are highly suitable for high temperature applications. In order to verify its behaviour, the Hall voltage and absolute sensitivity were obtained through simulations. The temperature influence was also investigated for the considered SOI Hall cell.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128270076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208526
M. Ghasemzadeh, Amin Akbari, K. Hadidi
A novel high speed booth encoder is designed by utilizing a new truth table. The important advantage of this structure is its low delay with respect to the previously presented papers. Moreover, generating partial products and putting the partial products array in order are done at the same time. Simulation results applied to the Hspice software in TSMC 0.18μm technology proves that the total delay of the proposed structure is about 170ps.
{"title":"An ultra high speed booth encoder structure for fast arithmetic operations","authors":"M. Ghasemzadeh, Amin Akbari, K. Hadidi","doi":"10.1109/MIXDES.2015.7208526","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208526","url":null,"abstract":"A novel high speed booth encoder is designed by utilizing a new truth table. The important advantage of this structure is its low delay with respect to the previously presented papers. Moreover, generating partial products and putting the partial products array in order are done at the same time. Simulation results applied to the Hspice software in TSMC 0.18μm technology proves that the total delay of the proposed structure is about 170ps.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128405460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208544
Z. Jaworski
Capacitor based DACs are common designer's choice for projects realized in nanometer technologies. Designs kits provide several devices that can be used as capacitors. However, they exhibit serious differences in terms of linearity, minimum area and sensitivity to process disturbances The paper presents analysis of capacitive divider design to be used in 8-bit DAC realized in 65 nm CMOS process. Various devices utilized as capacitor are examined in order to select the most suitable one for the DAC implementation in respect to resolution, conversion time and layout area.
{"title":"Optimization of capacitive divider for 8-bit DAC realized in 65 nm CMOS process","authors":"Z. Jaworski","doi":"10.1109/MIXDES.2015.7208544","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208544","url":null,"abstract":"Capacitor based DACs are common designer's choice for projects realized in nanometer technologies. Designs kits provide several devices that can be used as capacitors. However, they exhibit serious differences in terms of linearity, minimum area and sensitivity to process disturbances The paper presents analysis of capacitive divider design to be used in 8-bit DAC realized in 65 nm CMOS process. Various devices utilized as capacitor are examined in order to select the most suitable one for the DAC implementation in respect to resolution, conversion time and layout area.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132211535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208534
P. Kmon, P. Grybos
We report on design of the amplifier dedicated to recording very low frequency biomedical signals. As the amplifier is used in multichannel integrated circuit dedicated to biomedical signals acquisition its key requirements are very low power consumption and low area occupation. The amplifier is designed in 180 nm CMOS process, occupies 58×55 μm2, and allows to set its bandwidth in the single Hz range. It is supplied from 1.8 V and is characterized by sub μW power consumption. The amplifier is controlled by 6-bit correction DAC to set bandwidth required for a given recordings. The paper presents our former measurement results and describes encountered problems. The design of amplifier is provided with emphasis on its limits. Additionally, the simulation results are also given.
{"title":"Design of the ultra low power, low area occupied amplifier for recording biomedical signals in the single Hz bandwidth","authors":"P. Kmon, P. Grybos","doi":"10.1109/MIXDES.2015.7208534","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208534","url":null,"abstract":"We report on design of the amplifier dedicated to recording very low frequency biomedical signals. As the amplifier is used in multichannel integrated circuit dedicated to biomedical signals acquisition its key requirements are very low power consumption and low area occupation. The amplifier is designed in 180 nm CMOS process, occupies 58×55 μm2, and allows to set its bandwidth in the single Hz range. It is supplied from 1.8 V and is characterized by sub μW power consumption. The amplifier is controlled by 6-bit correction DAC to set bandwidth required for a given recordings. The paper presents our former measurement results and describes encountered problems. The design of amplifier is provided with emphasis on its limits. Additionally, the simulation results are also given.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133981352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208569
K. Kasinski, R. Kleczek, R. Szczygiel, P. Otfinowski, P. Grybos
This paper presents multi-objective optimization of a front-end electronics implemented in multichannel integrated circuit for silicon sensors readout in the Silicon Tracking System in the CBM experiment at the FAIR center. We present the optimization towards low-power (<; 8 mW/channel) and low-noise while keeping the channel pitch of 58 μm and minimum number of external components required for the circuit's operation. Detailed study of the system noise (equivalent noise charge) with respect to a realistic model of the detector and interconnecting kapton microcable as well as realistic models of decoupling capacitors, wire-bonds and on-chip power distribution network are included.
{"title":"Noise optimization of the time and energy measuring ASIC for silicon tracking system","authors":"K. Kasinski, R. Kleczek, R. Szczygiel, P. Otfinowski, P. Grybos","doi":"10.1109/MIXDES.2015.7208569","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208569","url":null,"abstract":"This paper presents multi-objective optimization of a front-end electronics implemented in multichannel integrated circuit for silicon sensors readout in the Silicon Tracking System in the CBM experiment at the FAIR center. We present the optimization towards low-power (<; 8 mW/channel) and low-noise while keeping the channel pitch of 58 μm and minimum number of external components required for the circuit's operation. Detailed study of the system noise (equivalent noise charge) with respect to a realistic model of the detector and interconnecting kapton microcable as well as realistic models of decoupling capacitors, wire-bonds and on-chip power distribution network are included.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122470707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208538
Mariusz Derlecki, T. Borejko, W. Pleskacz
This paper presents a sixth-order IF polyphase band-pass filter design in 28 nm FD-SOI technology. This filter has been synthesized from a low-pass Butterworth filter prototype. The filter's bandwidth is 1.2 MHz and its center frequency is 2 MHz. A calibration technique using back-gate biasing that is available in fully depleted SOI to minimize the mismatch impact, has been also described. The two filters have been designed using two different types of transistors (regular P/NMOS and flip-well P/NMOS). The power consumption is 1.4 mW. The simulation results of the designed filter have also been presented in this paper.
{"title":"IF polyphase filter design and calibration with back-gate biasing in 28 nm FD-SOI technology","authors":"Mariusz Derlecki, T. Borejko, W. Pleskacz","doi":"10.1109/MIXDES.2015.7208538","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208538","url":null,"abstract":"This paper presents a sixth-order IF polyphase band-pass filter design in 28 nm FD-SOI technology. This filter has been synthesized from a low-pass Butterworth filter prototype. The filter's bandwidth is 1.2 MHz and its center frequency is 2 MHz. A calibration technique using back-gate biasing that is available in fully depleted SOI to minimize the mismatch impact, has been also described. The two filters have been designed using two different types of transistors (regular P/NMOS and flip-well P/NMOS). The power consumption is 1.4 mW. The simulation results of the designed filter have also been presented in this paper.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132701594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208533
R. Piesiewicz
In this paper design of critical building blocks of a 10 GHz silicon integrated circuit of an FMCW radar transceiver is reported. Specifically, design of VCO and LNA is discussed. The targeted transceiver structure will be world's first, commercially available silicon integrated circuit built in SiGe BiCMOS technology and dedicated for low-power radar applications.
{"title":"Design of building blocks of an X-band silicon integrated transceiver for FMCW radar","authors":"R. Piesiewicz","doi":"10.1109/MIXDES.2015.7208533","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208533","url":null,"abstract":"In this paper design of critical building blocks of a 10 GHz silicon integrated circuit of an FMCW radar transceiver is reported. Specifically, design of VCO and LNA is discussed. The targeted transceiver structure will be world's first, commercially available silicon integrated circuit built in SiGe BiCMOS technology and dedicated for low-power radar applications.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"27 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114025031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208585
J. Jasielski, S. Kuta, W. Kołodziejski, W. Machowski
In the paper a new architecture and implementation of the 9-bit hybrid LBDD PWM modulator for digital Class-BD audio amplifier has been proposed. First, the PCM audio signal is transformed into the requantized to 9-bit resolution DPWM data, using LBDD algorithm. Then the 9-bit DPWM data are converted into the two physical trains of PWM pulses to control the output power transistors, using two hybrid digital to time converters (HDTC). The HDTC converts 6 MSB data on the base counter method using advanced-control timers TIM1 and TIM8 of the STM32F407VGT6 microcontroller, while the remaining 4 LSB data - using a quantizer system based on the tapped voltage controlled delay line (TVCDL) put into the ADLL loop, which have been designed in 180nm CMOS technology from UMC. A basic feasibility study of proposed configuration has been performed.
{"title":"Hybrid LBDD PWM modulator for digital class-BD audio amplifier based on STM32F407VGT6 microcontroller and analog DLL","authors":"J. Jasielski, S. Kuta, W. Kołodziejski, W. Machowski","doi":"10.1109/MIXDES.2015.7208585","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208585","url":null,"abstract":"In the paper a new architecture and implementation of the 9-bit hybrid LBDD PWM modulator for digital Class-BD audio amplifier has been proposed. First, the PCM audio signal is transformed into the requantized to 9-bit resolution DPWM data, using LBDD algorithm. Then the 9-bit DPWM data are converted into the two physical trains of PWM pulses to control the output power transistors, using two hybrid digital to time converters (HDTC). The HDTC converts 6 MSB data on the base counter method using advanced-control timers TIM1 and TIM8 of the STM32F407VGT6 microcontroller, while the remaining 4 LSB data - using a quantizer system based on the tapped voltage controlled delay line (TVCDL) put into the ADLL loop, which have been designed in 180nm CMOS technology from UMC. A basic feasibility study of proposed configuration has been performed.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123790450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208597
R. Kotas, P. Marciniak, B. Sakowicz, D. Makowski, M. Czarnecki, J. Wachowicz, Radoslaw Zielinski, T. Truszkowski, M. Rosiński, A. Michalski, R. Sobiecki, G. Skrabalak, R. Talar, A. Napieralski
Cubic boron nitride is commonly used as a cutting tools material for the sake of its high hardness and wear-resistance. Pulse Plasma Sintering was proposed to decrease the production costs. This method is very attractive for industry, because it significantly decreases the costs of production. The goal of this paper is to present the control system prototype for Pulse Plasma Sintering processes based on programmable logic controller. Only sintering process with carefully controlled parameters allows to restrict the transformation of cBN into hBN and guarantee production of high-quality cubic boron nitride samples. Thus a dedicated control system was developed to control parameters and therefore to improve the production process. This paper presents also a visualisation system which allows the operator to control, monitor and analyze the production process. Prepared application consists of manual and auto operating mode.
{"title":"Control and monitoring system prototype for pulse plasma sintering process","authors":"R. Kotas, P. Marciniak, B. Sakowicz, D. Makowski, M. Czarnecki, J. Wachowicz, Radoslaw Zielinski, T. Truszkowski, M. Rosiński, A. Michalski, R. Sobiecki, G. Skrabalak, R. Talar, A. Napieralski","doi":"10.1109/MIXDES.2015.7208597","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208597","url":null,"abstract":"Cubic boron nitride is commonly used as a cutting tools material for the sake of its high hardness and wear-resistance. Pulse Plasma Sintering was proposed to decrease the production costs. This method is very attractive for industry, because it significantly decreases the costs of production. The goal of this paper is to present the control system prototype for Pulse Plasma Sintering processes based on programmable logic controller. Only sintering process with carefully controlled parameters allows to restrict the transformation of cBN into hBN and guarantee production of high-quality cubic boron nitride samples. Thus a dedicated control system was developed to control parameters and therefore to improve the production process. This paper presents also a visualisation system which allows the operator to control, monitor and analyze the production process. Prepared application consists of manual and auto operating mode.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124949485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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